Patent application number | Description | Published |
20090017139 | Iodine therapy dosing for treating medical conditions - A method for therapeutically treating medical conditions requiring chronic therapy such as fibrocystic breast disease, endometriosis, ovarian cysts, uterine fibroids and including the treatment of women considered to be at risk to breast and/or ovarian cancer without causing an overt thyroid disease by first administering to a patient a daily loading dose of molecular iodine (I | 01-15-2009 |
20150118688 | METHODS, SYSTEMS, AND DEVICES FOR DETECTING AND IDENTIFYING MICROORGANISMS IN MICROBIOLOGICAL CULTURE SAMPLES - Provided herein are methods, systems, and devices for detecting and/or identifying one or more specific microorganisms in a culture sample. Indicator particles, such as surface enhanced Raman spectroscopy (SERS)-active nanoparticles, each having associated therewith one or more specific binding members having an affinity for the one or more microorganisms of interest, can form a complex with specific microorganisms in the culture sample. Further, agitating magnetic capture particles also having associated therewith one or more specific binding members having an affinity for the one or more microorganisms of interest can be used to capture the microorganism-indicator particle complex and concentrate the complex in a localized area of an assay vessel for subsequent detection and identification. The complex can be dispersed, pelleted, and redispersed so that the culture sample can be retested a number of times during incubation so as to allow for real-time monitoring of the culture sample. | 04-30-2015 |
20150147400 | SOLID ORAL DOSAGE FORM FOR BREAST SYMPTOMS - The invention is a solid oral dosage form that is designed to deliver a supraphysiological dose of molecular iodine of 3 to 60 mg per day. The solid oral dosage form is designed to have a low risk of thyroid related adverse clinical events for patients with deficiencies of certain minerals. The solid oral dosage form includes a source of iodine, a reactive agent, and calcium or iron. The solid oral dosage form may include one or more of selenium, vitamin A, vitamin D, zinc, gamma-linolenic acid, vitamin B1, and magnesium. The solid dosage form may further comprise an enteric coating that coats ingredients that are absorbed predominantly from the intestines, such as vitamin A and D, and does not coat the source of iodine and the reactive agent. | 05-28-2015 |
20150185208 | LED ASSAY READER WITH TOUCHSCREEN CONTROL AND BARCODE SAMPLE ID - Assay devices, assay detection systems, and methods comprising same for analytical tests, medical assays, diagnostic tests, medical diagnosis, risk assessment, or quality control purposes are provided. These devices, systems, and methods are designed to be employed at the point of care, such as in emergency rooms, operating rooms, hospital laboratories and other clinical laboratories, doctor's offices, in the field, or in any situation in which a rapid and accurate result is desired. The systems and methods process samples, such as clinical, biological, or blood sample, and read data from colorimetric based biochemical assays to provide an indication of the presence or absence of a bacterial, fungal, or viral contaminants therein. The assay devices include an optical reader apparatus and barcode scanner for reading and matching the test results to identification information provided by the barcodes to facilitate ease of tracking compliant and noncompliant samples. | 07-02-2015 |
20160054307 | LED ASSAY READER WITH TOUCHSCREEN CONTROL AND BARCODE SAMPLE ID - Assay devices, assay detection systems, and methods comprising same for analytical tests, medical assays, diagnostic tests, medical diagnosis, risk assessment, or quality control purposes are provided. These devices, systems, and methods are designed to be employed at the point of care, such as in emergency rooms, operating rooms, hospital laboratories and other clinical laboratories, doctor's offices, in the field, or in any situation in which a rapid and accurate result is desired. The systems and methods process samples, such as clinical, biological, or blood sample, and read data from colorimetric based biochemical assays to provide an indication of the presence or absence of a bacterial, fungal, or viral contaminants therein. The assay devices include an optical reader apparatus and barcode scanner for reading and matching the test results to identification information provided by the barcodes to facilitate ease of tracking compliant and noncompliant samples. | 02-25-2016 |
Patent application number | Description | Published |
20100310541 | Compositions and Methods for Reducing the Toxicity of Certain Toxins - Compositions and methods for reducing the toxic effect of certain peptide toxins by administering an agent that directly or indirectly reduces disulfide bonds that are important for maintaining the toxin in an active conformation. Also described are compositions and methods for reducing the toxic effect of toxins that contain a heavy metal using an agent that destabilizes the binding of a metal ion that is important for toxin activity. | 12-09-2010 |
20110118184 | Treatments of Gastrointestinal Disorders - The present invention provides peptides that are useful for the treatment of gastrointestinal disorders. The present invention also provides compositions and methods of treating gastrointestinal disorders and pharmaceutical compositions for accomplishing the same. In some embodiments, these pharmaceutical compositions include oral dosage forms. | 05-19-2011 |
20110306125 | Protein Expression Methods - The present invention relates to compositions and methods for obtaining (e.g., expressing, isolating and/or purifying) polypeptides capable of binding to and/or activating the guanylate cyclase C receptor. | 12-15-2011 |
20130085107 | Treatments for Gastrointestinal Disorders - The present invention provides peptides that are useful for the treatment of gastrointestinal disorders. The present invention also provides compositions and methods of treating gastrointestinal disorders and pharmaceutical compositions for accomplishing the same. In some embodiments, these pharmaceutical compositions include oral dosage forms. | 04-04-2013 |
20130130995 | Treatments for Gastrointestinal Disorders - Described herein are peptides, compositions, and related methods for treating upper gastrointestinal disorders and conditions (e.g., dyspepsia, gastroparesis, post-operative gastric ileus, a functional esophageal disorder, a functional gastroduodenal disorder, gastroesophageal reflux disease (GERD), or a duodenal or stomach ulcer) as well as other conditions and disorders that are described herein. | 05-23-2013 |
20130190238 | Treatments for Gastrointestinal Disorders - The present invention features peptides, compositions, and related methods for treating gastrointestinal disorders and conditions, including but not limited to, irritable bowel syndrome (IBS), gastrointestinal motility disorders, functional gastrointestinal disorders, gastroesophageal reflux disease (GERD), duodenogastric reflux, Crohn's disease, ulcerative colitis, inflammatory bowel disease, functional heartburn, dyspepsia, visceral pain, gastroparesis, chronic intestinal pseudo-obstruction (or colonic pseudo-obstruction), disorders and conditions associated with constipation, and other conditions and disorders are described herein, using peptides and other agents that activate the guanylate cyclase C (GC-C) receptor. | 07-25-2013 |
20140024593 | Treatments of Gastrointestinal Disorders - The present invention provides peptides that are useful for the treatment of gastrointestinal disorders. The present invention also provides compositions and methods of treating gastrointestinal disorders and pharmaceutical compositions for accomplishing the same. In some embodiments, these pharmaceutical compositions include oral dosage forms. | 01-23-2014 |
20140073571 | Treatments for Gastrointestinal Disorders - The present invention features peptides, compositions, and related methods for treating gastrointestinal disorders and conditions, including but not limited to, irritable bowel syndrome (IBS), gastrointestinal motility disorders, functional gastrointestinal disorders, gastroesophageal reflux disease (GERD), duodenogastric reflux, Crohn's disease, ulcerative colitis, inflammatory bowel disease, functional heartburn, dyspepsia, visceral pain, gastroparesis, chronic intestinal pseudo-obstruction (or colonic pseudo-obstruction), disorders and conditions associated with constipation, and other conditions and disorders are described herein, using peptides and other agents that activate the guanylate cyclase C (GC-C) receptor. | 03-13-2014 |
20140179607 | Treatments for Gastrointestinal Disorders - The present invention provides peptides that are useful for the treatment of gastrointestinal disorders. The present invention also provides compositions and methods of treating gastrointestinal disorders and pharmaceutical compositions for accomplishing the same. In some embodiments, these pharmaceutical compositions include oral dosage forms. | 06-26-2014 |
20140256634 | Treatments for Gastrointestinal Disorders - Described herein are peptides, compositions, and related methods for treating upper gastrointestinal disorders and conditions (e.g., dyspepsia, gastroparesis, post-operative gastric ileus, a functional esophageal disorder, a functional gastroduodenal disorder, gastroesophageal reflux disease (GERD), or a duodenal or stomach ulcer) as well as other conditions and disorders that are described herein. | 09-11-2014 |
20140323397 | TREATMENTS FOR GASTROINTESTINAL DISORDERS - The present invention provides new uroguanylin derivatives that are useful for the treatment of gastrointestinal disorders. The present invention also provides compositions and methods of treating gastrointestinal disorders and pharmaceutical compositions for accomplishing the same. In some embodiments, these pharmaceutical compositions include oral dosage forms. | 10-30-2014 |
20140342996 | Treatments for Gastrointestinal Disorders - The present invention provides pharmaceutical compositions and methods of treating lower gastrointestinal disorders, including irritable bowel syndrome and constipation. | 11-20-2014 |
20150030697 | TREATMENTS FOR GASTROINTESTINAL DISORDERS - The present invention provides pharmaceutical compositions and methods of treating lower gastrointestinal disorders, including irritable bowel syndrome and constipation. | 01-29-2015 |
20150094265 | Treatments for Gastrointestinal Disorders - The present invention features peptides, compositions, and related methods for treating gastrointestinal disorders and conditions, including but not limited to, irritable bowel syndrome (IBS), gastrointestinal motility disorders, functional gastrointestinal disorders, gastroesophageal reflux disease (GERD), duodenogastric reflux, Crohn's disease, ulcerative colitis, inflammatory bowel disease, functional heartburn, dyspepsia, visceral pain, gastroparesis, chronic intestinal pseudo-obstruction (or colonic pseudo-obstruction), disorders and conditions associated with constipation, and other conditions and disorders are described herein. using peptides and other agents that activate the guanylate cyclase C (GC-C) receptor. | 04-02-2015 |
20150094272 | Treatments for Gastrointestinal Disorders - The present invention features peptides, compositions, and related methods for treating gastrointestinal disorders and conditions, including but not limited to, irritable bowel syndrome (IBS), gastrointestinal motility disorders, functional gastrointestinal disorders, gastroesophageal reflux disease (GERD), duodenogastric reflux, Crohn's disease, ulcerative colitis, inflammatory bowel disease, functional heartburn, dyspepsia, visceral pain, gastroparesis, chronic intestinal pseudo-obstruction (or colonic pseudo-obstruction), disorders and conditions associated with constipation, and other conditions and disorders are described herein, using peptides and other agents that activate the guanylate cyclase C (GC-C) receptor. | 04-02-2015 |
20150119328 | Treatments for Gastrointestinal Disorders - Described herein are peptides, compositions, and related methods for treating upper gastrointestinal disorders and conditions (e.g., dyspepsia, gastroparesis, post-operative gastric ileus, a functional esophageal disorder, a functional gastroduodenal disorder, gastroesophageal reflux disease (GERD), or a duodenal or stomach ulcer) as well as other conditions and disorders that are described herein. | 04-30-2015 |
Patent application number | Description | Published |
20120155474 | MESSAGING WITH FLEXIBLE TRANSMIT ORDERING - In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo. | 06-21-2012 |
20120185752 | DRAM ADDRESS PROTECTION - In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address. | 07-19-2012 |
20130097608 | Processor With Efficient Work Queuing - Work submitted to a co-processor enters through one of multiple input queues, used to provide various quality of service levels. In-memory linked-lists store work to be performed by a network services processor in response to lack of processing resources in the network services processor. The work is moved back from the in-memory inked-lists to the network services processor in response to availability of processing resources in the network services processor. | 04-18-2013 |
20130100812 | PACKET PRIORITY IN A NETWORK PROCESSOR - In a network processor, a “port-kind” identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID is implemented to assign a priority to the packet, as well as determine whether a traffic threshold is exceeded, thereby enabling a backpressure signal to limit packet traffic associated with the particular backpressure ID. | 04-25-2013 |
20130103870 | INPUT OUTPUT BRIDGING - In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge unit for packet data access with the memory that includes a second arbitration unit that is coupled with a packet input unit, a packet output unit, and the memory and is configured to receive requests from the packet input unit and receive requests from the packet output unit, and choose among the requests to send to the memory on a second memory bus. | 04-25-2013 |
20130103904 | SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS - In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time. | 04-25-2013 |
20130103909 | SYSTEM AND METHOD TO PROVIDE NON-COHERENT ACCESS TO A COHERENT MEMORY SYSTEM - In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration. | 04-25-2013 |
20130104130 | Method and Apparatus for Power Control - Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. | 04-25-2013 |
20130107711 | PACKET TRAFFIC CONTROL IN A NETWORK PROCESSOR | 05-02-2013 |
20130111073 | NETWORK PROCESSOR WITH DISTRIBUTED TRACE BUFFERS | 05-02-2013 |
20130111141 | MULTI-CORE INTERCONNECT IN A NETWORK PROCESSOR | 05-02-2013 |
20130254906 | Hardware and Software Association and Authentication - Authentication and association of hardware and software is accomplished by loading a secure code from an external memory at startup time and authenticating the program code using an authentication key. Access to full hardware and software functionality may be obtained upon authentication of the secure code. However, if the authentication of the secure code fails, an unsecure code that provides limited functionality to hardware and software resources is executed. | 09-26-2013 |
20130282942 | Input Output Bridging - In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus. | 10-24-2013 |
20140013061 | System And Method To Reduce Memory Access Latencies Using Selective Replication Across Multiple Memory Ports - In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index. | 01-09-2014 |
20140079071 | MESSAGING WITH FLEXIBLE TRANSMIT ORDERING - In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo. | 03-20-2014 |
20140317353 | Method and Apparatus for Managing Write Back Cache - A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet. | 10-23-2014 |
20140372709 | System and Method to Provide Non-Coherent Access to a Coherent Memory System - In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration. | 12-18-2014 |
20150089116 | Merged TLB Structure For Multiple Sequential Address Translations - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. | 03-26-2015 |
20150089147 | Maintenance Of Cache And Tags In A Translation Lookaside Buffer - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency. | 03-26-2015 |
20150089150 | Translation Bypass In Multi-Stage Address Translation - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address. | 03-26-2015 |
20150089184 | Collapsed Address Translation With Multiple Page Sizes - A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB. | 03-26-2015 |
20150089251 | Method and Apparatus for Managing Global Chip Power on a Multicore System on Chip - According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so. | 03-26-2015 |
20150100737 | Method And Apparatus For Conditional Storing Of Data Using A Compare-And-Swap Based Approach - According to at least one example embodiment, a method and corresponding apparatus for conditionally storing data include initiating an atomic sequence by executing, by a core processor, an instruction/operation designed to initiate an atomic sequence. Executing the instruction designed to initiate the atomic sequence includes loading content associated with a memory location into a first cache memory, and maintaining an indication of the memory location and a copy of the corresponding content loaded. A conditional storing operation is then performed, the conditional storing operation includes a compare-and-swap operation, executed by a controller associated with a second cache memory, based on the maintained copy of the content and the indication of the memory location. | 04-09-2015 |
20150100747 | Method And Apparatus For Supporting Wide Operations Using Atomic Sequences - Implementations of wide atomic sequences are achieved by augmenting a load operation designed to initiate an atomic sequence and augmenting a conditional storing operation that typically terminates the atomic sequence. The augmented load operation is designed to further allocate a memory buffer besides initiating the atomic sequence. The conditional storing operation is augmented to check the allocated memory buffer for any data stored therein. If one or more data words are detected in the memory buffer, the conditional storing operation stores the detected data word(s) and another word provided as operand in a concatenation of memory locations. The achieved wide atomic sequences enable the hardware system to support wide memory operations and wide operations in general. | 04-09-2015 |
20150249603 | PACKET OUTPUT PROCESSING - A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination. | 09-03-2015 |
20150249604 | PACKET SCHEDULING IN A NETWORK PROCESSOR - A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination. | 09-03-2015 |
20150249620 | PACKET SHAPING IN A NETWORK PROCESSOR - A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination. | 09-03-2015 |
20150253997 | Method and Apparatus for Memory Allocation in a Multi-Node System - According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet. | 09-10-2015 |
20150254104 | METHOD AND SYSTEM FOR WORK SCHEDULING IN A MULTI-CHIP SYSTEM - According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share hardware resources. According to at least one example embodiment, a method of processing work item in the multi-chip system comprises designating, by a work source component associated with a chip device, referred to as the source chip device, of the multiple chip devices, a work item to a scheduler for scheduling. The scheduler then assigns the work item to a another chip device, referred to as the destination chip device, of the multiple chip devices for processing, the scheduler is one of one or more schedulers each associated with a corresponding chip device of the multiple chip devices. | 09-10-2015 |
20150254182 | MULTI-CORE NETWORK PROCESSOR INTERCONNECT WITH MULTI-NODE CONNECTION - According to at least one example embodiment, a method of data coherence is employed within a multi-chip system to enforce cache coherence between chip devices of the multi-node system. According at least one example embodiment, a message is received by a first chip device of the multiple chip devices from a second chip device of the multiple chip devices. The message triggers invalidation of one or more copies, if any, of a data block. The data block stored in a memory attached to, or residing in, the first chip device. Upon determining that one or more remote copies of the data block are stored in one or more other chip devices, other than the first chip device, the first chip device sends one or more invalidation requests to the one or more other chip devices for invalidating the one or more remote copies of the data block. | 09-10-2015 |
20150254183 | INTER-CHIP INTERCONNECT PROTOCOL FOR A MULTI-CHIP SYSTEM - A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received. | 09-10-2015 |
20150254207 | METHOD AND SYSTEM FOR ORDERING I/O ACCESS IN A MULTI-NODE ENVIRONMENT - According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources, such as I/O devices. According to at least one example embodiment, a method of synchronizing access to an input/output (I/O) device in the multi-chip system comprises initiating, by a first agent of the multi-chip system, a first operation for accessing the I/O device, the first operation is queued, prior to execution by the I/O device, in a queue. Once the first operation is queued, an indication of such queuing is provided. Upon detecting, by a second agent of the multi-chip system, the indication of queuing the first operation in the queue, initiating a second operation to access the I/O device, the second operation is queued subsequent to the first operation in the queue. | 09-10-2015 |
20150261535 | METHOD AND APPARATUS FOR LOW LATENCY EXCHANGE OF DATA BETWEEN A PROCESSOR AND COPROCESSOR - According to at least one example embodiment, a method of processing a wide command includes storing wide command data in a first physical structure of a processor. Information associated with the wide command is determined based on the wide command data and/or a corresponding memory address range associated with the wide command. The information associated with the wide command determined includes a size of the wide command and is stored in a second physical structure of the processor. The processor causes the wide command data and the information associated with the wide command to be provided directly to a coprocessor for executing the wide command. The processor and the coprocessor may reside on a single chip device. Alternatively, the processor and the coprocessor may reside on separate chip devices in a multi-chip system. | 09-17-2015 |
20150288625 | MESSAGING WITH FLEXIBLE TRANSMIT ORDERING - In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the plurality of memories is filled, copy the at least one fragment to a memory external to the packet reception unit. | 10-08-2015 |
Patent application number | Description | Published |
20150188816 | LOOK-ASIDE PROCESSOR UNIT WITH INTERNAL AND EXTERNAL ACCESS FOR MULTICORE PROCESSORS - A method and a system embodying the method for information lookup request processing at a look-aside processor unit comprising storing a received lookup transaction request in a first buffer; rebuilding the lookup transaction request into a request packet; transmitting the request packet; receiving a packet; determining whether the received packet comprises a response packet or an exception packet; and processing the received packet in accordance with the determining is disclosed. Furthermore, a method and a system embodying the method for exception packet processing at a look-aside processor unit comprising storing at least one received lookup transaction request in a first buffer; receiving a packet; determining that the received packet comprises an exception packet; and associating the exception packet with one of the at least one stored lookup transaction request in accordance with an identifier of the first buffer is disclosed. | 07-02-2015 |
20150242655 | Apparatus and Method for Software Enabled Access to Protected Hardware Resources - A semiconductor includes a set of protected hardware resources, where at least one protected hardware resource stores a secure key. The semiconductor also includes a computation kernel and a memory to store a resource enablement module executed by the computation kernel. The resource enablement module selectively enables a protected hardware resource in response to a delivered key corresponding to the secure key. | 08-27-2015 |
20150317088 | SYSTEMS AND METHODS FOR NVME CONTROLLER VIRTUALIZATION TO SUPPORT MULTIPLE VIRTUAL MACHINES RUNNING ON A HOST - A new approach is proposed that contemplates systems and methods to virtualize a physical NVMe controller associated with a computing device or host so that every virtual machine running on the host can have its own dedicated virtual NVMe controller. First, a plurality of virtual NVMe controllers are created on a single physical NVMe controller, which is associated with one or more storage devices. Once created, the plurality of virtual NVMe controllers are provided to VMs running on the host in place of the single physical NVMe controller attached to the host, and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller. | 11-05-2015 |
20150317091 | SYSTEMS AND METHODS FOR ENABLING LOCAL CACHING FOR REMOTE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support mapping/importing remote storage devices as NVMe namespace(s) via an NVMe controller using a storage network protocol and utilizing one or more storage devices locally coupled to the NVMe controller as caches for fast access to the mapped remote storage devices. The NVMe controller exports and presents the NVMe namespace(s) of the remote storage devices to one or more VMs running on a host attached to the NVMe controller. Each of the VMs running on the host can then perform read/write operations on the logical volumes. During a write operation, data to be written to the remote storage devices by the VMs is stored in the locally coupled storage devices first before being transmitted over the network. The locally coupled storage devices may also cache data intelligently pre-fetched from the remote storage devices based on reading patterns and/or pre-configured policies of the VMs in anticipation of read operations. | 11-05-2015 |
20150317176 | SYSTEMS AND METHODS FOR ENABLING VALUE ADDED SERVICES FOR EXTENSIBLE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support a plurality of value-added services for storage operations on a plurality of remote storage devices virtualized as extensible/flexible storages and NVMe namespace(s) via an NVMe controller in real time. First, the NVMe controller virtualizes and presents the remote storage devices to one or more VMs running on a host attached to the NVMe controller as logical volumes so that each of the VMs running on the host can perform read/write operations on the emote storage devices as if they were local storage devices. The NVMe controller then monitors and meters the resources consumed by the activities/operations by the VMs to the virtualized remote storage devices as well as the data being transmitted during such operations in real time and creates analytics for billing purposes. In addition, the NVMe controller performs one or more of crypto operations, checksum operations, and compression and/or decompression operations on the data written to and/or read from the remote storage devices by the VMs as part of the value-added services to improve security, integrity, and efficient transmission of the data. | 11-05-2015 |
20150317177 | SYSTEMS AND METHODS FOR SUPPORTING MIGRATION OF VIRTUAL MACHINES ACCESSING REMOTE STORAGE DEVICES OVER NETWORK VIA NVME CONTROLLERS - A new approach is proposed that contemplates systems and methods to support (live or quiesced) migration of virtual machines (VMs) accessing a set of remote storage devices over a network via non-volatile memory express (NVMe) controllers from a current host to a destination host. At the time of the VM migration, a first virtual NVMe controller running on a first physical NVMe controller enables a first VM running on the current host to access and perform a plurality of storage operations to one or more logical volumes mapped to the remote storage devices over the network as if they were local storage volumes. During the VM migration process, the current host puts the first virtual NVMe controller serving the first VM into a quiesce state, captures and saves an image of states of the first virtual NVMe controller on the first host. A second virtual NVMe controller is then created on a second physical NVMe controller using the saved image, wherein the second virtual NVMe controller is configured to serve a second VM on the destination host and has exactly the same states as the first virtual NVMe controller. The second virtual NVMe controller then initiates and/or resumes the storage operations to the remote storage devices without being interrupted by the migration of the first VM on the first host to the second VM on the second host. | 11-05-2015 |
20150319237 | SYSTEMS AND METHODS FOR ENABLING ACCESS TO EXTENSIBLE STORAGE DEVICES OVER A NETWORK AS LOCAL STORAGE VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support extensible/flexible storage access in real time by virtualizing a plurality of remote storage devices as NVMe namespace(s) via an NVMe controller using a storage network protocol. The NVMe controller exports and presents the remote storage devices to one or more VMs running on a host attached to the NVMe controller as the NVMe namespace(s), wherein these remote storage devices appear virtually as one or more logical volumes of a collection of logical blocks in the NVMe namespace(s) to the VMs. As a result, each of the VMs running on the host can access these remote storage devices to perform read/write operations as if they were local storage devices via the NVMe namespace(s). | 11-05-2015 |
20150319243 | SYSTEMS AND METHODS FOR SUPPORTING HOT PLUGGING OF REMOTE STORAGE DEVICES ACCESSED OVER A NETWORK VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support hot plugging and/or unplugging one or more of remote storage devices virtualized as extensible/flexible storages and NVMe namespace(s) via an NVMe controller during operation. First, the NVMe controller virtualizes and presents a set of remote storage devices to one or more VMs running on a host attached to the NVMe controller as logical volumes in the NVMe namespace(s) so that each of the VMs running on the host can access these remote storage devices to perform read/write operations as if they were local storage devices. When the one or more remote storage devices are added to or removed from the set of remote storage devices based on storage space needs of the VMs, the NVMe controller updates the logical volumes in the NVMe namespace(s) accordingly and enables these remote storage devices to be hot plugged or unplugged from the plurality of remote storage devices at runtime without requiring shutting down and restarting any of the VMs, the host, and/or the NVMe controller. The VMs may then perform read/write operations on the NVMe namespace(s) updated to reflect the changes in the configuration of the set of remote storage devices dynamically without any interruption. | 11-05-2015 |
20160077740 | SYSTEMS AND METHODS FOR ENABLING LOCAL CACHING FOR REMOTE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support mapping/importing remote storage devices as NVMe namespace(s) via an NVMe controller using a storage network protocol and utilizing one or more storage devices locally coupled to the NVMe controller as caches for fast access to the mapped remote storage devices. The NVMe controller exports and presents the NVMe namespace(s) of the remote storage devices to one or more VMs running on a host attached to the NVMe controller. Each of the VMs running on the host can then perform read/write operations on the logical volumes. During a write operation, data to be written to the remote storage devices by the VMs is stored in the locally coupled storage devices first before being transmitted over the network. The locally coupled storage devices may also cache data intelligently pre-fetched from the remote storage devices based on reading patterns and/or pre-configured policies of the VMs in anticipation of read operations. | 03-17-2016 |