Patent application number | Description | Published |
20080243414 | Determining a design attribute by estimation and by calibration of estimated value - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately. | 10-02-2008 |
20110113396 | DETERMINING A DESIGN ATTRIBUTE BY ESTIMATION AND BY CALIBRATION OF ESTIMATED VALUE - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately. | 05-12-2011 |
20110252390 | AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS - Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes. | 10-13-2011 |
20110252393 | AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS - Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes. | 10-13-2011 |
20120066656 | Parallel Parasitic Processing In Static Timing Analysis - A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process. | 03-15-2012 |
20120324410 | AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANALYSIS - Modes of a circuit are merged together to reduce the number of modes. Subsets of modes are identified such that modes belonging to each subset are mergeable. A set of modes is mergeable if every pair of modes in the set is mergeable. Constraints of modes belonging to each pair of modes are compared to determine whether two modes are mergeable. To allow two modes to be merged, a constraint is transformed such that it affects the same paths in the merged mode and the first mode but excludes paths from the second mode. Determining whether two modes are mergeable may include verifying whether a clock in one mode blocks propagation of a clock in another mode and whether a value specified in a constraint in a mode is within specified tolerance of the value of a corresponding constraint in another mode. | 12-20-2012 |
20140059508 | Determining A Design Attribute By Estimation And By Calibration Of Estimated Value - A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately. | 02-27-2014 |
20160110485 | Simplifying Modes of an Electronic Circuit by Reducing Constraints - A mode of a circuit design is simplified by eliminating clocks and corresponding exceptions and timing constraints from the mode. A system receives a description of a mode of a circuit. The system identifies sets of clock pairs and corresponding exceptions associated with timing nodes of the mode, each clock pair comprising a launch clock and a capture clock and corresponding exceptions for a timing path. The system compares time intervals between an edge of the launch clock and a corresponding edge of the capture clock for the clock pairs subject to timing exceptions associated with the timing path. The system identifies certain clock pairs as critical based on the comparison of the time interval associated with each clock pair. The system simplifies the mode by eliminating non-critical clocks and corresponding exceptions and timing constraints. The modified mode is used for performing timing analysis. | 04-21-2016 |
Patent application number | Description | Published |
20100130696 | POLYISOBUTYLENES AND PROCESS FOR MAKING SAME - The present invention generally relates to alcohol-terminated polyisobutylene (PIB) compounds, and to a process for making such compounds. In one embodiment, the present invention relates to primary alcohol-terminated polyisobutylene compounds, and to a process for making such compounds. In still another embodiment, the present invention relates to polyisobutylene compounds that can be used to synthesize polyurethanes, to polyurethane compounds made via the use of such polyisobutylene compounds, and to processes for making such compounds. In yet another embodiment, the present invention relates to primary alcohol-terminated polyisobutylene compounds having two or more primary alcohol termini and to a process for making such compounds. In yet another embodiment, the present invention relates to primary terminated polyisobutylene compounds having two or more primary termini selected from amine groups or methacrylate groups. | 05-27-2010 |
20110082259 | SINGLY-TERMINATED POLYISOBUTYLENES AND PROCESS FOR MAKING SAME - The present invention generally relates to singly-terminated polyisobutylene (PIB) compounds, and to a process for making such compounds. In one embodiment, the present invention relates to singly-terminated polyisobutylene compounds that contain only one primary alcohol, amine, or methacrylate group as the single-terminating group. In another embodiment, the present invention relates to singly-terminated polyisobutylenes carrying exactly one terminal alcohol, amine, or methacrylate group, where such singly-terminated polyisobutylenes have a number average molecular weight of about 500 to about 5000 grams per mole. In still another embodiment, the present invention relates to singly-terminated polyisobutylene compounds that can be used to synthesize polyurethanes, to polyurethane compounds made via the use of such polyisobutylene compounds, and to processes for making such compounds. | 04-07-2011 |