Patent application number | Description | Published |
20100117048 | MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS - A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions. | 05-13-2010 |
20100117049 | MEMORY CELL ACCESS DEVICE HAVING A PN-JUNCTION WITH POLYCRYSTALLINE PLUG AND SINGLE-CRYSTAL SEMICONDUCTOR REGIONS - A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions. | 05-13-2010 |
20100165728 | PHASE CHANGE DEVICE HAVING TWO OR MORE SUBSTANTIAL AMORPHOUS REGIONS IN HIGH RESISTANCE STATE - Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode. | 07-01-2010 |
20100177553 | REWRITABLE MEMORY DEVICE - Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes. | 07-15-2010 |
20100265773 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 10-21-2010 |
20100321987 | MEMORY DEVICE AND METHOD FOR SENSING AND FIXING MARGIN CELLS - A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can comprise reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within a pre-specified range. The refresh process includes determining a data value stored in the selected cell, using for example a destructive read process, and refreshing the data value in the selected cell. The time interval can be measured by detecting timing within the sensing interval of a transition of voltage or current on a bit line across a threshold. | 12-23-2010 |
20100328995 | METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY - Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics. | 12-30-2010 |
20100328996 | PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES - A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions. | 12-30-2010 |
20110012192 | Vertical Channel Transistor Structure and Manufacturing Method Thereof - A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate. | 01-20-2011 |
20110049456 | PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY - A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region. | 03-03-2011 |
20110286283 | 3D TWO-BIT-PER-CELL NAND FLASH MEMORY - A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string. | 11-24-2011 |
20110317480 | PHASE CHANGE MEMORY CODING - An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit. | 12-29-2011 |
20120170359 | Phase Change Memory With Fast Write Characteristics - A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells. | 07-05-2012 |
20120193595 | COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS - A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition. | 08-02-2012 |
20120231613 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 09-13-2012 |
20120326111 | Ge-RICH GST-212 PHASE CHANGE MEMORY MATERIALS - A phase change material comprises Ge | 12-27-2012 |
20130119455 | NAND FLASH WITH NON-TRAPPING SWITCH TRANSISTORS - A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures. | 05-16-2013 |
20130234093 | COMPOSITE TARGET SPUTTERING FOR FORMING DOPED PHASE CHANGE MATERIALS - A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition. | 09-12-2013 |
20140021628 | METHOD FOR FORMING INTERLAYER CONNECTORS IN A THREE-DIMENSIONAL STACKED IC DEVICE - A method is used with an IC device including a stack of dielectric/conductive layers to form interlayer connectors extending from a surface of the device to the conductive layers. Contact openings are created through a dielectric layer to a first conductive layer. N etch masks, with 2 | 01-23-2014 |
20140119110 | PHASE CHANGE MEMORY CODING - An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit. | 05-01-2014 |
20140119127 | DIELECTRIC CHARGE TRAPPING MEMORY CELLS WITH REDUNDANCY - A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells. | 05-01-2014 |
20140217518 | CONDUCTOR STRUCTURE AND METHOD - A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. | 08-07-2014 |
20140264546 | DAMASCENE CONDUCTOR FOR 3D ARRAY - For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material. | 09-18-2014 |
20140269077 | ARRAY ARRANGEMENT FOR 3D NAND MEMORY - A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two string select structures arranged as side gates for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one string select structure arranged as a side gate for the second particular active strip. The turn-off bias includes one of a ground voltage, a non-negative voltage, and a floating condition. | 09-18-2014 |
20150076668 | CONDUCTOR WITH A PLURALITY OF VERTICAL EXTENSIONS FOR A 3D DEVICE - Conductors in a 3D circuit that include horizontal lines with a plurality of vertical extensions in high aspect ratio trenches can be formed using a two-step etching procedure. The procedure can comprise providing a substrate having a plurality of spaced-apart stacks; forming a pattern of vertical pillars in a body of conductor material between stacks; and forming a pattern of horizontal lines in the body of conductor material over stacks, the horizontal lines connecting vertical pillars in the pattern of vertical pillars. The body of conductor material can be deposited over the plurality of spaced-apart stacks. A first etch process can be used to form the pattern of vertical pillars. A second etch process can be used to form the pattern of horizontal lines. The conductors can be used as word lines or as bit lines in 3D memory. | 03-19-2015 |