Patent application number | Description | Published |
20090108870 | I/O BUFFER CIRCUIT - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 04-30-2009 |
20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 04-22-2010 |
20100277216 | I/O Buffer Circuit - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 11-04-2010 |
20110241752 | Mixed-voltage I/O buffer - A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level. | 10-06-2011 |
Patent application number | Description | Published |
20090074122 | DATA TRANSMISSION METHOD AND SYSTEM - A data transmission method for a data transmission system including a first device and a second device is disclosed. The method comprises the steps of transmitting a clock signal to synchronize the first device and the second device; transmitting a mode signal from the first device to the second device, wherein the mode signal indicates a transmission mode between the first device and the second device; and transmitting a serial data between the first device and the second device based on the clock signal, wherein the length of the serial data is determined based on the transmission mode. | 03-19-2009 |
20130111223 | ELECTRONIC DEVICE AND METHOD FOR DRIVING AN INTERNAL FUNCTION BLOCK OF A PROCESSOR OF THE ELECTRONIC DEVICE TO OPERATE IN A LINEAR REGION | 05-02-2013 |
20130207594 | PORTABLE ELECTRONIC DEVICES AND CHARGING METHOD THEREOF - A portable electronic device is provided. Connector includes the first and data pins. Processor includes input and output pins and detection pin coupled to the input pin. First resistor is coupled between the detection pin and first voltage. When the processor detects that the first and second pins of charger are coupled to the first and second data pins of the connector, the processor provides switching signal to the selector, so as to couple the first and second data pins of the connector to the input and output pins of the processor, respectively, and to provide second voltage different from the first voltage, to the second pin of the charger via the output pin. The processor obtains charging current value of the charger according to voltage of the detection pin. The charger includes second resistor coupled between the first and second pins. | 08-15-2013 |
20130322010 | PORTABLE DEVICE AND PERIPHERAL EXTENSION DOCK - An electronic device includes a housing, a connector port and a switching device. The connector port receives a peripheral device. The processor is electrically connected to the connector port and includes a detection pin and a 1-wire pin. The switching device is coupled between the connector port and the processor to selectively connect the connector port to one of the detection pin or the 1-wire pin. When the peripheral device is inserted into the connector port, the processor controls the switching device to connect the connector port to the detection pin to determine whether the connected peripheral device is a 1-wire device. When the processor determines that the connected peripheral device is a 1-wire device, the processor controls the switching device to connect the connector port to the 1-wire pin and the processor executes 1-wire communication with the peripheral device via the 1-wire pin. | 12-05-2013 |
20140006678 | PORTABLE ELECTRONIC DEVICE AND ACCESSORY DEVICE THEREOF, AND OPERATING METHOD FOR THE PORTABLE ELECTRONIC DEVICE | 01-02-2014 |
Patent application number | Description | Published |
20120042550 | KEY TAG - A key tag includes: a body having a recess and a through hole near its one end, a tag sheet accommodated in the recess, and a cover sheet adaptively engaged with the body so as to confine the tag sheet within the recess. | 02-23-2012 |
20120042703 | KEY BOX - According to the present invention, a key box is provided to include: a body; a cover, pivotally connected with the body to render an open state and a closed state; and a panel set, embedded on the cover, comprising a keypad module and a lock module. Wherein, by manipulating either the keypad module or the lock module, the open state and the closed state can be switched. | 02-23-2012 |
20120042704 | CASH BOX - An electronic cash box including a body, a cover and a panel set is provided. The cover is pivotally connected to the body, and provides an open state and a closed state. The panel set includes a keypad module providing an electronic lock function and a lock module providing a mechanical lock function. By operating either the keypad module or the lock module, the open state and closed state can be switched. | 02-23-2012 |
Patent application number | Description | Published |
20150022730 | TOUCH DISPLAY PANEL - A touch display panel includes an LCD panel and a touch structure formed on the LCD panel. The LCD panel includes a first substrate, a second substrate and a liquid crystal layer formed between the first substrate and the second substrate. A color filter is formed on a bottom surface of the first substrate adjacent to the liquid crystal layer. A touch structure is formed on the LCD panel. The touch structure includes a first transparent ITO film. The first transparent ITO film defines a plurality of channels thereon. A photo etching barrier layer is formed between the first transparent ITO film and the color filter. The photo etching barrier layer is configured to prevent the channels from extending to the color filter and the liquid crystal layer. | 01-22-2015 |
20150053974 | THIN FILM TRANSISTOR AND DISPLAY ARRAY SUBSTRATE USING SAME - A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole. | 02-26-2015 |
20150056761 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND DISPLAY ARRAY SUBSTRATE USING SAME - A manufacturing method of a thin film transistor includes hard-baking and etching processes for a stop layer. Two through holes are exposed and developed in a photoresistor layer, in which a distance between the two through holes is substantially equal to the channel length of the thin film transistor. Further, the etching stop layer is dry-etched to obtain the thin film transistor having an expected channel length. | 02-26-2015 |
20150085207 | TOUCH DEVICE - A touch device includes a first conducting layer, a second conducting layer, and a resistance reduction layer. The first conducting layer is insulated to the second conducting layer to form a touch sensing structure. The resistance reduction layer is coupled to the first conducting layer. A combination of the resistance reduction layer and the first conducting layer has a resistance that is less than an intrinsic resistance of the first conducting layer. | 03-26-2015 |