Patent application number | Description | Published |
20100161879 | Efficient and Secure Main Memory Sharing Across Multiple Processors - Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide computing systems that include at least two processors each communicably coupled to a network switch via network interfaces. The computing systems further include a memory appliance communicably coupled to the network switch, and configured to operate as a main memory for the two or more processors. | 06-24-2010 |
20100161908 | Efficient Memory Allocation Across Multiple Accessing Systems - Various embodiments of the present invention provide systems and methods for reducing memory usage across multiple virtual machines. For example, various embodiments of the present invention provide methods for reducing resource duplication across multiple virtual machines. Such methods include allocating a shared memory resource between a first virtual machine and a second virtual machine. A data set common to both the first virtual machine and the second virtual machine is identified. A first set of configuration information directing access to the data set by the first virtual machine to a first physical memory space is provided, and a second set of configuration information directing access to the data set by the second virtual machine to a second physical memory space is provided. The first physical memory space at least partially overlaps the second physical memory space. | 06-24-2010 |
20100161909 | Systems and Methods for Quota Management in a Memory Appliance - Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide thinly provisioned computing systems. Such thinly provisioned computing systems include a network switch, at least two or more processors each communicably coupled to the network switch, and a memory appliance communicably coupled to the at least two or more processors via the network switch. The memory appliance includes a bank of memory of a memory size, and the memory size is less than the aggregate memory quota. In some instances of the aforementioned embodiments, the memory appliance further includes a memory controller that is operable to receive requests to allocate and de-allocate portions of the bank of memory. | 06-24-2010 |
20100161929 | Flexible Memory Appliance and Methods for Using Such - Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide methods for configuring a shared main memory region. The methods include providing a memory appliance that includes a randomly accessible bank of memory and a memory controller that is operable to maintain information in relation to a first virtual machine and a second virtual machine. The methods further include receiving a request to allocate a first portion of the bank of memory to the first virtual machine, and receiving a request to allocate a second portion of the bank of memory to the second virtual machine. The first portion of the bank of memory is identified as accessible to the first virtual machine, and the second portion of the bank of memory is identified as accessible to the second virtual machine. | 06-24-2010 |
20100264983 | Systems and Methods for Power Dissipation Control in a Semiconductor Device - Various embodiments of the present invention provide systems and methods for governing power dissipation in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include a first function circuit, a second function circuit, and a power state change control circuit. The power state change control circuit is operable to determine a combination of power states of the first function circuit and the second function circuit that provides an overall power dissipation within a power dissipation level. | 10-21-2010 |
20100268917 | Systems and Methods for Ramped Power State Control in a Semiconductor Device - Various embodiments of the present invention provide systems and methods for ramping current usage in a semiconductor device. For example, various embodiments of the present invention provide semiconductor devices that include at least a first function circuit and a second function circuit, and a power state change control circuit. The power state change control circuit is operable to transition the power state of the first function circuit from a reduced power state to an operative power state, and to transition the second function circuit from a reduced power state to an operative power state. Transition of the power state of at least one of the first function circuit and the second function circuit is done in at least a first stage at a first time and a second stage at a second time, with the second time being after the first time. | 10-21-2010 |
20100269074 | Predictive Power Management Semiconductor Design Tool and Methods for Using Such - Various embodiments of the present invention provide systems and methods for improved semiconductor design. For example, various embodiments of the present invention provide methods for semiconductor design that include receiving a semiconductor design with at least a first function circuit and a second function circuit; simulating the semiconductor design using a first instruction and a second instruction; determining a power state transition between the first instruction and the second instruction; and augmenting the semiconductor design to implement the determined power state transition. Simulating the semiconductor design using a first instruction and a second instruction identifies an indication of a first subset of the first function circuit and the second function circuit used in executing the first instruction and a second subset of the first function circuit and the second function circuit used in executing the second instruction. The power state transition accommodates at least one power attribute selected from a group consisting of: an inrush current value, and an overall power dissipation value. | 10-21-2010 |
Patent application number | Description | Published |
20090313416 | Computer main memory incorporating volatile and non-volatile memory - A main memory for a computer system comprises a controller including an interface to one or more processors, non-volatile memory, and volatile memory. The main memory comprises one or more contiguous range of real addresses supported by both the non-volatile memory and the volatile memory. The controller may be incorporated into a mainboard and the non-volatile memory and the volatile memory may comprise pluggable memory modules. Alternatively, the controller may be incorporated into a hybrid pluggable memory module including non-volatile memory and volatile memory. The controller may utilize the volatile memory as a cache for the non-volatile memory. One or more subsets of the non-volatile memory may be configured to contain a system image, an operating system managed emulated disk image, and/or an operating system managed a page-file. The controller may encrypt and/or compress data written to and/or decrypt and/or decompress data read from the non-volatile memory. | 12-17-2009 |
20100031222 | BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME - A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions. | 02-04-2010 |
20130111181 | METHODS AND APPARATUS FOR INCREASING DEVICE ACCESS PERFORMANCE IN DATA PROCESSING SYSTEMS | 05-02-2013 |
20130262918 | Proxy Responder for Handling Anomalies in a Hardware System - An apparatus for handling anomalies in a hardware system including a master device and at least one slave device coupled with the master device through an interconnect device is provided. The apparatus includes at least one controller operative to receive status information relating to the slave device. The status information is indicative of whether an anomaly is present in the slave device and/or the interconnect device. The controller is operative to generate output response information as a function of the status information relating to the slave device for detecting and/or responding to hardware system anomalies in a manner which reduces a need for resetting the hardware system to return to normal operation. | 10-03-2013 |