Patent application number | Description | Published |
20110157884 | OPTOELECTRONIC DEVICE - A light-emitting device includes an insulating carrier; a light-emitting array formed on the insulating carrier including a first light-emitting circuit having a first light-emitting unit, wherein the first light-emitting circuit is a one-way circuit, a second light-emitting circuit having a second light-emitting unit, wherein the second light-emitting circuit is a one-way circuit, a first conductive layer, a second conductive layer, and a third conductive layer, wherein the first light-emitting circuit is formed between the first conductive layer and the second conductive layer and connects with them electrically, the second light-emitting circuit is formed between the second conductive layer and the third conductive layer and connects with them electrically, wherein an area of the second conductive layer is greater or equal to 1.9×10 | 06-30-2011 |
20120012867 | MULTI-DIMENSIONAL LIGHT-EMITTING DEVICE - The present application provides a multi-dimensional light-emitting device electrically connected to a power supply system. The multi-dimensional light-emitting device comprises a substrate, a blue light-emitting diode array and one or more phosphor layers. The blue light-emitting diode array, disposed on the substrate, comprises a plurality of blue light-emitting diode chips which are electrically connected. The multi-dimensional light-emitting device comprises a central area and a plurality of peripheral areas, which are arranged around the central area. The phosphor layer covers the central area. When the power supply system provides a high voltage, the central area and the peripheral areas of the multi-dimensional light-emitting device provide a first light and a plurality of second lights, respectively. The first light and the second lights are blended into a mixed light. | 01-19-2012 |
Patent application number | Description | Published |
20110315549 | TESTING STRIP FOR DETECTING A FLUIDIC SAMPLE - The present invention provides a testing strip for detecting a fluidic sample for testing a fluidic sample. The testing strip for detecting a fluidic sample comprises a substrate, a plurality of electrodes, a supporting layer and a cover that are serially stacked. The testing strip for detecting a fluidic sample includes a longitudinal long axis and a transverse short axis. The testing strip for detecting a fluidic sample includes a first end and a second end opposing to the first end along the longitudinal long axis. The testing strip for detecting a fluidic sample includes a reacting region located at the terminal of the first end, and the reacting region is defined and enclosed by the cover, the supporting layer and the substrate. The reacting region has a C-liked structure from a cross-sectional view taken along a direction perpendicular to the longest flowing path of the fluidic sample. | 12-29-2011 |
20130228266 | MANUFACTURING METHOD OF A TEST STRIP - The present invention discloses a manufacturing method of a test strip, which comprises making a first semi-finished product and a second semi-finished product. The manufacturing process of the first semi-finished product comprises: providing a substrate, forming a plurality of electrodes on the substrate, forming a supporting layer with a plurality of channels on the substrate, and providing a reaction material to fill in the channels. The manufacturing process of the second semi-finished product comprises: providing a lid, forming a hydrophilic layer on a first surface of the lid, forming an adhesive layer on the first surface without the hydrophilic layer. Thereafter, a test strip assembly is formed by adhering the channels of the first semi-finished product to the hydrophilic layer of the second semi-finished product. Finally, a plurality of test strips are produced by cutting the test strip assembly along a first axis of the substrate. | 09-05-2013 |
20130330683 | SELF-LOCKING AND POSITIONING DEVICE FOR DENTAL BRACE - A self-locking and positioning device for a dental brace, comprising: a brace main body, an elastic piece, and an upper cover. Wherein, on the brace main body is provided with a track and a fixing slot, while on the elastic piece is provided with a positioning piece and a slot. The positioning piece is provided with a barb, while the upper cover slides and fixes into the brace main body through the track. Then, the barb of the positioning piece on the elastic piece will act against a block portion on bottom of said upper cover, to restrict movement of the upper cover, to lock automatically the upper cover into position. The dental brace is simple in construction and easy to assemble, hereby raising production efficiency and yield. | 12-12-2013 |
Patent application number | Description | Published |
20090161901 | ULTRA THIN PACKAGE FOR ELECTRIC ACOUSTIC SENSOR CHIP OF MICRO ELECTRO MECHANICAL SYSTEM - An ultra thin package for an electric acoustic sensor chip of a micro electro mechanical system is provided. A substrate has a first substrate surface and a second substrate surface opposite to the first substrate surface. At least one conductor bump is formed on the second substrate surface. An electric acoustic sensor chip having a first chip surface and a second chip surface opposite to the first chip surface is provided. The first chip surface is electrically connected to the conductor bump. The conductor bump is positioned between the second substrate surface and the first chip surface to create a space. The conductor bump is used for transferring a signal from the sensor chip to the substrate. An acoustic opening passing through the substrate is formed. | 06-25-2009 |
20100084723 | MEMS STRUCTURE AND METHOD OF MANUFACTURING THE SAME - An MEMS structure and a method of manufacturing the same are provided. The MEMS structure includes a substrate and at least one suspended microstructure located on the substrate. The suspended microstructure includes a plurality of metal layers, at least one dielectric layer, and at least one peripheral metal wall. The dielectric layer is sandwiched by the metal layers, and the peripheral metal wall is parallel to a thickness direction of the suspended microstructure and surrounds an edge of the dielectric layer. | 04-08-2010 |
20100139767 | CHIP PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A chip package structure including a heat dissipation substrate, a chip and a heterojunction heat conduction buffer layer is provided. The chip is disposed on the heat dissipation substrate. The heterojunction heat conduction buffer layer is disposed between the heat dissipation substrate and the chip. The heterojunction heat conduction buffer layer includes a plurality of pillars perpendicular to the heat dissipation substrate. The aspect ratio of each pillar is between about 3:1 and 50:1. | 06-10-2010 |
20100150381 | MICRO-SPEAKER AND MANUFACTURING METHOD THEREOF - A micro-speaker and a manufacturing method thereof are provided. The micro-speaker has a sandwich structure. The micro-speaker includes two piezoelectric material layers and a diaphragm disposed between the two piezoelectric material layers, where the piezoelectric material layers have a ring-shaped structure. The problem of insufficient sound pressure at low frequency is resolved, and the flexibility of the micro-speaker is improved. | 06-17-2010 |
Patent application number | Description | Published |
20100271753 | METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes the first electrode comprising the first conductive lines and vias, where the first conductive lines on the same layer are parallel to each other and connected to the first periphery conductive line, and the first conductor lines aligned in adjacent layers are coupled to each other by the vias; the second electrode aligned opposite to the first electrode comprising the second conductive lines and vias, where the second conductive lines on the same layer are parallel to each other and connected to the second periphery conductive line, and the second conductor lines aligned in adjacent layers are coupled to each other by the vias; and oxide layers formed between the first electrode and the second electrode, where the vias have rectangular (slot) shape on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten. The vias can have various sizes. | 10-28-2010 |
20130127016 | METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode. | 05-23-2013 |
Patent application number | Description | Published |
20080238479 | REVERSIBLE SEQUENTIAL ELEMENT AND REVERSIBLE SEQUENTIAL CIRCUIT THEREOF - A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output. | 10-02-2008 |
20080238480 | REVERSIBLE SEQUENTIAL APPARATUSES - A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set to a constant level so that the second output line and the first output line have the same outputs. | 10-02-2008 |
20120066542 | Method for Node Addition and Removal of a Circuit - The present invention discloses a method for node addition and removal of a circuit. The steps of the method include: (a) providing a circuit with a plurality of nodes; (b) selecting a target node for computing mandatory assignments (MAs) of stuck-at 0 and stuck-at 1 fault tests on the target node, respectively, by a processing unit; (c) finding an added substitute node by utilizing the MAs of stuck-at 0 and stuck-at 1 fault tests of the target node by the processing unit; and (d) replacing the target node by using the added substitute node closest to primary inputs; and (e) the steps (b)˜(d) are repeated for removing the replaceable nodes and simplifying the circuit. | 03-15-2012 |
Patent application number | Description | Published |
20110193179 | LIGHTLY DOPED SOURCE/DRAIN LAST METHOD FOR DUAL-EPI INTEGRATION - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. | 08-11-2011 |
20110223752 | METHOD FOR FABRICATING A GATE STRUCTURE - The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode. | 09-15-2011 |
20110291201 | MULTI-STRAINED SOURCE/DRAIN STRUCTURES - The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor. | 12-01-2011 |
20130334617 | GATE STRUCTURE HAVING LIGHTLY DOPED REGION - A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric. | 12-19-2013 |
20140103454 | Lightly Doped Source/Drain Last Method For Dual-EPI Integration - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. | 04-17-2014 |
Patent application number | Description | Published |
20100033152 | PWM power converter using a multi-slope ramp signal to improve the transient response thereof - A ramp generator is provided to provide a multi-slope ramp signal for a PWM power converter. The ramp generator determines the slope turning points for the multi-slope ramp signal according to the error signal of the PWM power converter and thereby improve the transient response of the PWM power converter. Preferably, the slope turning point of the multi-slope ramp signal varies with the average of the error signal and is thus adaptive to the error signal and thereby the load condition. | 02-11-2010 |
20100201336 | Voltage mode switching regulator and control circuit and method therefor - The present invention discloses a voltage mode switching regulator with improved light load efficiency and mode transition characteristic, and a control circuit and a control method therefor. The switching regulator can switch between a pulse width modulation (PWM) mode and a pulse skipping mode. The control method for the switching regulator comprises: comparing a feedback signal relating to an output voltage with a reference signal, to generate an error amplification signal; generating a duty signal according to the error amplification signal and a ramp signal, to control the switching regulator; setting a threshold level of the error amplification signal and a threshold level of the pulse skipping mode according to the error amplification signal in a stable status; and when the error amplification signal is close or equal to the threshold level of the pulse skipping mode, generating a pulse skip signal to enter the pulse skipping mode. | 08-12-2010 |
20100301822 | Switching regulator and control circuit thereof, and method for determining on-time in switchng regulator - The present invention discloses a switching regulator and control method thereof, and a method for determining On-time in switching regulator. The switching regulator comprises: a power switch circuit including at least one power transistor switch which operates to convert an input voltage to an output voltage; a PWM generation circuit for generating a duty signal in a normal operation mode according to a feedback signal relating to the output voltage; a pulse skipping circuit for determining On-time in a pulse skipping mode according to a node with non-constant voltage level, the node being connected with the power transistor switch; and a driver circuit for driving the at least one power transistor switch according to one of the outputs from the PWM generation circuit and the pulse skipping circuit. | 12-02-2010 |
Patent application number | Description | Published |
20110103144 | STRUCTURES AND METHODS OF TRIMMING THRESHOLD VOLTAGE OF A FLASH EEPROM MEMORY - A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density. | 05-05-2011 |
20120155177 | STRUCTURES AND METHODS FOR READING OUT NON-VOLATILE MEMORY USING REFERENCING CELLS - The structures and methods of reading out semiconductor Non-Volatile Memory (NVM) using referencing cells are disclosed. The new invented scheme can reduce large current consumption from the direct current biasing in the conventional scheme and achieve a high resolution on the cell threshold voltage with a good sensing speed. | 06-21-2012 |
20120182811 | METHOD OF ERASING A FLASH EEPROM MEMORY - A method for erasing a flash EEPROM memory device is disclosed. The memory device has a first semiconductor region of one conductivity type formed within a second semiconductor region of an opposite conductivity type, source and drain regions formed from a semiconductor layer of the opposite conductivity type in the first semiconductor region, a well electrode formed from a semiconductor layer of the conductivity type inside the first semiconductor region, a charge storing layer electrically isolated from the first semiconductor region by a dielectric layer and having electric charge retention properties, and a control gate electrode electrically isolated from the charge storing layer by a inter layer of coupling dielectrics. The method comprises the steps of: applying a first voltage bias to both the well electrode and the second semiconductor region and a second bias to the control gate electrode for a duration of F/N tunneling; applying a third voltage bias to the well electrode and the second semiconductor region and a first zero voltage bias to the control gate electrode for a duration of traps depopulation; and, after the duration of traps depopulation, applying a fourth voltage bias to the control gate electrode and a second zero voltage bias to the well electrode and the second semiconductor region for a duration of traps assisted tunneling. | 07-19-2012 |
20120313590 | RECHARGEABLE BATTERY - A rechargeable battery is disclosed. The rechargeable battery of the invention includes a high density capacitor and an integrated circuit. The high density capacitor is connected to a ground terminal and a first node carrying a first voltage. The integrated circuit includes a band gap circuit, a first detecting unit, a voltage divider, a second detecting unit and at least one low dropout voltage regulator. The band gap circuit generates a band gap voltage according to the first voltage. The first detecting unit measures the first voltage and determines whether to apply an input charging voltage to the high density capacitor. The voltage divider is connected in parallel with the high density capacitor and has a second node carrying a second voltage. The second detecting unit measures the second voltage according to the band gap voltage and determines whether to connect a third node to the first node. Each low dropout voltage regulator is connected to the third node and generates a specified voltage output and a specified current output according to the band gap voltage and the first voltage. | 12-13-2012 |
Patent application number | Description | Published |
20100134130 | INTEGRATED CIRCUIT PROBING APPARATUS HAVING A TEMPERATURE-ADJUSTING MECHANISM - A probing apparatus for integrated circuit devices comprises a probe card, a probe holder for holding the probe card, a test head and a temperature-adjusting mechanism. The probe card comprises at least one probe capable of forming an electrical connection with the integrated circuit device facing a first surface of the probe card, and the temperature-adjusting mechanism can be positioned on/above a second surface of the probe card. The temperature-adjusting mechanism can be positioned inside the probe card, inside the probe holder or on the probe holder. The test head comprises a plurality of pins configured to form electrical connections with connecting sites of the probe card and test and measurement units and apparatus. The temperature-adjusting mechanism can be positioned on or inside the test head. The temperature-adjusting mechanism comprises a flow line having at least one inlet and a plurality of outlets, and the outlets can be positioned on the second surface of the probe card. | 06-03-2010 |
20110062317 | Testing Apparatus for Light-Emitting Devices - A sensing module for light-emitting devices includes a circuit board having at least one retaining region configured to retain a optical sensor, at least one circuit configured to electrically connect the optical sensor to an output interface at a front end of the circuit board, a substrate positioned on the circuit board and having at least one aperture exposing the retaining regions, and an optical device positioned on the aperture and configured to collect emitting lights from a light-emitting device to the retaining region through the aperture. | 03-17-2011 |
20110063608 | Sensing Module for Light-Emitting Devices and Testing Apparatus Using the Same - A sensing module for light-emitting devices includes a substrate having at least one first hole and at least one second hole connected to the first hole, an optical device positioned in the first hole and configured to collect emitting lights from the light-emitting device to the first hole, a light-guiding device positioned in the second hole, a reflector positioned in the first hole and configured to reflect the emitting lights from the light-emitting device to the light-guiding device, and an optical coupler positioned at a front end of the substrate and coupled with the light-guiding device. | 03-17-2011 |
20130082731 | SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR CHARACTERISTIC MEASUREMENT USING THE SAME - A switching matrix includes a plurality of input ports, a plurality of output ports, a plurality of switching devices configured to open and close, an electrical connection between the input ports and the output ports, and an electrical sensor configured to generate a signal by measuring a predetermined electrical property of the electrical connection, the open and close of switching devices is pre-determined by status read from the electrical sensor. | 04-04-2013 |
20140340105 | TEST ASSEMBLY - A test assembly adapted to test a semiconductor device is provided. The test assembly includes a main circuit board, an intermediate dielectric board, an intermediate circuit board, a plurality of intermediate conductive elements and a plurality of test probes. The main circuit board includes a surface and a plurality of pads disposed on the surface. The intermediate dielectric board is detachably disposed on the surface of the main circuit board and includes a plurality of through holes. The intermediate circuit board is disposed on the intermediated dielectric board and includes a plurality of first pads, a plurality of second pads, a first surface and a second surface opposite to the first surface. The intermediate conductive elements are disposed in the through holes, respectively. Each of the intermediate conductive elements electrically connects one of the pads of the main circuit board and one of the first pads of the intermediate circuit board. The test probes are disposed on the second surface of the intermediate circuit board and respectively electrically connected to the second pads of the intermediate circuit board. Each of the test probes is electrically connected to the main circuit board through the intermediate circuit board and one of the intermediated conductive elements. | 11-20-2014 |
20140340108 | TEST ASSEMBLY - A test assembly adapted to test a semiconductor device is provided. The test assembly includes a main circuit board, a space transformer, a plurality of electrical connection elements, an intermediary stiffener, and a plurality of test probes. The space transformer is disposed on the main circuit board and has a first surface and a second surface opposite to the first surface. The first surface of the space transformer faces the main circuit board. The electrical connection elements are disposed between the main circuit board and the first surface of the space transformer. The space transformer is electrically connected to the main circuit board through the electrical connection elements. The intermediary stiffener is disposed between the main circuit and the first surface of the space transformer. The intermediary stiffener has a plurality of accommodating through holes. Each of the electrical connection elements is disposed in one of the accommodating through holes. The test probes are disposed on the second surface of the space transformer and electrically connected to the space transformer. | 11-20-2014 |
Patent application number | Description | Published |
20090244071 | Synthetic image automatic generation system and method thereof - Provided is a computer system and a computerized method to automatically generate the synthetic images that simulate the human activities in a particular environment. The program instructions are input in the form of the natural language. Particular columns are provided in the user interface to allow the user to select desired instruction elements from sets of limited candidates. The instruction elements form the program instructions. The system analyzes the program instructions to obtain the standard predetermined time evaluation codes of the instructions. Parameters not include in the input program instructions are generated automatically. Synthetic images are generated by using the input program instructions and the parameters obtained. | 10-01-2009 |
20150062301 | NON-CONTACT 3D HUMAN FEATURE DATA ACQUISITION SYSTEM AND METHOD - A non-contact 3D human data acquisition system and method includes a depth-sensing camera used to acquire the front and back depth image data of static body of a test individual, and a human characteristic algorithmic processor electrically connected with the depth-sensing camera, so as to acquire the depth image data for subsequent processing. The human characteristic algorithmic processor includes a human depth data analysis module, a human sire measurement module, and a 3D human feature data acquisition module. The depth-sensing camera could be used to capture depth images, and the human characteristic algorithmic processor can be performed without contacting, with the human body or available in remote control. This allows one individual to rapidly and easily obtain important characteristic data of the human body, conduct 3D human body analysis, and collect important characteristic sizes, thus helping to set up statistical databases for further analysis, research, and other applications. | 03-05-2015 |
20150066706 | MATTRESS PURCHASE SYSTEM AND METHOD ESTABLISHED BASED ON PHYSIOLOGICAL RESPONSES AND SUBJECTIVE EVALUATION DATA - A mattress purchase system and method established based on physiological responses and subjective evaluation data is implemented via a computer device to assist customers in selecting and purchasing most suitable mattress products. The mattress purchase system includes a mattress database, a physiological responses database, an integrated operation processing unit, an adjustment parameter selector module, and a display interface used to output and display body parameter values, preliminary data of appropriate mattress sequence and the final suggested mattress data. The mattress purchase system enables customers to select the most suitable mattresses quickly and accurately, and improves the performance of salesman with better practicability. | 03-05-2015 |
Patent application number | Description | Published |
20080220576 | MANUFACTURING METHOD OF ANTI-PUNCH-THROUGH SEMICONDUCTOR DEVICE - An anti-punch-through semiconductor device is provided. The anti-punch-through semiconductor device includes a substrate, at least an isolation region and a plurality of trench devices. The trench device is disposed in the substrate. The trench device includes a source/drain region. The source/drain region of the trench device is disposed at the bottom of the trench device. The isolation region is disposed in the substrate and between the source/drain regions of each trench device. | 09-11-2008 |
20080224202 | NON-VOLATILE MEMORY - A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates. | 09-18-2008 |
20090026525 | MEMORY AND METHOD FOR FABRICATING THE SAME - A method for fabricating a memory is provided. A tunneling dielectric layer, a first conductive layer, and a mask layer are formed on a substrate. The mask layer, the first conductive layer, the tunneling dielectric layer, and the substrate are patterned to form trenches in the substrate. A passivation layer and isolation structures are formed in sequence to fill the trenches, and the etching rate of the isolation structures is greater than that of the passivation layer. After the mask layer is removed, a second conductive layer is formed on the first conductive layer. Portions of the isolation structures are removed to expose the sidewalls of the first and the second conductive layers. Further, a third conductive layer is formed on the exposed sidewalls of the first and the second conductive layers. An inter-gate dielectric layer and a control gate are formed on the substrate. | 01-29-2009 |
20090075443 | METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes providing a substrate with a mask layer thereon, forming pluralities of shallow trenches in the substrate, forming a first oxide layer on the substrate and in the shallow trenches, removing a portion of the first oxide layer above the mask layer, forming a second oxide layer on the mask layer and the first oxide layer, wherein the first and second oxide layers have different etching ratios, removing a portion of the second oxide layer positioned above the mask layer so that an STI is formed with the first and the second oxide layers in each shallow trench, removing the mask layer to form recess portions between adjacent STIs, and filling the recess portions with a conductive layer to form floating gates in the recess portions. | 03-19-2009 |
20090130808 | METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes successively forming a floating gate insulating layer, a floating gate material layer, a dielectric layer, a control gate material layer, a silicide layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer, removing portions of the silicide layer, the control gate material layer, the dielectric layer, and the floating gate material layer not covered by the hard mask layer to form a stacked structure, forming a silicon cap layer covering the surface of the stacked structure, and performing a thermal process. | 05-21-2009 |
Patent application number | Description | Published |
20080219071 | Data flow scheme for low power DRAM - Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation. | 09-11-2008 |
20080316845 | MEMORY ROW ARCHITECTURE HAVING MEMORY ROW REDUNDANCY REPAIR FUNCTION - The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module. | 12-25-2008 |
20100103753 | DATA DETECTING APPARATUS AND METHODS THEREOF - A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit. | 04-29-2010 |
20100269001 | TESTING SYSTEM AND METHOD THEREOF - Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory. | 10-21-2010 |
20110085388 | SYSTEM IN PACKAGE INTEGRATED CIRCUIT WITH SELF-GENERATING REFERENCE VOLTAGE - This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage. | 04-14-2011 |
20110176381 | MEMORY HAVING A DISABLING CIRCUIT AND METHOD FOR DISABLING THE MEMORY - A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix. | 07-21-2011 |
20120170387 | DEVICE FOR GENERATING A TEST PATTERN OF A MEMORY CHIP AND METHOD THEREOF - A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal. | 07-05-2012 |
20130010558 | Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof - By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages. | 01-10-2013 |
20130234766 | INPUT RECEIVER AND OPERATION METHOD THEREOF - An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal. | 09-12-2013 |
20140075251 | CHIP CAPABLE OF IMPROVING TEST COVERAGE OF PADS AND RELATED METHOD THEREOF - A method capable of improving test coverage of chip pads, where the chip includes a control unit, a plurality of pads, and a storage unit, is disclosed. The storage unit includes a plurality of blocks. The method includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed. | 03-13-2014 |
Patent application number | Description | Published |
20110193188 | IMAGE SENSOR - An image sensor comprising a black pixel region and an active pixel region is provided. The active pixel region is adjacent to the black pixel region. The black pixel region comprises a dummy black pixel region and a readout black pixel region. The readout black pixel region is surrounded by the dummy black pixel region. The dummy black pixel region comprises a photo-sensitive element, a first shielding layer, a second shielding layer and a third shielding layer. The first shielding layer, the second shielding layer and the third shielding layer are used for blocking the incident light going into the photo-sensitive element. The first shielding layer, the second shielding layer and the third shielding layer cover the photo-sensitive element, and the second shielding layer is interposed between the first shielding layer and the third shielding layer. | 08-11-2011 |
20130201388 | OPTICAL SENSING APPARATUS AND OPTICAL SETTING METHOD - An optical sensing apparatus includes an optical sensing pixel array and a plurality of micro-optical device sets. The optical sensing pixel array has a plurality of array elements, and each of the array elements has one or multiple of a plurality of optical sensing pixels. The micro-optical device sets are configured corresponding to the optical sensing pixels respectively. Each of the micro-optical device sets has a shifting vector with respect to one of the optical sensing pixels. The optical sensing pixel array has a reference original point. Two shifting vectors of two of the micro-optical device sets with respect to corresponding two of the optical sensing pixels at the same radial distance on two polar axes from the reference original point and along opposite directions are asymmetric. | 08-08-2013 |
20140332664 | IMAGE SENSOR - An image sensor including a plurality of sensing pixels, a plurality of micro-lenses disposed on the sensing pixels and a plurality of first light distributing elements disposed between the sensing pixels and the micro-lenses is provided. Each of the first light distributing elements includes a first refractive index pattern and a second refractive index pattern surrounding the first refractive index pattern. The refractive index of the first refractive index pattern is larger than the refractive index of the second refractive index pattern. | 11-13-2014 |
Patent application number | Description | Published |
20110255084 | BIO-SAMPLE IMAGE PICKUP DEVICE - A bio-sample image pickup device includes a light source module, a carrier, an image pickup unit, a first filter set, and a second filter set. The carrier carries the light source module and the bio-sample, and moves between a first position and a second position. The first filter set between the light source module and the image pickup unit for filtering the light emitted by the light source module, and the image pickup unit picks up the image of the bio-sample through the first filter set in the first position. The second filter set in the second position filters the light emitted by the light source module for allowing an operator to see the bio-sample in the second position through the second filter. | 10-20-2011 |
20130344580 | ASSISTANT DEVICE FOR PIPETTING - An assistant device for pipetting is disclosed. The assistant device for pipetting comprises: a multi-well plate, a first light emitting element array, a first photo detector array, a second light emitting element array, a second photo detector array, a control circuit, and a display. The multi-well plate comprises a plurality of wells for containing a solution, and the plurality of wells are disposed as an array. The first and second light emitting element arrays are disposed at adjacent sides of the multi-well plate. The first and second photo detector arrays are disposed at the side opposite to the first and second light emitting element arrays respectively. The control circuit is connected to the light emitting element arrays, the photo detector arrays, and the display to determine the amount of pipetting times of each of the wells and display on the display. | 12-26-2013 |
Patent application number | Description | Published |
20120001690 | System for Driver Amplifier - In an embodiment, a circuit includes a two-stage amplifier and a feedback component. The two stage amplifier consists of an input stage biased at a first power supply voltage, and an output stage biased at a second power supply voltage. The second power supply voltage is greater than the first power supply voltage, and the second stage is configured for high voltage operation. The feedback component is connected between the output stage to the input stage. | 01-05-2012 |
20130141145 | CLOCK AND DATA RECOVERY CIRCUIT - The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal. | 06-06-2013 |
20130169326 | GATED VOLTAGE-CONTROLLED OSCILLATOR AND CLOCK AND DATA RECOVERY CIRCUIT - A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal. | 07-04-2013 |
Patent application number | Description | Published |
20110080388 | DISPLAY PANEL AND ACTIVE DEVICE ARRAY SUBSTRATE THEREOF - A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines. | 04-07-2011 |
20110233567 | PIXEL ARRAY - A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line. | 09-29-2011 |
20110273654 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd | 11-10-2011 |
20110292331 | PIXEL STRUCTURE AND DISPLAY PANEL HAVING THE SAME - A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line. | 12-01-2011 |
20120169677 | LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY PANEL THEREOF - A liquid crystal display (LCD) and an LCD panel thereof are provided. The structure of the pixel array of the LCD panel is the structure of the one third source driving (OTSD), and by which skillfully layout the coupled relationship among each pixel, each signal line and each scan line, such that the LCD panel can be driven by a column inversion to achieve the purpose of single-dot inversion displaying, and thus not only reducing the power consumption of the whole LCD, but also promoting the display quality. | 07-05-2012 |
20120315733 | METHOD OF FABRICATING GATE ELCTRODE USING A TREATED HARD MASK - A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure. | 12-13-2012 |
20130009216 | Semiconductor Device With a Dislocation Structure and Method of Forming the Same - A semiconductor device with bi-layer dislocation and method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having a gate stack. The method further includes performing a first pre-amorphous implantation process on the substrate and forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate and performing a second annealing process on the substrate and the second stress film. | 01-10-2013 |
20130146895 | PINCH-OFF CONTROL OF GATE EDGE DISLOCATION - The embodiments of processes and structures described provide mechanisms for improving the mobility of carriers. A dislocation is formed in a source or drain region between gate structures or between a gate structure and an isolation structure by first amortizing the source or drain region and then recrystallizing the region by using an annealing process with a low pre-heat temperature. A doped epitaxial material may be formed over the recrystallized region. The dislocation and the strain created by the doped epitaxial material in the source or drain region help increase carrier mobility. | 06-13-2013 |
20130146949 | MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE - The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved. | 06-13-2013 |
20130157431 | STRUCTURE AND METHOD FOR THERMAL TREATMENT WITH EPITAXIAL SICP THERMAL STABILITY IMPROVEMENT - The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet. | 06-20-2013 |
20130178029 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film. | 07-11-2013 |
20140154876 | MECHANISMS FOR FORMING STRESSOR REGIONS IN A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes performing a pre-amorphous implantation (PAI) process to form an amorphized region on a substrate. The method also includes forming a stress film over the substrate, and performing an annealing process to recrystallize the amorphized region after the stress film is formed. The method further includes forming a recess region on the substrate. The recess region overlies the recrystallized region. The method additionally includes forming an epitaxial stress-inducing material in the recess region. | 06-05-2014 |
20140220757 | PINCH-OFF CONTROL OF GATE EDGE DISLOCATION - A method of manufacturing a semiconductor device includes providing a substrate having a gate stack, and performing a pre-amorphous implantation (PAI) process to form an amorphized region on the substrate. The method also includes performing an annealing process to recrystallize the amorphized region after the stress film is formed. The annealing process includes a preheat at a temperature in a range from about 400° C. to about 550° C. and an annealing temperature equal to or greater than about 900° C., and the annealing process recrystallizes the amorphized region. | 08-07-2014 |
Patent application number | Description | Published |
20110299086 | SENSING DEVICE AND IMAGE SENSING SYSTEM THEREOF - A sensing device includes a housing and an image sensing system disposed in the housing and used for detecting a reflected light from an object. The image sensing system includes a substrate, a light sensing element, and a reflection and redirection element. The light sensing element is disposed on the substrate. The reflection and redirection element is disposed between the light sensing element and the object, and used for reflecting and redirecting the reflected light from the object to a receiving direction of the light sensing element, such that the light sensing element receives the reflected light and generates a corresponding sensing signal. | 12-08-2011 |
20120001054 | SENSING DEVICE AND IMAGE SENSOR MODULE THEREOF - An image sensor module is installed in a sensing device, and is used to detect a reflected light of an object. The image sensor module includes a carrier, a light sensing element, and a package body. The light sensing element is disposed on a substrate. The carrier is disposed on the substrate in the sensing device. The light sensing element is installed in the carrier, and is electrically connected with the substrate via multiple solder balls. The package body is installed on the carrier, and has a reflecting and diverting element, which is located between the light sensing element and the object and is used for reflecting reflected light of the object and diverting the reflected light towards a receiving direction of the light sensing element. The light sensing element receives the reflected light and generates a corresponding sensing signal. | 01-05-2012 |
20120019715 | DISPLAY PANEL AND ASSEMBLING METHOD OF THE SAME - A display panel and an assembling method of the same are described. An image capture module is electrically disposed on a substrate of a display module, such that the image capture module and the display module are combined into an integrated structure, so as to reduce the overall size of a display assembled by using the display panel. | 01-26-2012 |
20120032946 | NEW CALIBRATION PROCEDURES FOR THREE-DIMENSIONAL DIGITAL IMAGE CORRELATION - The present invention discloses new calibration procedures for three-dimensional digital image correlation (3D-DIC) method comprising steps: providing a 3D-DIC system: arranging an object at a focus of a first image capture device and a second image capture device, and using a light source device to uniformly project light on the object, and linking the system to a processor capable of data processing and analyzing; providing a calibration plate: arranging the calibration plate at a position where the object is located; performing a system calibration procedures: treating the first and second image capture devices as an identical unit and rotating them simultaneously to acquire a plurality of calibration images of the calibration plate, wherein each calibration image contains a plurality of circles formed at an identical spacing which is preset to work out a plurality of system parameters through the spacings for measurement and calculation of the object. | 02-09-2012 |
20130250277 | APPARATUS FOR QUANTIFYING UNKNOWN STRESS AND RESIDUAL STRESS OF A MATERIAL AND METHOD THEREOF - An apparatus for quantifying unknown stress and residual stress of a material to be tested, the material being a birefringent or temporary birefringent material, which includes a light source, a polarizer in front of the light source for converting a light beam from the light source into a beam with linear polarization, a first quarter-wave plate in front of the polarizer for generating circular polarization, a standard material, a second quarter-wave plate, an analyzer, a loading unit, a spectrometer for obtaining transmissivity spectrum of the standard material under the wavelength of the light source and a detecting module connected to the spectrometer to have the transmissivity spectrum of the material to be tested and consequently a stress quantifying formula for the standard material. | 09-26-2013 |
20140111649 | MULTI-IMAGE CAPTURE DEVICE CAPTURING IMAGES BY MEANS OF CIRCULAR MOTION - A multi-image capture device capturing images by means of circular motion controls the shift movement, along a semi-circular measuring rod, of a moving mechanism by a location control device. Furthermore, a rotary control device is used to control the positioning and image-capturing angle of a second image capture device fixed on the rotary mechanism. Thereby, a first image capture device and the second image capture device are of a co-circle configuration where the optical axis of the first image capture device and the second image capture device overlap to form a center of the co-circle. Such a configuration can broaden the visual range of the image capture device, and allows quick calibration of the image capture device according to positioning of shift movement and image-capturing angles. | 04-24-2014 |
20140111810 | SYSTEM OF COMPUTING SURFACE RECONSTRUCTION, IN-PLANE AND OUT-OF-PLANE DISPLACEMENTS AND STRAIN DISTRIBUTION - A system of computing surface reconstruction, in-plane and out-of-plane displacements and strain distribution utilizes the optical switching element to switch the reference beam to analyze the images of the test object before and after deformation, to measure the topography, in-plane and out-of-plane displacements and surface two-dimensional strain distribution on the test surface of the test object, and thus to increase the measurement range on the test surface of the test object with the use of image registration. Thereby, the complexity and error of scanning the test object can be reduced. Such a system need not to move the image capturing device or test object to generate relative displacement for reaching the measurement effect of the test surface of the test object in three-dimensional coordinates. | 04-24-2014 |
Patent application number | Description | Published |
20110258371 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access management includes: with regard to a same memory cell of a memory, according to a first digital value output by the memory, requesting the memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the memory cell, and a number of various possible states of the memory cell is equal to a number of various possible combinations of all bit(s) stored in the memory cell; and based upon the at least one second digital value, generating/obtaining soft information of the memory cell, for use of performing soft decoding. An associated memory device and a controller thereof are also provided. | 10-20-2011 |
20120023387 | CONTROLLING METHODS AND CONTROLLERS UTILIZED IN FLASH MEMORY DEVICE FOR REFERRING TO DATA COMPRESSION RESULT TO ADJUST ECC PROTECTION CAPABILITY - A controlling method utilized in a flash memory device includes: compressing first data received from a host to generate second data; generating record data according to the first data and the second data where the record data records error correct coding (ECC) control information at least; executing ECC protection upon specific data selected from the first and second data to generate third data; and writing the third data into the flash memory device. | 01-26-2012 |
20130304977 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access management includes: with regard to a same Flash cell of a Flash memory, receiving a first digital value outputted by the Flash memory, requesting the Flash memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the Flash cell, and a number of various possible states of the Flash cell correspond to a possible number of bit(s) stored in the Flash cell; based upon the second digital value, generating/obtaining soft information of the Flash cell, for use of performing soft decoding; and controlling the Flash memory to perform sensing operations by respectively utilizing a plurality of sensing voltages that are not all the same, in order to generate the first digital value and the second digital value. | 11-14-2013 |
20140321203 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for accessing a memory includes: utilizing a Flash memory to perform a plurality of sensing operations with a plurality of different sensing voltages respectively corresponding to the plurality of sensing operations; according to the plurality of sensing operations, generating a first digital value of a Flash cell of the Flash memory; according to the plurality of sensing operations and the first digital value, generating at least a second digital value of the Flash cell; and obtaining soft information of the Flash cell according to the second digital value. The first digital value and the second digital value are used for determining information of a same bit stored in the Flash cell, a number of possible bit(s) of the Flash cell directly corresponds to a number of possible states of the Flash cell, and the obtained soft information is used for performing soft decoding. | 10-30-2014 |
Patent application number | Description | Published |
20110035043 | METHOD AND APPARATUS FOR WIRELESS TRANSMISSION OF DIAGNOSTIC INFORMATION - The present disclosure provides a system for fabricating a semiconductor device. The system includes a semiconductor fabrication tool. The semiconductor fabrication tool has an integrated inter interface that measures a first process parameter of the fabrication tool. The system also includes a wireless sensor. The wireless sensor is detachably coupled to the fabrication tool. The wireless sensor measures a second process parameter of the fabrication tool. The second process parameter is different from the first process parameter. | 02-10-2011 |
20110035186 | PORTABLE WIRELESS SENSOR - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 02-10-2011 |
20110207332 | THIN FILM COATED PROCESS KITS FOR SEMICONDUCTOR MANUFACTURING TOOLS - A plasma processing apparatus used in semiconductor device manufacturing includes a process kit formed of insulating materials such as quartz and coated with a Y | 08-25-2011 |
20130026381 | DYNAMIC, REAL TIME ULTRAVIOLET RADIATION INTENSITY MONITOR - An apparatus and method for detecting an intensity of radiation in a process chamber, such as an ultraviolet curing process chamber, is disclosed. An exemplary apparatus includes a process chamber having a radiation source therein, wherein the radiation source is configured to emit radiation within the process chamber; a radiation sensor attached to the process chamber; and an optical fiber coupled with the radiation source and the radiation sensor, wherein the optical fiber is configured to transmit a portion of the emitted radiation to the radiation sensor, and the radiation sensor is configured to detect an intensity of the portion of the emitted radiation via the optical fiber. | 01-31-2013 |
20140008213 | MAGNET MODULE HAVING EPICYCLIC GEARING SYSTEM AND METHOD OF USE - This disclosure relates to a magnet assembly including an epicyclic gearing system. The epicyclic gearing system including a central gear configured to be rotated, at least one peripheral gear connected to the central gear and configured to rotate and translate relative to the central gear, and an annulus surrounding the at least one peripheral gear and connected with the at least one peripheral gear. The magnet assembly further includes a magnet module connected with the epicyclic gearing system, the magnet module including a support connected with the at least one peripheral gear, the axis of rotation of the support being coaxial with the axis of rotation of the at least one peripheral gear connected with the support. | 01-09-2014 |
20140167614 | ARC CHAMBER WITH MULTIPLE CATHODES FOR AN ION SOURCE - An apparatus for extending the useful life of an ion source, comprising an arc chamber containing a plurality of cathodes to be used sequentially and a plurality of repellers to protect cathodes when not in use. The arc chamber includes an arc chamber housing defining a reaction cavity, gas injection openings, a plurality of cathodes, and at least one repeller element. A method for extending the useful life of an ion source includes providing power to a first cathode of an arc chamber in an ion source, operating the first cathode, detecting a failure or degradation in performance of the first cathode, energizing a second cathode, and continuing operation of the arc chamber with the second cathode. | 06-19-2014 |
20140200702 | Digital Wireless Data Collection - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The first and second sensors may communicate the parameters using different and incompatible protocols. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 07-17-2014 |
20140273293 | Portable Wireless Sensor - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 09-18-2014 |
20140273459 | Systems and Methods for a Narrow Band High Transmittance Interference Filter - The present disclosure provides an interference filter, a lithography system incorporating an interference filter, and a method of fabricating an interference filter. The interference filter includes a transparent substrate having a front surface and a back surface, a plurality of alternating material layers formed over the front surface of the transparent substrate that form a bandpass filter, and an anti-reflective structure formed over the back surface of the transparent substrate. The alternating material layers alternate between a relatively high refractive index material and a relatively low refractive index material. | 09-18-2014 |
20140340665 | ULTRAVIOLET LIGHT EMITTING DIODE ARRAY LIGHT SOURCE FOR PHOTOLITHOGRAPHY AND METHOD - A light source includes a plurality of ultraviolet (UV) light emitting diodes (LEDs) and an LED phase shift controller coupled to the plurality of UV LEDs adapted to control the phase shift of each UV LED in the plurality of UV LEDs. The plurality of UV LEDs forms a UV LED array. An ultraviolet lithography system can include a light source as described above. The system can further include a mirror assembly in a light path of the light source, the mirror assembly having a polarization mirror with an interference coating. A method provides a light source for an ultraviolet lithography system including the element of providing an plurality of UV LEDs that emit UV light and the element of controlling a phase shift of the plurality of UV LEDs with an LED phase shift controller coupled to each UV LED or arrays of the UV LEDs in the plurality of UV LEDs. | 11-20-2014 |
20150038056 | TEMPERATURE MODIFICATION FOR CHEMICAL MECHANICAL POLISHING - Among other things, one or more systems and techniques for increasing temperature for chemical mechanical polishing (CMP) are provided. For example, a liquid heater component is configured to supply heated liquid to a polishing pad upon which a semiconductor wafer is to be polished, resulting in a heated polishing pad having a heated polishing pad temperature. The increased temperature of the heated polishing pad increases oxidation of the semiconductor wafer, which improves a CMP removal rate of material from the semiconductor wafer due to a decreased oxidation timespan and a stabilization timespan for reaching a stable CMP removal rate during CMP. In this way, the semiconductor wafer is polished utilizing the heated polishing pad, such as by a tungsten CMP process. | 02-05-2015 |