Patent application number | Description | Published |
20080242063 | Solder composition doped with a barrier component and method of making same - A solder composition and a method of making the composition. The solder composition comprises a Sn-containing base material and a barrier component having a reactivity with Sn which is higher than a reactivity of Ni or Cu with Sn, the barrier component being present in the composition in an amount sufficient to reduce a reactivity of Sn with both Ni and Cu. | 10-02-2008 |
20090001550 | Method of Forming a Multilayer Substrate Core Structure Using Sequential Microvia Laser Drilling And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 01-01-2009 |
20090002958 | Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof. | 01-01-2009 |
20090056989 | PRINTED CIRCUIT BOARD AND METHOD FOR PREPARATION THEREOF - Disclosed is a method for preparing a printed circuit board. The method comprises forming a conductive layer on an insulated layer substrate. The method further includes partitioning the conductive layer into a first area and a second area by applying a photoresist mask. Furthermore, the method includes applying a first etching process to the conductive layer to pattern a first set of features on the first area of the conductive layer. Thereafter, the method includes applying a second etching process to the conductive layer to pattern a second set of features on the second area of the conductive layer. The second set of features on the second area of the conductive layer has a finer pitch as compared to the first set of features on the first area of the conductive layer. | 03-05-2009 |
20090079530 | Forming a helical inductor - In one embodiment, the present invention includes an apparatus having a substrate with vias extending between first and second surfaces thereof, and at least one helical inductor adapted within a via, which may be formed of a conductive material. Other embodiments are described and claimed. | 03-26-2009 |
20090108455 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 04-30-2009 |
20090166858 | LGA SUBSTRATE AND METHOD OF MAKING SAME - An LGA substrate includes a core ( | 07-02-2009 |
20090196000 | SYSTEM, APPARATUS, AND METHOD FOR ADVANCED SOLDER BUMPING - According to some embodiments, a method, apparatus, and system are provided. In some embodiments, the method includes providing solder resist material on a surface of a substrate, applying mask material on top of the solder resist material, reflowing solder located in an opening formed through both the solder resist material and the mask material, and removing the mask material after the reflowing of the solder. | 08-06-2009 |
20090238233 | OPTICAL DIE STRUCTURES AND ASSOCIATED PACKAGE SUBSTRATES - Optical die structures and associated package substrates are generally described. In one example, an electronic device includes a package substrate having a package substrate core, a dielectric layer coupled with the package substrate core, and one or more input/output (I/O) optical fibers coupled with the package substrate core or coupled with the build-up dielectric layer, or combinations thereof, the one or more I/O optical fibers to guide I/O optical signals to and from the package substrate wherein the one or more I/O optical fibers allow both input and output optical signals to travel through the one or more I/O optical fibers. | 09-24-2009 |
20090238516 | SUBSTRATES FOR OPTICAL DIE STRUCTURES - Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard. | 09-24-2009 |
20090294992 | EMBEDDING DEVICE IN SUBSTRATE CAVITY - An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device. | 12-03-2009 |
20100044862 | METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR SUBSTRATE - A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate. | 02-25-2010 |
20100155115 | Doping of lead-free solder alloys and structures formed thereby - Methods of forming a microelectronic structure are described. Those methods include doping a lead free solder material with nickel, wherein the nickel comprises up to about 0.2 percent by weight of the solder material, and then applying the solder material to a substrate comprising a copper pad. | 06-24-2010 |
20100155947 | SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE - Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed. | 06-24-2010 |
20100301484 | LGA SUBSTRATE AND METHOD OF MAKING SAME - An LGA substrate includes a core ( | 12-02-2010 |
20110058340 | METHOD OF FORMING A MULTILAYER SUBSTRATE CORE STRUCTURE USING SEQUENTIAL MICROVIA LASER DRILLING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 03-10-2011 |
20110290864 | SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE - Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed. | 12-01-2011 |
20110293962 | SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE - Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed. | 12-01-2011 |
20110298135 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 12-08-2011 |
20130242498 | METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER DRILLING AND CONDUCTIVE LAYER PRE-PATTERNING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD - A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof. | 09-19-2013 |