Patent application number | Description | Published |
20100155818 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 06-24-2010 |
20110058418 | 3D NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A 3D nonvolatile memory device includes: a plurality of channel structures including a plurality of channel layers and interlayer dielectric layers, which are alternately stacked, and extended in a first direction; a plurality of word lines extended in a second direction at least substantially perpendicular to the first direction; a plurality of row select lines connected to the plurality of channel layers, respectively, and extended in the second direction; and a plurality of column select lines connected to the plurality of channel structures, respectively, and extended in the first direction. | 03-10-2011 |
20110266611 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer. | 11-03-2011 |
20120126308 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a plurality of memory cells stacked along a channel protruded from a substrate, a first select transistor connected to one end of the plurality of memory cells, a first interlayer dielectric layer for being coupled between a source line and the first select transistor, and a second interlayer dielectric layer disposed between the first select transistor and the one end of the plurality of memory cells, and configured to include a first recess region. | 05-24-2012 |
20120168850 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel protruding in a vertical direction from a substrate, a plurality of interlayer dielectric layers and gate electrode layers which are alternately stacked over the substrate along the channel, and a memory layer formed between the channel and a stacked structure of the interlayer dielectric layers and gate electrode layers. Two or more gate electrode layers of the plurality of gate electrode layers are coupled to an interconnection line to form a selection transistor. | 07-05-2012 |
20120289020 | METHOD FOR FABRICATING VARIABLE RESISTANCE MEMORY DEVICE - A method for fabricating a variable resistance memory device includes forming a semiconductor pattern doped with impurities, forming a resistor over the semiconductor pattern, and forming a diode by performing microwave annealing to activate the impurities in the semiconductor pattern. | 11-15-2012 |
20130105905 | SEMICONDUCTOR DEVICE WITH METAL GATE AND HIGH-K DIELECTRIC LAYER, CMOS INTEGRATED CIRCUIT, AND METHOD FOR FABRICATING THE SAME | 05-02-2013 |
20130161710 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer. | 06-27-2013 |
20130175603 | VERTICAL CHANNEL TYPE NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels. | 07-11-2013 |
20130221425 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer. | 08-29-2013 |
20130240957 | METHOD OF FORMING GATE DIELECTRIC LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process. | 09-19-2013 |
20130244394 | METHOD FOR FABRICATING CAPACITOR WITH HIGH ASPECT RATIO - A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer. | 09-19-2013 |
20140004679 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140203337 | METHOD OF FORMING GATE DIELECTRIC LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process. | 07-24-2014 |
Patent application number | Description | Published |
20110064052 | CELL RESELECTION METHOD AND APPARATUS FOR PACKET DATA SERVICE IN A MOBILE COMMUNICATION TERMINAL - A cell reselection method and apparatus for a packet data service in a mobile communication terminal are provided. The cell reselection method for the packet data service in the mobile communication terminal includes if a Circuit Switch (CS) call ends, determining whether the ended call is a CS fallback call, if it is determined that the ended call is the CS fallback call, determining whether an accessible Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) cell exists by measuring signals received from neighbor cells, and reselecting the accessible E-UTRAN cell. | 03-17-2011 |
20110151930 | APPARATUS AND METHOD FOR SUPPORTING SIM CARD IN MOBILE COMMUNICATION TERMINAL HAVING MULTIPLE MODEMS - An apparatus and method for supporting a Subscriber Identity Module (SIM) card in a mobile communication terminal including a plurality of modems are provided. The apparatus includes the SIM card for storing user information, and the plurality of modems each for providing a clock and for transmitting/receiving a signal by an independent interface with respect to the SIM card. Only a first modem of the plurality of modems controls a reset of the SIM card. | 06-23-2011 |
20110171967 | METHOD AND APPARATUS FOR REQUESTING RESOURCE ALLOCATION IN MOBILE COMMUNICATION TERMINAL - A method and an apparatus for requesting resource allocation in a mobile communication terminal are provided. In the method, a priority of each logical channel when there is transmission data to be transmitted is determined. A weight is applied to a size of transmission data for each logical channel according to the priority. A Buffer Status Report (BSR) message representing the size of the transmission data for each logical channel to which the weight has been applied is generated. The BSR message is transmitted to a base station. | 07-14-2011 |
20110275373 | USER EQUIPMENT SUPPORTING MULTIPLE MOBILE COMMUNICATION SYSTEMS AND CELL SELECTION METHOD FOR THE SAME - A user equipment supporting multiple communication systems and a cell selection method for the same are provided. The cell selection method, for a user equipment supporting first and second systems, includes storing records of services received by the user equipment in a service log, receiving, by the user equipment, a service from a reference cell of the first system, extracting, by the user equipment which waits to receive a service from the second system during service reception from the reference cell, a cell frequency band of the second system corresponding to identification information of the reference cell from the service log, and performing, when extraction of a cell frequency band of the second system is successful, cell acquisition using the extracted cell frequency band. The user equipment supporting different communication systems may thereby perform cell selection in an improved manner. | 11-10-2011 |