Liu, Hsinchu City
Chan-Jui Liu, Hsinchu City TW
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20110303825 | Active Photosensing Pixel - An active photosensing pixel is disclosed, in which a two-terminal photosensing transistor has a first terminal coupled to a first node, a second terminal coupled to a first selection line and a control terminal connected to the second terminal. A driving transistor has a first terminal coupled to a first reference voltage, a second terminal coupled to an output line and a control terminal connected to the first node. A reset transistor has a first terminal connected to the first node, a second terminal coupled to a second reference voltage and a control terminal coupled to a second selection line. | 12-15-2011 |
20130071650 | FABRICATING METHOD OF FLEXIBLE DISPLAY AND FLEXIBLE DISPLAY - A fabricating method of a flexible display is provided. A release layer is formed on a carrier substrate. The release layer is patterned to form a patterned release layer. A flexible substrate is formed on the patterned release layer, wherein the flexible substrate covers the patterned release layer and a portion of the flexible substrate contacts the carrier substrate. An adhesive force between the patterned release layer and the flexible substrate is larger than an adhesive force between the patterned release layer and the carrier substrate. A device layer is formed on the flexible substrate. A display layer is formed on the device layer. The flexible substrate and patterned release layer are cut simultaneously. The patterned release layer being cut is separated from the carrier substrate, wherein the flexible substrate, the device layer and the display layer which have been cut are sequentially disposed on the separated patterned release layer. | 03-21-2013 |
Chao-Yin Liu, Hsinchu City TW
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20100262763 | DATA ACCESS METHOD EMPLOYED IN MULTI-CHANNEL FLASH MEMORY SYSTEM AND DATA ACCESS APPARATUS THEREOF - A data access method used in a multi-channel flash memory system includes: respectively writing a plurality of data into a plurality of buffer areas of a buffer unit through direct memory accessing; and sequentially reading the plurality of data from the plurality of buffer areas, and respectively and synchronously storing the plurality of read data into the plurality of flash memory units, wherein each of the plurality of data is a data block protected by an error correction code (ECC). | 10-14-2010 |
20100262764 | METHOD FOR ACCESSING STORAGE APPARATUS AND RELATED CONTROL CIRCUIT - A storage apparatus includes a first storage unit and at least a second storage unit. A method for accessing the storage apparatus generates a plurality of bad block lists regarding the plurality of the storage units, respectively, and according to at least one bad block indicated by a bad block list of the first storage unit, configures at least a good block in each second storage unit corresponding to the at least one bad block of the first storage unit as a replacement block of each second storage unit. Accordingly, the method generates a mapping result of each second storage unit according to a bad block list of the second storage unit and each replacement block, and accesses the storage apparatus according to the bad block list of the first storage unit and each mapping result. | 10-14-2010 |
20100318722 | DATA INTERLEAVING METHOD FOR STORAGE DEVICE AND RELATED STORAGE DEVICE - The present invention provides a data interleaving method for a storage device and a related storage device. The storage device comprises a plurality of non-volatile memory units, a buffer, and a processing unit. The method comprises: transmitting a plurality of first data required to be written to the plurality of non-volatile memory units to the buffer one by one; and respectively performing a plurality of interleaving operations to transmit the plurality of first data received by the buffer in sequence to the plurality of non-volatile memory units, respectively. The data interleaving method and the related storage device of the present invention only has to use one buffer, and thus the data interleaving method and the related storage device of the present invention can reduce requirement of buffer memory. | 12-16-2010 |
20110138109 | METHOD FOR WEAR-LEVELING AND APPARATUS THEREOF - A method for Wear-Leveling includes: utilizing a comparison circuit to compare an average erase count with an erase count of a first data block; and utilizing a first free block as a replacement for storing data content of the first data block so as to make the first data block become a free block when the erase count of the first data block is smaller than the average erase count. | 06-09-2011 |
20110138110 | METHOD AND CONTROL UNIT FOR PERFORMING STORAGE MANAGEMENT UPON STORAGE APPARATUS AND RELATED STORAGE APPARATUS - A storage apparatus has a first storage unit and a second storage unit. A method for performing storage management upon the storage apparatus includes: storing an input data into the first storage unit; and, while the input data is being stored into the first storage unit, checking whether the input data is continuous, wherein a portion of the input data which is not stored into the first storage unit yet will be stored into the first storage unit if the input data is found to be continuous, and the portion of the input data which is not stored into the first storage unit yet will be stored into the second storage unit if the input data is found to not be continuous. | 06-09-2011 |
20120066560 | ACCESS METHOD OF VOLATILE MEMORY AND ACCESS APPARATUS OF VOLATILE MEMORY - An access method of a volatile memory accesses the volatile memory via a block access fashion. The volatile memory includes a plurality of blocks. The method includes: performing a reading operation for a block having at least one known bad cell among the blocks, which includes reading a block data and an error correction code data corresponding to the block and applying the ECC data to correct data read from the at least one known bad cell to generate a corrected block data. | 03-15-2012 |
20120089756 | NETWORK-ATTACHED STORAGE AND METHOD OF CONFIGURING NETWORK-ATTACHED STORAGE - When a NAS apparatus is directly connected to a network and an external apparatus simultaneously, the external apparatus is able to access the NAS apparatus, and the NAS apparatus concurrently communicates with the network for executing a specific function. A method of configuring the NAS apparatus includes: allocating a first storage unit in the NAS apparatus; and setting an attribute of the first storage unit such that the first storage unit is allowed to be read by the NAS apparatus or the external apparatus, and written by the NAS apparatus or the external apparatus. | 04-12-2012 |
Chao-Yung Liu, Hsinchu City TW
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20110157372 | MULTIMEDIA APPARATUS HAVING FUNCTION OF DETECTING VIDEO SIGNAL CONNECTION - A multimedia apparatus has a function of detecting video signal connection. The multimedia apparatus includes plural video output terminals. The user may selectively connect one of the video output terminals with a TV set. The analog video signal outputted from the video output terminal is detected by a detector. In a case that the connection between the first video output terminal and the TV set is interrupted but the second video output terminal is connected with the TV set, the detector issues control signal. According to the control signal, a first digital-to-analog converter is disabled to stop outputting a first analog video signal through the first video output terminal, and a second digital-to-analog converter is enabled to output a second analog video signal through the second video output terminal. | 06-30-2011 |
Chen Pang Liu, Hsinchu City TW
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20110139609 | WATER BODY SELF-GENERATING ELECTROLYTIC REDUCTION MODULE - A water body self-generating electrolytic reduction module is applied to a water body containing oxidizing substances. The water body self-generating electrolytic reduction module includes a self-generating unit and an electrolysis unit. The self-generating unit is coupled to the electrolysis unit. When circulating in a water transmission pipeline, the water body drives the self-generating unit to generate an electric power and deliver the electric power to the electrolysis unit. Upon receiving the electric power, the electrolysis unit performs electrolysis on the water body circulating to the electrolysis unit, so that a reduction reaction occurs to the oxidizing substances in the water body. | 06-16-2011 |
Chen-Shen Liu, Hsinchu City TW
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20100307688 | TAG ABLATION MECHANISM AND TAG-AND-TAPE COMBINATION APPARATUS USING THE SAME - The present invention provides a tag ablation mechanism and a tag-and-tape combination apparatus using the same, wherein a driving gear is actuated to rotate by a rotating device by way of a lever to drive a driven gear to rotate so as to ablate a tag from a bottom paper extended from a tag roll on the driven gear. In the present invention, an ablated tag is capable of being combined with a tape so that the tag attached to the tape can be adhered to a packaged object. The mechanism and apparatus of the present invention are capable of adjusting a rotating arc length so as to handle various tags with different sizes and lengths and to complete tag ablation and tag-and-tape combination in each driving operation. | 12-09-2010 |
Chen-Yen Liu, Hsinchu City TW
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20090061578 | Method of Manufacturing a Semiconductor Microstructure - A method of manufacturing a semiconductor microstructure comprises: forming a standard CMOS wafer with at least one micro-electro-mechanical structure on a top surface of a silicon substrate, forming at least one sacrificial layer and one resist layer sequentially on the top surface of the CMOS wafer; forming an etching resist layer on a lower rear surface of the silicon substrate, etching the lower rear surface of the silicon base by deep reactive ion etching or wet etching to form a space corresponding to the micro-electro-mechanical structure, and etching the CMOS wafer and the sacrificial layer, respectively, to cause suspension of the micro-electro-mechanical structure. Such arrangements effectively prevent the occurrence of undercut, reduce the exposure and possibility of damage of the micro-electro-mechanical structure, and effectively save the package cost. | 03-05-2009 |
Chia-Ying Liu, Hsinchu City TW
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20110169991 | IMAGE SENSOR WITH EPITAXIALLY SELF-ALIGNED PHOTO SENSORS - An image sensor pixel includes a substrate doped to have a first conductivity type. A first epitaxial layer is disposed over the substrate and doped to also have the first conductivity type. A transfer transistor gate is formed on the first epitaxial layer. An epitaxially grown photo-sensor region is disposed in the first epitaxial layer and has a second conductivity type. The epitaxially grown photo-sensor region includes an extension region that extends under a portion of the transfer transistor gate. | 07-14-2011 |
20120080765 | METHOD OF DAMAGE-FREE IMPURITY DOPING FOR CMOS IMAGE SENSORS - A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed. | 04-05-2012 |
20120319230 | ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER - Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed. | 12-20-2012 |
20140035087 | ETCHING NARROW, TALL DIELECTRIC ISOLATION STRUCTURES FROM A DIELECTRIC LAYER - Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed. | 02-06-2014 |
Chieh-Chao Liu, Hsinchu City TW
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20100099351 | RECEIVER APPLYING CHANNEL SELECTION FILTER FOR RECEIVING SATELLITE SIGNAL AND RECEIVING METHOD THEREOF - A satellite receiver for receiving at least a target satellite signal includes a channel selection filter and a controller. The channel selection filter is provided with a plurality of channel selection settings conforming to characteristics of a plurality of satellite signals corresponding to different satellite systems, wherein each of the channel selection settings is to receive at least one of the satellite signals. The controller controls the channel selection filter to enable a target channel selection setting selected from the channel selection settings to thereby receive at least the target satellite signal. | 04-22-2010 |
20100178874 | METHOD FOR PERFORMING ACTIVE JAMMER SUPPRESSION ON ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS - A method for performing active jammer suppression on an electronic device includes: performing down conversion on a received signal having in-band interference, in order to obtain at least one down-converted received signal; performing down conversion on a jammer signal derived from a jammer source causing the in-band interference, in order to obtain at least one down-converted jammer signal; adjusting a phase and/or an amplitude of the down-converted jammer signal to obtain a jammer suppression signal; and performing jammer suppression according to the down-converted received signal and the jammer suppression signal. An apparatus for performing the active jammer suppression on the electronic device includes a received-signal down converter, at least one jammer down converter, and at least one adjustment module. In particular, the adjustment module is arranged to iteratively adjust the phase and/or the amplitude of the down-converted jammer signal to obtain an optimal version of the jammer suppression signal. | 07-15-2010 |
20120069766 | System and method of hybrid FDM/TDM coexistence interference avoidance - A hybrid FDM/TDM solution for in-device coexistence interference avoidance is proposed. A user equipment (UE) comprises a first radio transceiver and a second co-located radio transceiver. The UE detects coexistence interference between the two radios based on radio signal measurement. The UE sends an IDC interference indicator to its serving base station (eNB). The UE also reports IDC information including recommendation for FDM and TDM configurations to the eNB. The eNB receives the IDC interference indicator and evaluates whether to trigger FDM-based solution to mitigate the coexistence interference. The eNB also evaluates whether to trigger TDM-based solution to mitigate coexistence interference. The evaluation is based on the recommended FDM and TDM configurations. The eNB may trigger FDM-based solution, TDM-based solution, or FDM and TDM solution based on the evaluation results of the feasibility and effectiveness of each solution. | 03-22-2012 |
20140134889 | UNIVERSAL SERIAL BUS RECEPTACLE AND UNIVERSAL SERIAL BUS PLUG WITH STRIP-LINE ARCHITECTURE - A universal serial bus (USB) receptacle includes a core part and a conducting layer. The core part of the USB receptacle has a plurality of signal pads on a first side of the core part. The conducting layer is disposed on a second side of the core part of the USB receptacle. The second side of the core part of the USB receptacle is opposite to the first side of the core part. An associated USB plug is also provided. The USB plug includes a core part and a conducting layer. The core part of the USB plug has a plurality of signal pads on a first side of the core part of the USB plug. The conducting layer is disposed on a second side of the core part. The second side of the core part of the USB plug is opposite to the first side of the core part. | 05-15-2014 |
Ching Tu Liu, Hsinchu City TW
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20100267276 | Strap with transmission line functionality - A strap with transmission line functionality includes a strap body, a first connecting end and a second connecting end. The strap body has at least one signal line wrapped therein. The first connecting end is disposed at one end of the strap body and the second connecting end is disposed at an opposite end of the strap body so that signals can be transmitted between the first connecting end and the second connecting end via the signal line disposed in the strap body. The first connecting end is directly fixed to and electrically connected with an electronic product, and a signal connector is also disposed at the second connecting end to connect with an external device. The strap body is substantially looped into a circular form so as to be used as a wrist strap or a neck strap of the electronic product. | 10-21-2010 |
Chin-Kuang Liu, Hsinchu City TW
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20110139188 | WAFER CLEANING DEVCIE AND METHOD THEREOF - A wafer cleaning device comprising a wafer stage for holding a wafer having a surface to be washed, a first nozzle positioned above the wafer, a second nozzle positioned above the wafer. A first height is between the first nozzle and the surface and a second height is between the second nozzle and the surface, wherein the first height is shorter than the second height. | 06-16-2011 |
20140096800 | WAFER CLEANING DEVICE AND METHOD THEREOF - A wafer cleaning device comprising a wafer stage for holding a wafer having a surface to be washed, a first nozzle positioned above the wafer, a second nozzle positioned above the wafer. A first height is between the first nozzle and the surface and a second height is between the second nozzle and the surface, wherein the first height is shorter than the second height. | 04-10-2014 |
Chin-Tong Liu, Hsinchu City TW
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20090052148 | Structure Of Memory Stick - A structure of memory stick is provided, including a substrate case, a bottom case, a circuit board and a cover layer. One end of the circuit board includes a plurality of metal plates surrounded by a plurality of via holes. The circuit board is placed inside the bottom case so that the via holes correspond to the concave trenches of the bottom case. The substrate case covers the top of circuit board with the metal plates exposed. The cover layer is formed to cover the circumference of the engagement part of the substrate case and the bottom case, as well as the surrounding of the metal plates of the circuit board. The cover layer is formed by an inject molding process so that the substrate case, bottom case, circuit board and cover layer all engage together so as to achieve the object of higher assembly stability and waterproof effect. | 02-26-2009 |
Chung Che Liu, Hsinchu City TW
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20090158763 | REFRIGERANT FLOATING EXPANSION APPARATUS - A refrigerant floating expansion apparatus including a main body, a standpipe, a float element and a separation element is provided. The main body includes a base plate and a pipe-shaped housing. The standpipe fixed on the base plate has a second pipe opening and a third pipe opening. The pipe wall of the standpipe has at least an opening near the second pipe opening. The float element surrounds the standpipe for controlling a fluid-passing area of the opening. The separation element surrounding the float element is disposed on the base plate and forms an inner path with the pipe-shaped housing. The separation element has several fluid passageways near the base plate. A high-pressure fluid entering the main body is guided to pass through the fluid passageways to move the float element for controlling the fluid-passing area of the opening. Then, the high-pressure fluid is transferred to a low-pressure fluid. | 06-25-2009 |
20100211228 | METHOD AND SYSTEM FOR CONTROLLING COMPRESSOR - In the present invention, a method and a system for controlling a compressor are provided. The method includes the steps of: providing a condenser connected to the compressor, and at least one evaporator connected to the condenser; measuring an inlet pressure and an outlet pressure of the compressor to obtain a flow rate of the condensate; determining a secure flow rate and a demanding flow rate based on a total number of the at least one evaporator; comparing at least two of the flow rate, the demanding flow rate and the secure flow rate with each other to obtain a compared result; and controlling the compressor based on the comparing result. | 08-19-2010 |
20100229587 | AIR CONDITIONING SYSTEM - An air conditioning system includes a first circulation module and a second circulation module. Two circulation modules are joined by a heat exchanger. The first circulation is a modular refrigeration system includes a compressor, expansion device, and heat exchangers. The second circulation module includes a main liquid refrigerant tank, a number of distributed liquid refrigerant tanks, liquid pumps and a plurality of indoor units which includes a heat exchange device and a vapor propelling device. The heat exchange device is connected to the main liquid tank. The vapor propelling device propels the working fluid in a saturated vapor state to the first heat exchanger, thus forming a working fluid loop. It can be switched between the heating and cooling modes. | 09-16-2010 |
Chun-Tiao Liu, Hsinchu City TW
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20090207574 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element. | 08-20-2009 |
20100102917 | INDUCTOR - An inductor includes a first core, a second core, a protruding structure, at least two gaps and a conducting wire. The first core has a protruding portion. The second core is disposed opposite to the first core. The protruding structure protrudes from the protruding portion of the first core and toward the second core. The at least two gaps are between the protruding portion of the first core and the second core. The conducting wire winds around at least one of the first and second cores. The conducting wire has a specific resistance value of 1.42 μΩm or lower. | 04-29-2010 |
20100308950 | CHOKE - A choke including a core and a hollow coil is provided. The core includes a first core body and a second core body. The first core body includes a pillar. The second core body is a flat plate and has an opening. An end of the pillar is suitable to be disposed in the opening and joined to the same. The hollow coil is fitted on the pillar. | 12-09-2010 |
20110057761 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a bridge element is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The bridge element spans across the metal element in a direction across direction of current flow in the metal element, wherein the bridge element facilitates breaking of the metal element upon melting. | 03-10-2011 |
20110090648 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element. | 04-21-2011 |
20110278704 | THREE-DIMENSIONAL PACKAGE STRUCTURE - A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The shielding layer is disposed between the control component and at least part of the magnetic body to inhibit or reduce EMI (Electro-Magnetic Interference) from the energy storage element and to get a tiny package structure. The three-dimensional package structure is applicable to a POL (Point of Load) converter. | 11-17-2011 |
20120014079 | ELECTRONIC PACKAGE STRUCTURE - An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element. | 01-19-2012 |
20120236519 | ELECTRONIC PACKAGE STRUCTURE - The present invention discloses an electronic package structure. The body has a top surface with a cavity thereon, the first conductive element is disposed in the cavity, and the second conductive element is disposed in the body. The first external electrode electrically connected to the first conductive element and the second external electrode electrically connected to the second conductive element are both disposed on the top surface of the body or a first surface formed by the top surface of the encapsulation compound and the exposed portions of the top surface of the body which are not covered by the encapsulation compound. | 09-20-2012 |
20130001756 | THREE-DIMENSIONAL PACKAGE STRUCTURE - The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer. | 01-03-2013 |
20130321119 | PROTECTIVE DEVICE - A protective device including a substrate, a conductive section and a bridge element is provided. The conductive section is supported by the substrate, wherein the conductive section comprises a metal element electrically connected between first and second electrodes. The metal element serves as a sacrificial structure having a melting point lower than that of the first and second electrodes. The bridge element spans across the metal element in a direction across direction of current flow in the metal element, wherein the bridge element facilitates breaking of the metal element upon melting. | 12-05-2013 |
Chu-Yung Liu, Hsinchu City TW
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20110018049 | Charge trapping device and method for manufacturing the same - The present invention relates to a charge trapping device and a method for manufacturing the same. The charge trapping device includes: a substrate having a first surface and an opposite second surface; a tunneling insulating layer, disposed on the first surface of the substrate; a charge trapping layer, disposed on the tunneling insulating layer and including a first dielectric layer and a second dielectric layer, in which the first dielectric layer is connected to the tunneling insulating layer, the second dielectric layer is disposed over the first dielectric layer, and a conduction band offset between the first dielectric layer and the substrate is larger than that between the second dielectric layer and the substrate; and a blocking insulating layer, disposed on the charge trapping layer and connected to the second dielectric layer. Accordingly, the charge trapping device of the present invention has excellent programming, and erasing and charge retention properties. | 01-27-2011 |
Der-Zheng Liu, Hsinchu City TW
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20110013561 | Apparatus And Method For Adjusting Transmission Power Of Communication System - The present invention provides a method for adjusting transmission power of a communication system having a first terminal and a second terminal. In accordance with a preferred embodiment, the method comprises steps of: (a) repeatedly transmitting a detecting packet from the first terminal to the second terminal by sequentially using one of a variety of transmission powers; (b) receiving a responding packet from the second terminal, wherein the responding packet corresponds to the one of the variety of transmission powers; and (c) choosing at least one from the variety of the transmission powers for transmitting at least a data packet to the second terminal therewith based on the responding packet from the second terminal. | 01-20-2011 |
20120213104 | APPARATUS FOR ADJUSTING POWER AND METHOD THEREOF - A power adjusting apparatus communicating with a remote terminal is provided. The apparatus includes: a transceiving unit transmitting a plurality of test packets by a plurality of powers; a processing unit coupled to the transceiving unit, and deciding a transmission power for transmitting a subsequent packet according to at least one retransmission number of transmitting the test packets. | 08-23-2012 |
Ding Kun Liu, Hsinchu City TW
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20080225283 | IMAGING SYSTEM WITH HIGH-SPECTRUM RESOLUTION AND IMAGING METHOD FOR THE SAME - An imaging system comprises a light source module configured to generate a combination beam, a controller configured to control the light source module, an image-capturing module configured to capture the reflected beam by a sample. The light source module comprises a plurality of light-emitting devices configured to emit lights of different wavelengths, and the controller is configured to drive the light-emitting devices to emit the lights to form the combination beam consisting of at least two lights of different wavelengths. An imaging method comprises the steps of forming a first combination beam consisting essentially of at least two lights of different wavelengths, capturing the reflected first combination beam by a sample to have a first image, forming a second combination beam consisting of at least two lights of different wavelengths and capturing the reflected second combination beam by the sample to have a second image. | 09-18-2008 |
Hsiang Sheng Liu, Hsinchu City TW
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20110219166 | USB CONTROLLER AND EXECUTION METHOD THEREOF - A universal serial bus (USB) controller and an execution method thereof are presented. The USB controller stores settings of different sensors in an external memory, or stores modified program codes when an originally stored program has bugs. With the execution of the set configurations, the program section to be execute is dynamically loaded into the random access memory (RAM) of the USB controller, so as to reduce the size of the RAM, thereby providing a large program modification space and avoiding the entire chip (the USB controller) from being stretched by an excessive large RAM. | 09-08-2011 |
20120206971 | PROGRAMMABLE MEMORY DEVICE AND MEMORY ACCESS METHOD - A programmable memory device includes a plurality of one-time programmable (OTP) memory units, a search unit, a writing unit, and a reading unit. Each OTP memory unit is assigned an address. The search unit searches for the first writable OTP memory unit from the plurality of OTP memory units in a writing operation, or searches for the last programmed OTP memory unit from the plurality of OTP memory units in a reading operation. The writing unit writes data to be written and the bit length of the data to the first writable OTP memory unit. The reading unit sequentially reads data from the last programmed OTP memory unit. | 08-16-2012 |
J. C. Liu, Hsinchu City TW
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20080217719 | Method For Reducing Crosstalk In Image Sensors Using Implant Technology - The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy. | 09-11-2008 |
Jen-Chi Liu, Hsinchu City TW
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20090106438 | Method of Setting IP Address to Network Device - A method for setting an IP (Internet Protocol) address to a network device is provided. In this method, a step is first performed to check if a DHCP server exists in a network domain and obtain a checking result. When the checking result is yes, a dynamic IP address is obtained from the DHCP server and is set to a network device. When the checking result is no, a predetermined IP address and a predetermined gateway address are set to the network device. | 04-23-2009 |
20090110175 | Gateway and System and Auto Call-Transferring Method for VOIP - A VoIP gateway, a VoIP phone system and an auto call-transferring method for VoIP are disclosed. The method is used in the VoIP gateway with a plurality of predetermined IDs, wherein the method comprises the steps of: receiving a call connection request for a first predetermined ID form a calling end point; detecting if the first predetermined ID is in use; and establishing a call connection between the calling end point and a second predetermined ID when the first predetermined ID is in use. | 04-30-2009 |
Jin-King Liu, Hsinchu City TW
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20090161944 | TARGET DETECTING, EDITING AND REBUILDING METHOD AND SYSTEM BY 3D IMAGE - A method and system for target detecting, editing and rebuilding by 3D image is provided, which comprises an inputting and picking unit, a training and detecting unit, a displaying and editing unit and a rebuilding unit. The inputting and picking unit receives a digital image and a LiDAR data and picks up a first parameter to form a 3D image. The training and detecting unit selects a target, picks up a second parameter therefrom, calculates the second parameter to generate a threshold and detects the target areas in the 3D image according to the threshold. The displaying and editing unit sets a quick selecting tool according to the threshold and edits the detecting result. The rebuilding unit sets a buffer area surrounding the target, picks up a third parameter therefrom and calculates the original shape of the target by the Surface Fitting method according to the third parameter. | 06-25-2009 |
Jonq-Min Liu, Hsinchu City TW
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20090017295 | FLUORINATED CYCLIC OLEFIN ELECTRET FILM - The present invention provides a fluorinated cyclic olefin electret film including a fluorinated cyclic olefin polymer film characterized by having a cyclic olefin polymer grafted with a fluorocarbon alkyl group, and a parylene film over the fluorinated cyclic olefin polymer film. | 01-15-2009 |
Jue-Wen Liu, Hsinchu City TW
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20100235595 | DATA STORAGE SYSTEM AND BACKUP METHOD THEREOF - A data storage system and the backup method thereof are provided. The data storage system includes a storage device and a storage controller. The storage controller is coupled to the storage device and used for dividing the storage device into a primary data block and a backup data block and setting the data storage system to operate under one of a real time backup mode and a non-real time backup mode. Under the non-real time backup mode, the storage controller backups the data stored in the primary data block to the backup data block when the data storage system is idle. | 09-16-2010 |
Jun-Chin Liu, Hsinchu City TW
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20110073038 | GAS DISTRIBUTION PLATE AND APPARATUS USING THE SAME - The present invention provides a gas distribution plate for providing at least two gas flowing channel. In one embodiment, the gas distribution plate has a first flowing channel, at least a second flowing channel disposed around the first flowing channel, and a tapered opening communicating with the first and the second flowing channel. In another embodiment, the gas distribution plate has a first flowing channel passing through a first and a second surface of the gas distribution plate, a second flowing channel paralleling to the first surface and a third flowing channel disposed at the second surface and communicating with the second flowing channel. The ends of the first and the third flowing channel have a tapered opening respectively. Besides, the present further provides a gas distribution apparatus for allowing at least two separate gases to be delivered independently into a process chamber while enabling the gases to be mixed completely after entering the processing chamber. | 03-31-2011 |
20110094573 | Solar cell and method for fabricating the same - A solar cell and a method for fabricating the same are provided. The solar cell includes a first electrode, a second electrode, a photoelectric conversion layer and a non-conductive reflector. The first electrode including a nano-metal transparent conductive layer is disposed on a transparent substrate. The nano-metal transparent conductive layer substantially contacts with the photoelectric conversion layer. The second electrode is disposed between the photoelectric conversion layer and the transparent substrate. The photoelectric conversion layer is disposed between the first and the second electrodes. The non-conductive reflector is disposed on the first electrode. | 04-28-2011 |
20110247559 | GAS DISTRIBUTION SHOWER MODULE AND FILM DEPOSITION APPARATUS - A gas distribution shower module and a film deposition apparatus are provided. The gas distribution shower module includes a first distributor, a second distributor, a third distributor and a fourth distributor. The second distributor is under the first distributor, the third distributor is under the second distributor, the fourth distributor is under the third distributor, and a distance is between the fourth distributor and the third distributor. The third distributor is divided into an inner region and an outer region, and an area ratio of the inner region to the outer region is from 1:1 to 1:5. Furthermore, the third distributor has a plurality of gas holes in the inner region and the outer region, and an area ratio of the gas holes in the inner region to the gas holes in the outer region is from 1:1 to 1:5. | 10-13-2011 |
20130037094 | CONDUCTIVE PASTES AND SOLAR CELLS COMPRISING THE SAME - A conductive paste is provided. The conductive paste includes a polymer matrix and a filler blended in the polymer matrix, wherein the filler is non-spherical and at least one dimension of the filler has a length greater than or equal to λ/2n, wherein λ is a wavelength of light reflected by the conductive paste and n is a refractive index of the filler, and the polymer matrix and the filler have a weight ratio of 3:7 to 7:3. | 02-14-2013 |
Keh-Shium Liu, Hsinchu City TW
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20100061118 | Lens Beam-Concentrating Device - A lens beam-concentrating device comprises at least one light-emitting diode light source disposed on a lateral edge of a light guide plate. The light source emits light rays toward the light guide plate, after the light rays are directed by the light guide plate, a parallel light beam will emit from an emission surface of the light guide plate to form a plane light source. A first lens element and a second lens element are arranged in front of the light emission surface of the light guide plate for adjusting and collimating the parallel beam, so as to ensure the light rays to emit out of the beam-concentrating device parallel to each other. | 03-11-2010 |
Kuang-Chih Liu, Hsinchu City TW
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20090040086 | DWA STRUCTURE AND METHOD THEREOF, DIGITAL-TO-ANALOG SIGNAL CONVERSION METHOD AND SIGNAL ROUTING METHOD - A data weighted average (DWA) structure including a first delay unit, a binary to thermometer code converter, an adder, a second delay unit, a decoder, a barrel shifter, and a plurality of signal lines is provided. The first delay unit delays an input digital signal. The binary to thermometer code converter converts an output signal of the first delay unit into a thermal code. The second delay unit delays an output signal of the adder. The adder adds the input digital signal to an output signal of the second delay unit. The decoder decodes the output signal of the second delay unit. The barrel shifter generates an output signal from the thermal code in accordance with an output signal of the decoder. The signal lines route the output signal of the barrel shifter into two independent control signal groups. | 02-12-2009 |
20090110102 | SIGNAL ROUTING METHOD - A signal routing method adapted to a DWA structure is provided. The signal routing method at least includes following steps. An M-bit input digital signal is provided. The odd bit in the input digital signal is routed into a low-bit signal of an output digital signal, and the even bit in the input digital signal is routed into a high-bit signal of the output digital signal, wherein the output digital signal has M bits. | 04-30-2009 |
20100281222 | CACHE SYSTEM AND CONTROLLING METHOD THEREOF - A cache system and a method for controlling the cache system are provided. The cache system includes a plurality of caches, a buffer module, and a migration selector. Each of the caches is accessed by a corresponding processor. Each of the caches includes a plurality of cache sets and each of the cache sets includes a plurality of cache lines. The buffer module is coupled to the caches for receiving and storing data evicted due to conflict miss from a source cache line of a source cache set of a source cache among the caches. The migration selector is coupled to the caches and the buffer module. The migration selector selects, from all the cache sets, a destination cache set of a destination cache among the caches according to a predetermined condition and causing the evicted data to be sent from the buffer module to the destination cache set. | 11-04-2010 |
Mao-Shin Liu, Hsinchu City TW
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20110100975 | CARRIER FOR HEATING AND KEEPING WARM - A carrier for heating and keeping warm used for directly carrying food to-be kept warm is provided. The carrier for heating and keeping warm includes a carrier and at least a high melt point-electric heating alloy pattern. The carrier has a first surface and a second surface opposite to the first surface. The food is suitable for being directly placed on the first surface. A material of the second surface is ceramics or glass so that the second surface | 05-05-2011 |
20120111872 | COOKING UTENSIL AND MANUFACTURING METHOD THEREOF - A cooking utensil and a manufacturing method thereof are provided. The cooking utensil includes a cooking body, a first metal-ceramic composite layer having an electromagnetic property and a second metal-ceramic composite layer having a heat conductive property. The cooking body has an external bottom surface. The first metal-ceramic composite layer is disposed on the external bottom surface of the cooking body. The second metal-ceramic composite layer is disposed on the first metal-ceramic composite layer. The cooking utensil is suitable for both an induction cooker and a gas burner. | 05-10-2012 |
20130224392 | METHOD FOR PROVIDING A COATING LAYER WITH PROTECTION AND THERMAL CONDUCTIVITY - A method for providing a coating layer with well protection and thermal conductivity, providing a coating layer material, the coating layer material set on a workpiece to form a coating layer with thickness 160˜500 micrometer. The coating layer is able to avoid wear of the surface of the workpiece, and has well protection and thermal conductivity, to avoid the situation of damage or mechanical property changing occurred due to the temperature of the surface rising caused by the friction. | 08-29-2013 |
Ming-Chyi Liu, Hsinchu City TW
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20080237761 | SYSTEM AND METHOD FOR ENHANCING LIGHT SENSITIVITY FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A system and method for enhancing light sensitivity of a back-side illumination image sensor are described. An integrated circuit includes a substrate and an image sensor device comprising at least one transistor formed over a first surface of the substrate and a photosensitive region. A color filter is disposed over a second surface of the substrate opposite the first surface thereof. A micro-lens structure is disposed between the second surface of the substrate and the color filter. | 10-02-2008 |
20080246152 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern. | 10-09-2008 |
20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 05-14-2009 |
20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 05-21-2009 |
20100062611 | Method and Apparatus for Thinning a Substrate - Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH. | 03-11-2010 |
20100151615 | METHODS FOR FABRICATING IMAGE SENSOR DEVICES - Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer. | 06-17-2010 |
20110177668 | METHOD OF MAKING A THIN FILM RESISTOR - A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole. | 07-21-2011 |
20110318898 | HARD MASK FOR THIN FILM RESISTOR MANUFACTURE - Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer. | 12-29-2011 |
20120211759 | STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER - The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions. | 08-23-2012 |
20140070360 | FinFETs with Vertical Fins and Methods for Forming the Same - In a method for forming a device, a ( | 03-13-2014 |
20140273424 | Method of Conducting a Direction-Specific Trimming Process for Contact Patterning - The present disclosure discloses a method of fabricating a semiconductor device. A first layer is formed over a substrate. A patterned second layer is then formed over the first layer. The patterned second layer includes an opening. A spacer material is then deposited in the opening, thereby reducing the opening in a plurality of directions. A direction-specific trimming process is performed to the spacer material and the second layer. Thereafter, the first layer is patterned with the second layer. | 09-18-2014 |
20150021665 | TRANSISTOR HAVING BACK-BARRIER LAYER AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate, a back-barrier layer over the channel layer, and an active layer over the back-barrier layer. The back-barrier layer has a band gap discontinuity with the channel layer. The band gap of the active layer is less than the band gap of the back-barrier layer. A two dimensional electron gas (2-DEG) is formed in the channel layer adjacent an interface between the channel layer and the back-barrier layer. | 01-22-2015 |
20150021666 | TRANSISTOR HAVING PARTIALLY OR WHOLLY REPLACED SUBSTRATE AND METHOD OF MAKING THE SAME - A transistor includes a substrate, a channel layer over the substrate, an active structure over the channel layer, a gate electrode over the channel layer, and a drain electrode over the channel layer. The active structure is configured to cause a two dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active structure. The gate electrode and the drain electrode define a first space therebetween. The substrate has a first portion directly under the first space defined between the gate electrode and the drain electrode, and the first portion has a first electrical conductivity value less than that of intrinsic silicon and a thermal conductivity value greater than that of intrinsic silicon. | 01-22-2015 |
20150069574 | INTEGRATED CIRCUIT AND MANUFACTURING AND METHOD THEREOF - A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 03-12-2015 |
20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 03-12-2015 |
Ming Hsin Liu, Hsinchu City TW
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20100303662 | Screw compressors - A screw compressor includes a housing, a motor stator, a motor rotor, a helical screw rotor, a motor rotor stop, a screw fastener, and a third bearing. The helical screw rotor includes an extension section, a motor coupling section, a first supporting section, a helical screw section, and a second supporting section. The motor rotor stop includes two flange portions, wherein one flange portion is sleeved with the extension section and abuts axially upon the effective sensing section of the motor rotor. The third bearing is interposed between the other flange portion and the housing cap. The screw fastener extends through the motor rotor stop and is threadedly engaged into a thread hole of the helical screw rotor and then biases axially upon the motor rotor stop. Therefore, the motor rotor is secured more firmly, and that a compressor shaft maintains a stable running. | 12-02-2010 |
Neng Liu, Hsinchu City TW
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20090030600 | Method of providing navigation information by recalculating navigation route - A method of providing navigation information by recalculating a navigation route is used in a global positioning device. The method reads an original navigation route first. If another new navigation route can be read again, it shows that the global positioning device is deviated from the original navigation route, and route data of the original navigation route and the new navigation route are compared to generate a comparing information such as an overlapped position of the two navigation routes, and the time or distance required to return to the original new navigation route from the new navigation route and display the comparing information on the global positioning device to remind the users. The present invention can greatly reduce the tension of a user who is not familiar with the routes and road conditions. | 01-29-2009 |
20090177374 | Method for real-time updating background weather patern of electronic map - A method for a navigation device to change a background weather pattern of an electronic map comprises steps of: reading a plurality of positioning signals received by a positioning module and calculating a current location of the navigation accordingly; reading from a map database and a real-time weather database, respectively, an electronic map and a background weather pattern that correspond to the current location, and outputting the electronic map and the background weather pattern corresponding to the current location on a display device; determining whether it is necessary to change the electronic map corresponding to the current location; and when it is necessary, reading from the real-time weather database a background weather pattern corresponding to an updated current location and replacing the presently displayed electronic map and background weather pattern with an electronic map and a background weather pattern corresponding to the updated current location. | 07-09-2009 |
20090177387 | Method of planning pedestrian navigation route - The present invention discloses a method of planning a pedestrian navigation route, and the method is applied to a pedestrian navigation device. The pedestrian navigation device includes a map database having a pedestrian road data and a driving route data of at least one public transportation means. In the method, when the pedestrian navigation device is planning a pedestrian navigation route, the pedestrian navigation device reads start position information and end position information, plans a pedestrian road and a driving route of different public transportation means between a start position and an end position according to a pedestrian road data and a driving route data, and then compiles the same into a pedestrian navigation route. The invention allows a pedestrian to reach an end position (or destination) selectively by walking along the planned pedestrian road or taking a ride of the selected public transportation means. | 07-09-2009 |
20090216436 | NAVIGATION DEVICE CAPABLE OF DISPLAYING LOCAL LABELS AND METHOD THEREOF - The present invention discloses a navigation device which is capable of displaying local labels and a method thereof. The navigation device comprises a map database, a navigation module, a positioning module and a display interface. The map database is capable of storing at least one electronic map, comprising a plurality of map blocks. The navigation module is capable of providing a navigation route located on at least one of the plurality of map blocks, and the navigation route comprises a starting point, a plurality of local labels and a destination. The local labels are located from the starting point to the destination in order. The positioning module is capable of providing at least one positioning location. The display interface is capable of displaying at least one of the plurality of map blocks where the navigation route is located on according to the positioning location, and displays at a next local label on the map blocks. The next local label is located on one end of the navigation route toward a direction of the destination. | 08-27-2009 |
20110112757 | Navigation System and Method Thereof - A navigation system includes a storage module, a positioning module, a time module, and an integration module. The integration module is electrically connected to the storage module, the positioning module and the time module, and compares a navigation keyword with a plurality of landmark names of a map data stored in the storage module. When at least one of the landmark names is found to be partially or completely the same as the navigation keyword and is currently in opening hours, the integration module selects one of these landmark names and creates a navigation path directed to the selected landmark name based on the orientation data of the selected landmark name, positioning information output by the positioning module, and time information output by the time module. A navigation method implemented based on the above navigation system is also disclosed. | 05-12-2011 |
Nian-Qiang Liu, Hsinchu City TW
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20110140805 | PHASE SHIFTER - A phase shifter having a chamber in flat-shaped solid state, one side of which is recessed to form a holding space, and a lower coupling circuit board, assembled into the holding space. The lower coupling surface of the lower coupling circuit board is fitted with two coupling strips arranged at interval. One end of the coupling strips is provided with a cable coupling portion. An upper coupling strip is overlapped onto the lower coupling circuit board in a U-shaped pattern. The upper coupling strip is provided with an upper coupling surface for coupling with the coupling strips of the lower coupling circuit board. A slider has a driving end and a driven end, the driving end being used to connect and drive the upper coupling strip, and the driven end protrudes out of the chamber's holding space. A cover plate is used to seal the chamber's holding space. | 06-16-2011 |
20120194295 | PHASE SHIFTER WITH REVERSELY CONFIGURED ELECTRIC REGULATION UNITS - The present invention provides a phase shifter with reversely configured electric regulation units. The phase shifter has a chamber with a holding space, a first feeder unit and a second feeder unit at the sides of the holding space, and at least one reversely configured electric regulation unit. The regulation unit contains a first coupling set with a movable and a fixed coupling, and a second coupling set with a movable and a fixed coupling. A sync linkage mechanism is used to link the respective movable couplings. A push-pull unit is linked to a driven connection of the sync linkage mechanism. A cover plate seals the holding space. The phase shifter configuration makes it possible to reduce markedly the volume and space of the phase shifter, cut down the manufacturing cost and improve the mating accuracy with higher applicability. | 08-02-2012 |
Pei-Ching Liu, Hsinchu City TW
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20110199581 | OPTICAL PROJECTION SYSTEM AND METHOD FOR REDUCING UNESSENTIAL BEAMS FORMED THEREIN - An optical projection system includes a light source module, a field lens, a fly-eye lens, a light valve and a projection lens. The field lens is disposed on a propagation path of a light beam, where the light beam emitted from the light source module comprises a transmission light beam passing through the field lens and a reflection light beam reflected by the field lens. The fly-eye lens is disposed on the propagation path of the light beam and between the light source module and the field lens to homogenize the light beam, where the fly-eye lens includes a plurality of lens elements arranged in an array, the reflection light beam passes through the lens element via a transmissive region of the lens element, and at least one of an opaque structure, a light-diffusing structure and a light-deflecting structure is formed on the transmissive region. | 08-18-2011 |
Pi-Hai Liu, Hsinchu City TW
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20090296545 | APPARATUS AND METHOD FOR DEMODULATING INPUT SIGNAL MODULATED FROM REFERENCE SIGNAL AND DATA SIGNAL - An apparatus and method for demodulating an input signal modulated from a reference signal and a data signal are disclosed. The apparatus includes a determining unit, a first calculating unit, and a comparing unit. The determining unit is utilized for determining a plurality of first calculating timings of changing different calculating modes according to the input signal. The first calculating unit is coupled to the determining unit and utilized for generating a first calculating result of the input signal according to the first calculating timings and the calculating modes thereof. The comparing unit is coupled to the first calculating unit and utilized for generating a comparing result according to the first calculating result of the input signal and a threshold setting, and for outputting a demodulated data of the input signal according to the comparing result. | 12-03-2009 |
Pin-Miao Liu, Hsinchu City TW
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20090189883 | Flat Display Apparatus and Control Circuit and Method for Controlling the same - In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal. | 07-30-2009 |
Po-Yueh Liu, Hsinchu City TW
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20100326357 | NOZZLE AND FURNACE HAVING THE SAME - A nozzle and a furnace having the same are provided. The furnace has a high vacuum fitting used to assemble the nozzle to the furnace. The nozzle includes a first tube part and a second tube part connecting to the first tube part. In addition, an immobilization device is disposed on a surface of the first tube part. The immobilization device is corresponding to an o-ring of the high vacuum fitting and sheathed by the o-ring to steadily immobilize the nozzle to the furnace. | 12-30-2010 |
Ruey-Hsin Liu, Hsinchu City TW
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20080237703 | HIGH VOLTAGE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region. | 10-02-2008 |
20090283841 | SCHOTTKY DEVICE - An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer. | 11-19-2009 |
Ru-Gun Liu, Hsinchu City TW
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20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
20110023002 | DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM - A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC. | 01-27-2011 |
20110124193 | CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout. | 05-26-2011 |
20110161907 | Practical Approach to Layout Migration - The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node. | 06-30-2011 |
20110197168 | DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed. | 08-11-2011 |
20110204470 | METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN - An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density. | 08-25-2011 |
20110214101 | METHOD OF THERMAL DENSITY OPTIMIZATION FOR DEVICE AND PROCESS ENHANCEMENT - The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance. | 09-01-2011 |
20110217630 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material. | 09-08-2011 |
20110230998 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
20110243424 | METHOD AND APPARATUS FOR MONITORING MASK PROCESS IMPACT ON LITHOGRAPHY PERFORMANCE - The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern. | 10-06-2011 |
20110245949 | METHOD AND APPARATUS OF PATTERNING SEMICONDUCTOR DEVICE - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 10-06-2011 |
20110252387 | METHOD AND APPARATUS FOR REDUCING IMPLANT TOPOGRAPHY REFLECTION EFFECT - Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a corresponding developed photoresist feature of a photoresist layer; modifying the CD of the design feature to compensate for the difference, thereby generating a modified IC design layout; and making a mask using the modified IC design layout. | 10-13-2011 |
20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
20110296360 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method and system checks a double patterning layout and outputs a representation of G0-rule violations and critical G0-spaces. The method includes receiving layout data having patterns, determining whether each distance between adjacent pattern elements is a G0-space, find all G0-space forming a G0-rule violation, finding all G0-space that are critical G0-spaces, and outputting a representation of G0-rule violations and critical G0-spaces to an output device. By resolving G0-rule violations and critical G0-spaces, a design checker can effectively generate a double patterning technology (DPT) compliant layout. | 12-01-2011 |
20120040278 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. | 02-16-2012 |
20120045712 | EXTREME ULTRAVIOLET LIGHT (EUV) PHOTOMASKS, AND FABRICATION METHODS THEREOF - Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarizing process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber is substantially co-planar with the top surface of the hard mask layer. | 02-23-2012 |
20120072874 | DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION AND MASK RULE CHECK ENFORCEMENT - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC. | 03-22-2012 |
20120074400 | MULTIPLE EDGE ENABLED PATTERNING - Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance. | 03-29-2012 |
20120115073 | SUB-RESOLUTION ROD IN THE TRANSITION REGION - The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature. | 05-10-2012 |
20120131528 | METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT - A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color. | 05-24-2012 |
20120135600 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G | 05-31-2012 |
20120144361 | PARAMETERIZED DUMMY CELL INSERTION FOR PROCESS ENHANCEMENT - The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value. | 06-07-2012 |
20120192126 | SYSTEMS AND METHODS PROVIDING ELECTRON BEAM PROXIMITY EFFECT CORRECTION - A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium. | 07-26-2012 |
20120227018 | Method and Apparatus of Patterning Semiconductor Device - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 09-06-2012 |
20120237877 | ELECTRON BEAM DATA STORAGE SYSTEM AND METHOD FOR HIGH VOLUME MANUFACTURING - The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table. | 09-20-2012 |
20130024822 | DOUBLE PATTERNING METHODOLOGY - Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process. | 01-24-2013 |
20130055173 | GEOMETRIC PATTERN DATA QUALITY VERIFICATION FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying. | 02-28-2013 |
20130061187 | STRIPING METHODOLOGY FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system. | 03-07-2013 |
20130061196 | TARGET-BASED DUMMY INSERTION FOR SEMICONDUCTOR DEVICES - The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout. | 03-07-2013 |
20130080980 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method including receiving layout data representing the plurality of patterns, the layout data including a plurality of layers and identifying spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G | 03-28-2013 |
20130130410 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask. | 05-23-2013 |
20130258304 | ENHANCED EUV LITHOGRAPHY SYSTEM - The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location. | 10-03-2013 |
20130270704 | Semiconductor Device with Self-Aligned Interconnects - A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface. | 10-17-2013 |
20140101623 | METHOD OF MERGING COLOR SETS OF LAYOUT - A method includes determining one or more potential merges corresponding to a color set A | 04-10-2014 |
20140170537 | METHOD OF DEFINING AN INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern. | 06-19-2014 |
20140248555 | EXTREME ULTRAVIOLET LIGHT (EUV) PHOTOMASKS, AND FABRICATION METHODS THEREOF - An extreme ultraviolet photomask comprises a reflective layer over a substrate, a capping layer over the reflective layer, a hard mask layer over the capping layer, and an absorber. The absorber is in the hard mask layer, the capping layer and the reflective layer. | 09-04-2014 |
Shang-I Liu, Hsinchu City TW
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20100207963 | GAMMA VOLATGE GENERATING APPARATUS AND GAMMA VOLTAGE GENERATOR THEREOF - A gamma voltage generator including an operation amplifier, a first reference impedance unit, a second reference impedance unit, a first variable impedance unit, a second variable impedance unit, and a select unit is provided. The operation amplifier generates an amplified output voltage. The first reference impedance unit receives a first gamma voltage, and the second reference impedance unit receives a second gamma voltage. The first variable impedance unit provides a first variable impedance, and the second variable impedance unit receives the first gamma voltage and provides a second variable impedance. The select unit selects the amplified output voltage or the first gamma voltage according to a control signal to generate an interpolated gamma output voltage. | 08-19-2010 |
Shih-Jr Liu, Hsinchu City TW
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20090060991 | GLUTATHIONE BASED DELIVERY SYSTEM - A delivery system. The delivery system includes a carrier or an active compound and a glutathione or a glutathione derivative grafted thereon. The invention also provides a compound including a moiety comprising a vitamin E derivative or a phospholipid derivative, a polyethylene glycol (PEG) or a polyethylene glycol derivative bonded thereto, and a glutathione (GSH) or a glutathione derivative bonded to the polyethylene glycol or the polyethylene glycol derivative. | 03-05-2009 |
20100166849 | GLUTATHIONE BASED DELIVERY SYSTEM - A delivery system. The delivery system includes a carrier or an active compound and a glutathione or a glutathione derivative grafted thereon. The invention also provides a compound including a moiety comprising a vitamin E derivative or a phospholipid derivative, a polyethylene glycol (PEG) or a polyethylene glycol derivative bonded thereto, and a glutathione (GSH) or a glutathione derivative bonded to the polyethylene glycol or the polyethylene glycol derivative. | 07-01-2010 |
Shih-Kwan Liu, Hsinchu City TW
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20090233112 | MULTILAYER ZINC OXIDE VARISTOR - Enclosed is a multilayer zinc oxide (ZnO) varistor having a body portion, internal electrodes extending from both sides to the interior of the body portion respectively, and terminal electrodes disposed at both sides of the body portion. The multilayer zinc oxide is characterized in that: the components of said body portion include at least 90 mole % ZnO, 0.1 to 5.0 mole % antimony oxide functional additives, 0.01 to 1.0 mole % praseodymium oxide functional additives, and 0.01 to 10.0 wt. % glass; the sum amount of these metal oxides is less than 99.95 mole %. | 09-17-2009 |
20110316658 | THIN TYPE COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - A thin type common mode filter includes an insulating flexible substrate, a first magnetic material layer, a first coil leading layer, a coil main body multi-layer, a second coil leading layer, and a second magnetic material layer. The first coil leading layer is formed on a first surface of the flexible substrate, and the first coil leading layer is formed on a second surface of the flexible substrate opposite to the first surface. The coil main body multi-layer, the second coil leading layer, and the second magnetic material layer are sequentially stacked on the first coil leading layer. | 12-29-2011 |
20120281338 | ALUMINUM ELECTROLYTIC CAPACITOR AND METHOD OF MANFACTURING THE SAME - An aluminum electrolytic capacitor includes an aluminum foil substrate, a porous aluminum layer, an insulating layer, an electrically conductive polymer material, an electrically conductive material, and at least two terminal electrodes. The porous aluminum layer is attached to the aluminum foil substrate. The insulating layer is formed on the porous aluminum layer. The electrically conductive polymer material overlays the insulating layer. The terminal electrodes respectively connect to the aluminum foil and the electrically conductive material. | 11-08-2012 |
20130062656 | THERMALLY ENHANCED OPTICAL PACKAGE - A thermally enhanced optical package includes a heat conducting module configured to dissipate the heat generated from an optical device, a plurality of insulating pads disposed on a heat conducting substrate, and at least one electrical conducting pad disposed on the insulating pads. The heat conducting module includes a heat conducting substrate and a plurality of heat conducting pillars, and the optical device is a light emitting diode chip or a light emitting diode die in the present embodiments. The thermally enhanced optical package is further characterized in a simple manufacturing procedure, including substantially an electrical or electroless plating process, a metal foil laminating process, a thick film printing process, and a patterning and etching process. | 03-14-2013 |
Shiu-Feng Liu, Hsinchu City TW
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20090092772 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - An extreme low resistivity light attenuation anti-reflection coating structure with a surface protective layer includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of silicon carbide compound coating layers and a plurality of metal coating layers that are alternately stacked with each other. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
20090092808 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - An extreme low resistivity light attenuation anti-reflection coating with a transparent surface conductive layer includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of mixture coating layers and a plurality of metal coating layers that are alternately stacked with each other. Each mixture coating layer is composed of Ti-based oxide and carbon. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
20090092825 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - A extreme low resistivity light attenuation anti-reflection coating structure includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of Ti-based oxide coating layers and a plurality of metal coating layers that are alternately stacked with each other. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
20090092850 | Extreme low resistivity light attenuation anti-reflection coating structure and method for manufacturing the same - An extreme low resistivity light attenuation anti-reflection coating with a transparent surface conductive layer includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of mixture coating layers and a plurality of metal coating layers that are alternately stacked with each other. Each mixture coating layer is composed of silicon carbide compound and Ti-based oxide. The composed protection coating layer is formed on the coating module. | 04-09-2009 |
Shou-En Liu, Hsinchu City TW
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20110073749 | Photosensor Circuit - A photosensor circuit including a first node, a level shifting circuit, a phototransistor and an inverter is provided. The first node has an operation voltage signal. The level shifting circuit is coupled to the first node for biasing the first node, so that the operation voltage signal is biased to an operation biasing level. The phototransistor is coupled to the first node for receiving an optical signal and accordingly generates a first electrical signal by means of controlling the level of the operation voltage signal. The inverter receives the first electrical signal and accordingly generates and outputs a second electrical signal, which indicates the intensity of the optical signal. | 03-31-2011 |
Su-Cheng Liu, Hsinchu City TW
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20110285673 | WRITING DEVICE FOR ELECTRONIC PAPER AND WRITING METHOD THEREOF - A writing method for E-paper includes the following steps. A writing device for E-paper is provided, which includes a first writing electrode and a second writing electrode facing to the first writing electrode. A writing space is defined between the first writing electrode and the second writing electrode. Next, an E-paper is disposed into the writing space. Next, a voltage is applied on the first writing electrode and/or the second writing electrode to generate an electric field in the writing space. Next, the first writing electrode and the second writing electrode are driven to move with respective to the E-paper so that the E-paper is written by the electric field in the writing space. The E-paper can be written without a writing circuit configured therein by the writing method, thereby the production cost of the E-paper can be reduced and the E-paper is facilitated to carry. Furthermore, A writing device for E-paper is also provided. | 11-24-2011 |
20110316762 | ELECTRONIC SYSTEM, METHOD FOR CONTROLING MOBILE APPARATUS, READING APPARATUS AND METHOD FOR CONTORLING THEREOF - An electronic system comprises a mobile apparatus and a reading apparatus. The reading apparatus has a display screen and a plurality of operation units. When the reading apparatus is linked with the mobile apparatus through a data-transmission interface, the reading apparatus displays an image of an electronic file on the display screen thereof which is stored in the mobile apparatus. When one of the operation units is enabled, the reading apparatus generates a corresponding operation signal to the mobile apparatus, thus the mobile apparatus performs a corresponding operation process according to the operation signal. | 12-29-2011 |
20120042243 | ELECTRONIC SYSTEM AND CONTROLLING METHOD THEREOF - An electronic system comprises an electronic processing device and a reading device having a display screen. When the electronic processing device is connected to the reading device through a data-transmitting interface, the electronic processing device transmits an electronic file in the electronic processing device to the reading device by a predetermined mode, such that the reading device displays images of the electronic file on the display screen according to a predetermined specification. | 02-16-2012 |
20120182327 | DRIVING METHOD OF DISPLAY PANEL AND ELECTROPHORESIS DISPLAY APPARATUS USING THE SAME METHOD - A driving method of a display panel includes the following steps: driving the display panel to display a first image frame and providing display data of a second image frame, and each of the first and the second image frames has a first area and a second area for respectively displaying two different display contents, the positions of the two corresponding first areas overlap, and the positions of the two corresponding second areas overlap; determining whether display content differences exist between the two corresponding first areas, and determining whether display content differences exist between the two corresponding second areas, and driving the area where display content differences exist in the two areas of the first image frame to display a first-color display content when display content differences exist between the two corresponding first areas or the two corresponding second areas. Furthermore, a corresponding electrophoresis display apparatus is also provided. | 07-19-2012 |
Sung-Kao Liu, Hsinchu City TW
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20100091230 | LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A liquid crystal display (LCD) panel and a manufacturing method thereof are provided. The manufacturing method includes providing a panel including a first substrate having scan lines, data lines, an active device electrically connecting the scan and data lines, and a pixel electrode electrically connecting the active device, a second substrate having an opposite electrode, and a liquid crystal (LC) layer disposed between the first and the second substrates and having a monomer material. A first curing voltage and a second curing voltage are applied to the scan and data lines, respectively. The second curing voltage is thus transmitted to the pixel electrode. The first curing voltage is higher than an absolute value of the second curing voltage. The monomer material is polymerized to form a first polymer stabilized alignment (PSA) layer between the LC layer and the first substrate and a second PSA layer between the LC layer and the second substrate. The electrical field is then removed. | 04-15-2010 |
20130010220 | LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURING METHOD THEREOF - A liquid crystal display panel including a first substrate, a second substrate, a liquid crystal layer, a scan line, a data line intersects the scan line, an active device, a pixel electrode, an insulating layer covering the pixel electrode, an auxiliary electrode, a shielding electrode, and a first polymer stabilized alignment (PSA) layer is provided. | 01-10-2013 |
Ta-Ming Liu, Hsinchu City TW
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20100295583 | Apparatus for awaking an electronic device from a standby mode - An apparatus is used to awake an electronic device to an active mode from a standby mode in case of change in the voltage of a power supply of the electronic device. The apparatus includes a power supply for supplying electricity, a switch connected to the power supply, a low-voltage reset unit connected to the switch, a micro-controller unit connected to the switch and a monitoring and awaking unit. The monitoring and awaking unit includes an actuator connected to the switch, a bias generator connected to the actuator and a comparator connected to the bias generator. The control over the power supply by the switch causes change in the voltage of the actuator which cooperates with the bias generator and the comparator to generate an awaking signal to awake the micro-processing unit. | 11-25-2010 |
Te-Chiang Liu, Hsinchu City TW
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20110018049 | Charge trapping device and method for manufacturing the same - The present invention relates to a charge trapping device and a method for manufacturing the same. The charge trapping device includes: a substrate having a first surface and an opposite second surface; a tunneling insulating layer, disposed on the first surface of the substrate; a charge trapping layer, disposed on the tunneling insulating layer and including a first dielectric layer and a second dielectric layer, in which the first dielectric layer is connected to the tunneling insulating layer, the second dielectric layer is disposed over the first dielectric layer, and a conduction band offset between the first dielectric layer and the substrate is larger than that between the second dielectric layer and the substrate; and a blocking insulating layer, disposed on the charge trapping layer and connected to the second dielectric layer. Accordingly, the charge trapping device of the present invention has excellent programming, and erasing and charge retention properties. | 01-27-2011 |
Tien-Yueh Liu, Hsinchu City TW
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20090236637 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer. | 09-24-2009 |
20100023910 | METHOD OF PACKING-BASED MACRO PLACEMENT AND SEMICONDUCTOR CHIP USING THE SAME - A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format. | 01-28-2010 |
20110001168 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer. | 01-06-2011 |
20120038055 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first Insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer. | 02-16-2012 |
20120043663 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer. | 02-23-2012 |
Tseng-Yi Liu, Hsinchu City TW
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20100172191 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 07-08-2010 |
20110058430 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 03-10-2011 |
20120063232 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 03-15-2012 |
20120063236 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 03-15-2012 |
20120155181 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 06-21-2012 |
20120163087 | Decoder for Nand Memory - An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages. | 06-28-2012 |
20120198298 | On-the-Fly Repair Method for Memory - An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address of a failed block to be repaired, an enable bit and at least one error correction bit into both first and second redundancy information regions in a redundancy information set of the memory; checking whether error in the first and the second redundancy information regions is recoverable based on the error correction bit; and if the error is recoverable, then programming the redundancy information set as effective to replace the failed block by the redundancy block related to the effective redundancy information set. | 08-02-2012 |
20140098616 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 04-10-2014 |
Tsu-Chun Liu, Hsinchu City TW
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20100026410 | TRANSCEIVER DEVICE AND IMPEDANCE MATCHING METHOD - A transceiver device and an impedance matching method are provided. In the impedance matching method, a plurality of matching modes is set. Each matching mode includes a default impedance and a corresponding default power. In addition, one of the matching modes is selected for outputting a transmission signal to a load. Besides, a response signal derived from the transmission signal is received. Further, whether the default impedance is matched with an impedance of the load or not is determined according to a parameter of the response signal. Thereby, the echo signal can be restrained from being generated. | 02-04-2010 |
20100029346 | TRANSCEIVER DEVICE AND POWER SAVING METHOD THEREOF - A transceiver device and a power saving method thereof are provided. The transceiver device includes a transmitter, a receiver, and a control module. The control module is coupled to the transmitter and the receiver. After the control module lowers the output power of either the transmitter, the receiver, or both of them, the control module checks a signal transmission between the transceiver device and a far-end device is normal or not. When the signal transmission between the transceiver device and the far-end device is abnormal, the control module readjusts the output power of the transmitter, the receiver, or both of them. Thereby, the power consumption of the transceiver device is decreased. | 02-04-2010 |
Tzeng-Feng Liu, Hsinchu City TW
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20080226490 | Low-density alloy and fabrication method thereof - A low-density alloy and the fabrication method thereof are disclosed. The alloy comprises, in weight percent, equal to or greater than 15 wt. % but lower than or equal to 22.5 wt. % manganese, equal to or greater than 7.2 wt. % but lower than or equal to 9.0 wt. % aluminum, equal to or greater than 5.1 wt. % but lower than or equal to 7.8 wt. % chromium, equal to or greater than 0.6 wt. % but lower than or equal to 1.2 wt. % carbon and the balance of iron. The golf-club head made from the abovementioned alloy can obtain superior elongation, strength, damping capacity, and corrosion resistance even without any hot/cold working process, such as forging, rolling, etc.; therefore, the fabrication cost thereof can be obviously reduced. | 09-18-2008 |
20130081740 | Composition design and processing methods of high strength, high ductility, and high corrosion resistance FeMnAlC alloys - A novel FeMnAlC alloy, comprising 23˜34 wt. % Mn, 6˜12 wt. % Al, and 1.4˜2.2 wt. % C with the balance being Fe, is disclosed. The as-quenched alloy contains an extremely high density of nano-sized (Fe,Mn) | 04-04-2013 |
Wan-Yi Liu, Hsinchu City TW
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20100315580 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, DISPLAY PANEL, LIQUID CRYSTAL DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display panel having a pixel region and a sensing region includes a first substrate, a second substrate and a display medium layer. A plurality of pixel structures and at least one photo-voltaic cell device are disposed on the first substrate. The pixel structures are arranged in the pixel region in array, and each of the pixel structures includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The photo-voltaic cell device disposed in the sensing region includes a doped semiconductor layer, a transparent electrode layer, a first type doped silicon-rich dielectric layer and a second type doped silicon-rich dielectric layer. The first type doped silicon-rich dielectric layer and the second type doped silicon-rich dielectric layer are disposed between the doped semiconductor layer and the transparent electrode layer. The display medium layer is disposed between the first substrate and the second substrate. | 12-16-2010 |
20110156043 | THIN FILM TRANSISTOR - A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm | 06-30-2011 |
20140034951 | THIN FILM TRANSISTOR - A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a gate insulating layer, a silicon-rich channel layer, a source, and a drain. The gate is disposed on the substrate. The gate insulator is disposed over the gate. The silicon-rich channel layer is disposed above the gate, wherein the material of the silicon-rich channel layer is selected from a group consisting of silicon-rich silicon oxide (Si-rich SiOx), silicon-rich silicon nitride (Si-rich SiNx), silicon-rich silicon oxynitride (Si-rich SiOxNy), silicon-rich silicon carbide (Si-rich SiC) and silicon-rich silicon oxycarbide (Si-rich SiOC). The content (concentration) of silicon of the silicon-rich channel layer within a film depth between 10 nm to 170 nm ranges from about 1E23 atoms/cm | 02-06-2014 |
Wei- Kong Liu, Hsinchu City TW
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20110013339 | ASSEMBLY OF MAGNETIC CAPACITOR WITH PACKAGING - An assembly of an magnetic capacitor with a packaging comprises: a magnetic capacitor; two packing electrodes, one of the two end electrodes including an upper magnetic casing installed upon a top surface of the capacitor and a lower magnetic casing installed at a lower surface of the capacitor; each of the upper magnetic casing and the lower magnetic casing being formed with extruding pieces which is arranged around a lateral side of the capacitor; and at least one insulation material for isolating magnetic material is arranged within the magnetic capacitor. | 01-20-2011 |
Wen-Shin Liu, Hsinchu City TW
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20090257112 | METHOD AND APPARATUS FOR MANUFACTURING ELECTROPHORETIC DISPLAY - In an apparatus for manufacturing an electrophoretic display, the electrophoretic display includes a backside plate having a cover area and a display structure. The display structure is arranged on the backside plate and a rear surface thereof facing toward the backside plate has an area less than the cover area. The apparatus includes a main body and a pressure-supplying member. The main body includes a receiving cavity, a supporting surface and a plurality of absorption holes. The receiving cavity is configured to receive the display structure therein. The supporting surface is located at the bottom of the receiving cavity. The absorption holes are arranged at the bottom of the receiving cavity and each penetrates through the supporting surface. The absorption holes are configured to vacuum absorb the display structure on the supporting surface via vacuum absorption means. The pressure-supplying member is configured to apply a pressure onto the backside plate so as to stack the backside plate on the rear surface of the display structure. The present invention also provides a method for manufacturing an electrophoretic display. | 10-15-2009 |
Yang-Kuang Liu, Hsinchu City TW
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20090162231 | SCROLL COMPRESSOR - A scroll compressor including a block, a fixed scroll, an orbiting scroll, a crankshaft, an Oldham ring and an oil passage is provided, wherein the fixed scroll is fixed on the block, and the orbiting scroll, the crankshaft and the Oldham ring are disposed on the block. The fixed scroll and the orbiting scroll form a gas-in area, a compressing area and a gas-out area which are connected in a series. The orbiting scroll is eccentric connected with the crankshaft to orbit over the fixed scroll and drive the Oldham ring moving. A reciprocating motion area on the block is formed via the reciprocating motion between the block and the Oldham ring, wherein the block has an oil opening in the reciprocating motion area. Besides, one terminal of the oil passage is connected to the oil opening, and another terminal of the oil passage is connected to the gas-in area and the compressing area. | 06-25-2009 |
Yion Ni Liu, Hsinchu City TW
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20100163091 | Composite material of complex alloy and generation method thereof, thermoelectric device and thermoelectric module - A composite material of complex alloy is provided and it is the Ceramic-Metal Composite based on a thermoelectric material filled with ceramic material. The composite material is represented by the following general formula (I). | 07-01-2010 |
20110062389 | CONDUCTIVE MATERIAL FORMED USING LIGHT OR THERMAL ENERGY, METHOD FOR FORMING THE SAME AND NANO-SCALE COMPOSITION - An electrically conductive material includes a plurality of nanowires and a plurality of nanoconnectors. The ratio by weight of the plurality of nanowires to the plurality of nanoconnectors is in a range of from 1:9 to 9:1. Nanoconnectors can be heated by thermal energy or light energy so that the nanoconnectors can be closely interconnected to each other and to nanowires, resulting in significant increase of the electrical conductivity of the electrically conductive material. | 03-17-2011 |
20130087251 | THERMOELECTRIC ALLOY MATERIAL AND THERMOELECTRIC ELEMENT - A thermoelectric alloy material and thermoelectric element are provided, wherein the thermoelectric alloy material includes a Half-Heusler (HH) composition as matrix. The thermoelectric alloy material is represented by following formula (I): | 04-11-2013 |
Yong Yu Liu, Hsinchu City TW
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20100118297 | MICROSCOPE HAVING MULTIPLE IMAGE-OUTPUTTING DEVICES AND PROBING APPARATUS FOR INTEGRATED CIRCUIT DEVICES USING THE SAME - A microscope includes an object splitter configured to split the object image into a first optical path and a second optical path, a first imaging module positioned on the first path and a second imaging module positioned on the second path. The object splitter includes a first beam splitter configured to direct an illumination light to an object, an objective lens configured to collect the reflected light from the object and couple the reflected light on the first beam splitter, and a second beam splitter configured to split the reflected light into the first optical path and the second optical path, wherein the distance between the object and the objective lens is constant. The first imaging module includes a first close up lens configured to render a first object image to a first imaging device with auto-focusing and remote-zooming capabilities, and the second imaging module includes a second close up lens and a negative lens configured to render a second object image to a second imaging device with auto-focusing and remote-zooming capabilities. | 05-13-2010 |
20110304857 | Probing Apparatus with On-Probe Device-Mapping Function - One aspect of the present disclosure provides a probing apparatus with on-probe device-mapping function. A probing apparatus according to this aspect of the present disclosure comprises a housing, at least one probe stage positioned on the housing and configured to retain at least one probe, a device holder positioned in the housing and configured to receive at least one semiconductor device under test, and an inspection module having a predetermined field of view configured to capture an image showing at least the semiconductor device, wherein the probe stage includes a driving unit configured to move the probe out of focus of the inspection module in a mapping phase while keeping the device under test in the field of view of the optical inspection module. | 12-15-2011 |
Yueh-Hsiu Liu, Hsinchu City TW
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20090096775 | Differential signal interfacing device and related method - The present invention provides a differential signal interfacing device, including a reduced swing differential signaling (RSDS) transmitter and a plurality of RSDS receivers, in order to improve RSDS signal capacity. The RSDS transmitter is coupled to the plurality of RSDS receivers via a bus and transmits a RSDS signal in a discontinuous manner. The plurality of RSDS receivers receives the RSDS signal for signals of different types. | 04-16-2009 |
20090110138 | Shift Register Circuit - A shift register circuit includes a plurality of bit register units, coupled in series, for transferring an input signal among the plurality of bit register units to sequentially output the input signal to a plurality of data output terminals according to a control signal and a clock signal, wherein the number of the plurality of data output terminals is greater than that of the plurality of bit register units, and a control unit for generating the control signal to control transference of the input signal. | 04-30-2009 |
20090309860 | Driving Method and Related Device for Reducing Power Consumption of LCD - A driving method is provided for reducing power consumption of a liquid crystal display. The driving method includes steps of sequentially receiving first data and second data, determining whether the second data is the same as the first data, and controlling a data-line driving circuit not to read in driving data corresponding to the second data when the second data is the same as the first data. | 12-17-2009 |
20100045657 | Driving Device for Liquid Crystal Display - A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register. | 02-25-2010 |
20120056857 | Display apparatus and display method thereof - A display apparatus and a display method thereof are provided. The display apparatus comprises a panel, an unusual status detecting unit, a status recognizing unit, a scan driver and a data driver. The unusual status detecting unit detects an unusual status to output a status feedback signal. The status recognizing unit transforms a first output enabling signal into a second output enabling signal according to the status feedback signal. The scan driver outputs a plurality of scan signals to drive the panel according to the clock signal and the second output enabling signal. The second output enabling signal masks at least one of the scan signals. The data driver outputs the data signals to the panel. | 03-08-2012 |
20120194575 | GAMMA-VOLTAGE GENERATOR - A gamma-voltage generator is provided to generating a plurality of first gamma voltages and second gamma voltages. At least one of the first gamma voltages generated by DACs of the gamma-voltage generator within a first frame period and at least one of the second gamma voltages generated by the DACs within a second frame period are outputted from a same one of the gamma buffers of the gamma-voltage generator, whereby the transmitted gamma voltages have substantially equal offset. Therefore, the display quality approaches an ideal condition. | 08-02-2012 |
20120242644 | FRAME MAINTAINING CIRCUIT AND FRAME MAINTAINING METHOD - A frame maintaining circuit including a detection circuit and a display control circuit is provided. The detection circuit detects an unusual status to output a status feedback signal. The display control circuit maintains a frame displayed by a display apparatus according to the status feedback signal until the unusual status ceases. | 09-27-2012 |
20130342109 | DRIVING CIRCUIT OF FLAT DISPLAY - A driving circuit of flat display including a charging circuit path, a discharging circuit path, and a detecting circuit is provided. The charging circuit path has first and second impedance states, wherein an impedance value of the first impedance state is smaller than that of the second impedance state. The discharging circuit path has third and fourth impedance states, wherein an impedance value of the third impedance state is smaller than that of the fourth impedance state. The detecting circuit detects whether the charging circuit path or the discharging circuit path is in an unstable first state or stable second state, controls the charging circuit path to the first impedance state or the discharging circuit path to the third impedance state in the first state, and controls the charging circuit path to the second impedance state or the discharging circuit path to the fourth impedance state in the second state. | 12-26-2013 |
20140002437 | POWER-SAVING DRIVING CIRCUIT AND POWER-SAVING DRIVING METHOD FOR FLAT PANEL DISPLAY | 01-02-2014 |
20140022233 | Driving Device for Liquid Crystal Display - A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register. | 01-23-2014 |
20140043313 | GAMMA-VOLTAGE GENERATOR - A gamma-voltage generator is provided to generating a plurality of first gamma voltages and second gamma voltages. At least one of the first gamma voltages generated by DACs of the gamma-voltage generator within a first frame period and at least one of the second gamma voltages generated by the DACs within a second frame period are outputted from a same one of the gamma buffers of the gamma-voltage generator, whereby the transmitted gamma voltages have substantially equal offset. Therefore, the display quality approaches an ideal condition. | 02-13-2014 |
Yuh-Turng Liu, Hsinchu City TW
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20090224336 | SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality of metal line patterns. The polysilicon layer disposed between the substrate and the metal layer includes a gate pattern and at least one guard ring pattern. The at least one guard ring pattern connects to the gate pattern and surrounds at least one of the metal line patterns. One of the metal line patterns connects to the gate pattern. The others of the metal line patterns connect to one of the doped regions in the substrate. | 09-10-2009 |
20140197508 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor comprises a substrate, a plurality of image sensing elements and a first inorganic optical layer, wherein the substrate has an active region; the image sensing elements are disposed in the active region; and the first inorganic optical layer covers the image sensing elements and has at least two adjacent edges for forming an angle greater than 90 degrees (90°). | 07-17-2014 |
Yu-Lien Liu, Hsinchu City TW
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20100109043 | METHODS AND STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 05-06-2010 |
20100109076 | STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A first doped region of the first conductivity type and a second doped region of the second conductivity type are located in the second well region. A first transistor includes the first doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event. | 05-06-2010 |
20110216454 | ELECTROSTATIC DISCHARGE PROTECTORS HAVING INCREASED RC DELAYS - An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area. | 09-08-2011 |
20120286322 | METHODS AND STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region. | 11-15-2012 |
Yun-I Liu, Hsinchu City TW
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20080242798 | Anti-leaking cartridge and anti-leaking ink - The present invention is generally related to an anti-leaking cartridge and anti-leaking ink. The anti-leaking ink comprises: an organic solvent, which is selected from the group consisting of diethylene glycol, triethylene glycol, triethanolamine amine extra pure, polyethylene glycol 200, and ethylene glycol and functions with at least one seal member for avoiding leakage; at least one dye dissolved in the organic solvent; a buffer solution maintaining the pH value of the anti-leaking ink in between 6.0 to 8.0; an antibacterial avoiding that the properties of the ink is changed; surfactant, which homogenizes the aquas of ink and the organic solvent; and de-ionized water. | 10-02-2008 |