Patent application number | Description | Published |
20100038751 | STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE - A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node. | 02-18-2010 |
20120086103 | TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE - A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench. | 04-12-2012 |
20120228736 | TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE - A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench. | 09-13-2012 |
20130249052 | CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE - A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications. | 09-26-2013 |
20130256830 | SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING - Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. | 10-03-2013 |
20130285193 | METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI) - A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor. | 10-31-2013 |
20130320422 | FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM - A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin. | 12-05-2013 |
20140021523 | DRAM WITH DUAL LEVEL WORD LINES - A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels. | 01-23-2014 |
20140021585 | CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE - A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications. | 01-23-2014 |
20140035038 | Structure And Method To Realize Conformal Doping In Deep Trench Applications - The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping. | 02-06-2014 |
20140038382 | Structure And Method To Realize Conformal Doping In Deep Trench Applications - The specification and drawings present a new method, ASIC and computer/software related product (e.g., a computer readable memory) are presented for realizing conformal doping in embedded deep trench applications in the ASIC. A common SOI substrate with intrinsic or low dopant concentration is used for manufacturing such ASICs comprising a logic area having MOSFETs utilizing, for example, ultra thin body and box technology and an eDRAM area having deep trench capacitors with the conformal doping. | 02-06-2014 |
20140065777 | DRAM WITH DUAL LEVEL WORD LINES - A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels. | 03-06-2014 |
20140084411 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEEP TRENCH CAPACITOR - Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening. | 03-27-2014 |
20140151772 | UNIFORM FINFET GATE HEIGHT - A method including providing fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the fins and the nitride layer, removing a portion of the fins to form an opening, forming a dielectric spacer on a sidewall of the opening, and filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer. The method may further include forming a deep trench capacitor in-line with one of the fins, removing the nitride layer to form a gap between the fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the fins and the fill material to widen. | 06-05-2014 |
20140191359 | SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING - Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. | 07-10-2014 |
20140264522 | SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE - An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. | 09-18-2014 |
20140299882 | INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR - At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure. | 10-09-2014 |
20150021610 | SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE - An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. | 01-22-2015 |
20150021737 | METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI) - A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor. | 01-22-2015 |
20150037941 | FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM - A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin. | 02-05-2015 |
20150135156 | SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE - An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. | 05-14-2015 |
20150206885 | DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM - Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions. | 07-23-2015 |
20150348977 | VERTICALLY INTEGRATED MEMORY CELL - A vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor. | 12-03-2015 |
20160027789 | DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM - Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions. | 01-28-2016 |
20160099249 | INTEGRATED FIN AND STRAP STRUCTURE FOR AN ACCESS TRANSISTOR OF A TRENCH CAPACITOR - At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure. | 04-07-2016 |
Patent application number | Description | Published |
20100177950 | Systems and methods for treating, diagnosing and predicting the occurrence of a medical condition - Clinical information, molecular information and/or computer-generated morphometric information is used in a predictive model for predicting the occurrence of a medical condition. In an embodiment, a model predicts risk of prostate cancer progression in a patient, where the model is based on features including one or more (e.g., all) of preoperative PSA, dominant Gleason Grade, Gleason Score, at least one of a measurement of expression of AR in epithelial and stromal nuclei and a measurement of expression of Ki67-positive epithelial nuclei, a morphometric measurement of average edge length in the minimum spanning tree (MST) of epithelial nuclei, and a morphometric measurement of area of non-lumen associated epithelial cells relative to total tumor area. In some embodiments, the morphometric information is based on image analysis of tissue subject to multiplex immunofluorescence and may include characteristic(s) of a minimum spanning tree (MST) and/or a fractal dimension observed in the images. | 07-15-2010 |
20100184093 | Systems and methods for treating, diagnosing and predicting the occurrence of a medical condition - Clinical information, molecular information and/or computer-generated morphometric information is used in a predictive model for predicting the occurrence of a medical condition. In an embodiment, a model predicts whether a patient is likely to have a favorable pathological stage of prostate cancer, where the model is based on features including one or more (e.g., all) of preoperative PSA, Gleason Score, a measurement of expression of androgen receptor (AR) in epithelial and stromal nuclei and/or a measurement of expression of Ki67-positive epithelial nuclei, a morphometric measurement of a ratio of area of epithelial nuclei outside gland units to area of epithelial nuclei within gland units, and a morphometric measurement of area of epithelial nuclei distributed away from gland units. In some embodiments, quantitative measurements of protein expression in cell lines are utilized to objectively assess assay (e.g., multiplex immunofluorescence (IF)) performance and/or to normalize features for use within a predictive model. | 07-22-2010 |
20110040544 | Systems And Methods For Treating, Diagnosing And Predicting The Response To Therapy Of Breast Cancer - This present invention systems and methods of accessing/monitoring the responsiveness of a breast cancer to a therapeutic compound. | 02-17-2011 |
20130080134 | SYSTEMS AND METHODS FOR PREDICTING FAVORABLE-RISK DISEASE FOR PATIENTS ENROLLED IN ACTIVE SURVEILLANCE - In general, one aspect of the subject matter described in this specification can be embodied in methods for assessing risk associated with prostate cancer, the methods including the actions of receiving patient data, comparing, with a processor executing code, the patient data to one or more predictive models, the one or more predictive models comprising at least one of (a) a disease progression (DP) model, the DP model being configured to predicts a likelihood of developing significant disease progression, and (b) a favorable pathology (FP) model, the FP model being configured to predict a likelihood of having organ confined, low grade disease in a prostatectomy, and outputting one or more results of the comparison Other embodiments of the various aspects include corresponding systems, apparatus, and computer program products. | 03-28-2013 |
20130230230 | SYSTEMS AND METHODS FOR SEGMENTATION AND PROCESSING OF TISSUE IMAGES AND FEATURE EXTRACTION FROM SAME FOR TREATING, DIAGNOSING, OR PREDICTING MEDICAL CONDITIONS - Apparatus, methods, and computer-readable media are provided for segmentation, processing (e.g., preprocessing and/or postprocessing), and/or feature extraction from tissue images such as, for example, images of nuclei and/or cytoplasm. Tissue images processed by various embodiments described herein may be generated by Hematoxylin and Eosin (H&E) staining, immunofluorescence (IF) detection, immunohistochemistry (IHC), similar and/or related staining processes, and/or other processes. Predictive features described herein may be provided for use in, for example, one or more predictive models for treating, diagnosing, and/or predicting the occurrence (e.g., recurrence) of one or more medical conditions such as, for example, cancer or other types of disease. | 09-05-2013 |
Patent application number | Description | Published |
20100154866 | HYBRID SOLAR POWER SYSTEM - A hybrid solar power system incorporates both solar thermal technology and photovoltaic technology in producing power. The hybrid solar power system includes a cover, thermal layers, and photovoltaic layers disposed within an enclosure. The hybrid solar power system is arranged to produce power thermally via the thermal layers and directly via the photovoltaic layers. In producing the power, the thermal layers and the photovoltaic layers first harness sunlight incident on the hybrid solar power system. Subsequently, the inner surfaces of the enclosure include reflective surfaces, reflecting the incident sunlight back through the thermal layers and the photovoltaic layers so that additional power can be generated from the reflected light. | 06-24-2010 |
20100270203 | COMBINATION BANDAGE AND WOUND TREATMENT SYSTEM - A wound treatment system including a housing having a first compartment and a second compartment, a bandage disposed within the first compartment, and a swab disposed within the second compartment. Further, the first compartment is openable independent of the second compartment, and the second compartment is openable independent of the first compartment. | 10-28-2010 |
20100274104 | INFANT/CHILD MONITOR - A monitoring device including a plurality of sensors, each sensor configured to measure one of a plurality of vital sign parameters and a plurality of environmental parameters. The monitoring device further including a memory configured to store at least a programmable upper limit and a programmable lower limit for each of the measured parameters, a central processing unit configured to process the measured parameters and compare each measured parameter against its respective programmable upper limit and programmable lower limit, and at least one communications module configured to transmit and receive data. Further, the monitoring device being configured to automatically transmit an alert when one measured parameter is outside a range defined by its respective programmable upper limit and programmable lower limit. Optionally, the device includes various communications interfaces, including cellular, Internet, conventional telephone. Other optional features include an emergency dialer, positioning technology such as GPS, a microphone, and a speaker. | 10-28-2010 |
20150308059 | Directional Shovel - The present invention relates to a hand or motorized push shovel/plow with directional left or right side disbursement of snow, granular material, thicker liquids and other such desired materials with ease and comfort. The shovel allows a user to direct a shoveled load to a first or a second side of the shovel while moving the shovel in a substantially straight direction and generally comprises a handle, a shaft extending from the handle to a base shovel blade, and a steering mechanism secured along a portion of the shaft or handle and in steering communication with a directional shovel blade that is in a relational arrangement on top of the base shovel blade. The steering mechanism allows a user to angle the directional blade in a left or right direction. | 10-29-2015 |