Novichkov
Roman Vladimirovich Novichkov, Dubna RU
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20110269297 | METHOD FOR SYNTHESISING SEMICONDUCTOR QUANTUM DOTS - The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier , core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanoclystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes. The invention makes it possible to increase the photostability of semiconductor quantum dots up to 34% and the capacity thereof to be dispersed in both non-polar and polar solvents, so that the quantum yields are preserved and increased. | 11-03-2011 |
Vladimir Novichkov, Glenview, IL US
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20100153812 | METHODS AND APPARATUS FOR ENCODING LDPC CODES - Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph. | 06-17-2010 |
Vladimir Novichkov, Towaco, NJ US
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20090063925 | LCPC DECODING METHODS AND APPARATUS - A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused. | 03-05-2009 |
20090177869 | EFFICIENT CHECK NODE MESSAGE TRANSFORM APPROXIMATION FOR LDPC DECODER - In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log/exp instructions and especially on a SIMD FPU-equipped processors where log/exp functions are typically scalar. | 07-09-2009 |
Vladimir Novichkov, Martinsville, NJ US
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20090063933 | LCPC DECODING METHODS AND APPARATUS - A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused. | 03-05-2009 |