Electrical Isolation Of High Defect Density Regions In A Semiconductor DeviceAANM Kizilyalli; Isik C.AACI San FranciscoAAST CAAACO USAAGP Kizilyalli; Isik C. San Francisco CA USAANM Bour; David P.AACI CupertinoAAST CAAACO USAAGP Bour; David P. Cupertino CA USAANM Brown; Richard J.AACI Los GatosAAST CAAACO USAAGP Brown; Richard J. Los Gatos CA USAANM Edwards; Andrew P.AACI San JoseAAST CAAACO USAAGP Edwards; Andrew P. San Jose CA USAANM Nie; HuiAACI CupertinoAAST CAAACO USAAGP Nie; Hui Cupertino CA USAANM Romano; Linda T.AACI SunnyvaleAAST CAAACO USAAGP Romano; Linda T. Sunnyvale CA US - diagram, schematic, and image 02
Back to Electrical Isolation Of High Defect Density Regions In A Semiconductor DeviceAANM Kizilyalli; Isik C.AACI San FranciscoAAST CAAACO USAAGP Kizilyalli; Isik C. San Francisco CA USAANM Bour; David P.AACI CupertinoAAST CAAACO USAAGP Bour; David P. Cupertino CA USAANM Brown; Richard J.AACI Los GatosAAST CAAACO USAAGP Brown; Richard J. Los Gatos CA USAANM Edwards; Andrew P.AACI San JoseAAST CAAACO USAAGP Edwards; Andrew P. San Jose CA USAANM Nie; HuiAACI CupertinoAAST CAAACO USAAGP Nie; Hui Cupertino CA USAANM Romano; Linda T.AACI SunnyvaleAAST CAAACO USAAGP Romano; Linda T. Sunnyvale CA US , All Patents .