Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors - diagram, schematic, and image 05
Back to Layout of Cell of Semiconductor Device Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors , All Patents .