| 53rd week of 2009 patent applcation highlights part 75 |
| Patent application number | Title | Published |
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| 20090327570 | Bidirectional control circuit - A bidirectional bus control circuit to which first and second direction signals instructing bus directions are input and which inputs and outputs a clock signal and data signal includes a first bidirectional buffer that switches an input or output direction of the clock signal in accordance with the second direction signal, a second bidirectional buffer that switches an input or output direction of the data signal in accordance with the second direction signal, and a data confirmation unit that confirms a data signal input to the second bidirectional buffer and invalidates the confirmation of the data signal in accordance with switching of the signal direction instructed by the first direction signal from the input direction to the output direction, the switching of the signal direction instructed by the first direction signal occurring before the switching of the signal direction instructed by the second direction. | 2009-12-31 |
| 20090327571 | COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS - A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank | 2009-12-31 |
| 20090327572 | EXCHANGING INFORMATION BETWEEN COMPONENTS COUPLED WITH AN A I2C BUS VIA SEPARATE BANKS - A method and apparatus for exchanging information between components coupled with an a I | 2009-12-31 |
| 20090327573 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, including a memory banks and associated local data buses, and a bus connection circuit connected to the local data buses associated with two or more of the memory banks to perform a selective data transfer between a global data bus and those local data buses. | 2009-12-31 |
| 20090327574 | REPLAY TIME ONLY FUNCTIONALITIES - Replay-time-only functionalities in a computer program are executed only during replay in a virtual machine and are skipped outside of replay. If a replay-time-only functionality is detected during the replay of a program execution in a virtual machine, the replay may be paused and the virtual machine state may be saved. The replay-time-only core functionality is executed. When this execution is complete, a prior state of the virtual machine may be restored and the replay may be resumed. | 2009-12-31 |
| 20090327575 | COPY EQUIVALENT PROTECTION USING SECURE PAGE FLIPPING FOR SOFTWARE COMPONENTS WITHIN AN EXECUTION ENVIRONMENT - Embodiments of copy equivalent protection using secure page flipping for software components within an execution environment are generally described herein. An embodiment includes the ability for a Virtual Machine Monitor (VMM), Operating System Monitor, or other underlying platform capability to restrict memory regions for access only by specifically authenticated, authorized and verified software components, even when part of an otherwise compromised operating system environment. In an embodiment, an embedded VM is allowed to directly manipulate page table mappings so that, even without running the VMM or obtaining VMXRoot privilege, the embedded VM can directly flip pages of memory into its direct/exclusive control and back. Other embodiments may be described and claimed. | 2009-12-31 |
| 20090327576 | Direct Memory Access Filter for Virtualized Operating Systems - Described techniques increase runtime performance of workloads executing on a hypervisor by executing virtualization-aware code in an otherwise non virtualization-aware guest operating system. In one implementation, the virtualization-aware code allows workloads direct access to physical hardware devices, while allowing the system memory allocated to the workloads to be overcommitted. In one implementation, a DMA filter driver is inserted into an I/O driver stack to ensure that the target guest physical memory of a DMA transfer is resident before the transfer begins. The DMA filter driver may utilize a cache to track which pages of memory are resident. The cache may also indicate which pages of memory are in use by one or more transfers, enabling the hypervisor to avoid appropriating pages of memory during a transfer. | 2009-12-31 |
| 20090327577 | HYBRID STORAGE - Solid-state memory and mechanical disk memory can be used together to create a reliable storage unit with desirable performance characteristics. Initially, memory can be entered to the solid-state memory until filled as well as backed-up upon the mechanical disk memory. After the solid-state memory fills, less used information can be deleted from the solid-state memory yet retained upon the mechanical disk such that the less used information is not lost. To determine information use, an algorithm can be employed, such as an exponential algorithm. | 2009-12-31 |
| 20090327578 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed. | 2009-12-31 |
| 20090327579 | LIMITED MEMORY POWER - Storage devices can retain information through application of a charge upon the storage device. However, applying the charge upon the storage device can be change physical characteristics of the charge and ultimately increase a likelihood of device failure. Therefore, a determination can be made on how to apply the charge based upon analysis of the device, of data for retention, and the like. Raw data can be analyzed and/or estimations can be made to determine the charge. | 2009-12-31 |
| 20090327580 | OPTIMIZATION OF NON-VOLATILE SOLID-STATE MEMORY BY MOVING DATA BASED ON DATA GENERATION AND MEMORY WEAR - An exemplary method includes writing data to locations in non-volatile solid-state memory and deciding whether to move data written to one location in the memory to another location in the memory based on generation of the data and wear of the other location. Such a method may be used for non-volatile random access memory (NVRAM). Various other methods, devices, systems, etc., are also disclosed. | 2009-12-31 |
| 20090327581 | NAND MEMORY - Disclosed herein is a method and apparatus to refresh/rewrite the data in a NAND solid state storage device (“SSD”) only when it needs to be re-written. Upon power-up, the SSD assumes that it may have been a long time since some of its data was last written, and a background task to scan through all the data is started in the SSD. During idle periods, the entire contents of the drive is read. If a location is read and it has more than “bit error threshold” bits (for example three (3) bits if there is capability to correct eight (8) bits) in error before error correction is applied, it is assumed that this memory location is retaining the data only marginally, and the corrected data should be re-written to a new location, or alternatively re-written in the same location. The corrected data is then re-written to a new location or the same location. | 2009-12-31 |
| 20090327582 | Banded Indirection for Nonvolatile Memory Devices - Methods, apparatuses, and computer program products that enable banded indirection for nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments comprise a method for performing banded indirection when accessing data of a nonvolatile device. The methods comprise tracking fragmentation of a band of physical addresses of the nonvolatile memory device, storing a physical address of the band, and accessing data of a logical address of the band via the stored physical address based on the fragmentation of the band. Some embodiments comprise apparatuses for accessing data of nonvolatile devices using banded indirection. The embodiments comprise a nonvolatile memory element to store data, wherein the nonvolatile memory element has bands of physical addresses, a fragmentation detector to detect fragmentation of a band of the nonvolatile memory, and a data access module to access data of the band via a physical address based on the fragmentation. | 2009-12-31 |
| 20090327583 | Seek Time Emulation for Solid State Drives - Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests. | 2009-12-31 |
| 20090327584 | Apparatus and method for multi-level cache utilization - In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed. | 2009-12-31 |
| 20090327585 | DATA MANAGEMENT METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data management method a flash memory storage system and a controller using the same are provided. The data management method is used for accessing a flash memory of the flash memory storage system, wherein the flash memory includes a plurality of physical blocks and the physical blocks are grouped into a data area and a spare area. The data management method includes configuring a plurality of logical blocks for be accessed by a host. The data management method also includes dividing each physical block into a plurality of physical parts and mapping the logical blocks to the physical parts. The data management method further includes accessing the mapped physical parts according to the physical blocks to be accessed by the host. Accordingly, it is possible to increase the usage and the accessing speed of the physical blocks in the flash memory storage system. | 2009-12-31 |
| 20090327586 | MEMORY DEVICE AND DATA STORING METHOD - A memory device is provided, comprising a single-level memory unit, a multi-level memory unit and a control unit. The single-level memory unit comprises a first link table and stores data according to the first link table. The multi-level memory unit comprises a second link table and stores data according to the second link table. The control unit directs data which normally belongs to the single-level memory unit to the multi-level memory unit or directs data which normally belongs to the multi-level memory unit to the single-level memory unit according to a control signal. | 2009-12-31 |
| 20090327587 | PERSONALIZATION OF PORTABLE DATA STORAGE MEDIA - In a method for the personalization of portable data carriers ( | 2009-12-31 |
| 20090327588 | SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network. | 2009-12-31 |
| 20090327589 | TABLE JOURNALING IN FLASH STORAGE DEVICES - A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data. | 2009-12-31 |
| 20090327590 | ENHANCED MLC SOLID STATE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC-mimicking MLC flash, and relatively static data in normal MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC-mimicking MLC flash or in normal MLC flash depending on the number of writes that have occurred for that particular LBA. Dynamic allocation can occur between the two types of MLC. Related methods and software are also described. | 2009-12-31 |
| 20090327591 | SLC-MLC COMBINATION FLASH STORAGE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash. | 2009-12-31 |
| 20090327592 | CLUSTERING DEVICE FOR FLASH MEMORY AND METHOD THEREOF - Disclosed are a clustering device for a flash memory and a method thereof. The clustering device for a flash memory in accordance with an embodiment of the present invention can gather pages having similar update times and perform a write operation of the pages in a same block. Accordingly, the writing performance of the flash memory can be improved and the lifetime of the flash memory can be increased. | 2009-12-31 |
| 20090327593 | READ-ONLY MEMORY DEVICE WITH SECURING FUNCTION AND ACCESSING METHOD THEREOF - The present invention provides a memory device and a method for accessing the memory device thereof. The memory device comprises an address encoding selector for selecting one of plurality of encoding circuits which encodes a first address into a second address, and a data decoding selector for selecting one of plurality of decoding circuits which decodes a first data corresponding to the second address into a second data and a non-volatile memory, coupled to address encoding selector and the data decoding selector, for storing the first data. The method for accessing the memory device comprises encoding a first address into a second address by an address encoding selector, and decoding a first data corresponding to the second address into a second data by a data decoding selector, wherein the first data being stored in the non-volatile memory. | 2009-12-31 |
| 20090327594 | APPARATUS AND METHODS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES - Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the first data value and the second data value are written to one or more other memory cells. | 2009-12-31 |
| 20090327595 | STORAGE CAPACITY STATUS - In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display. | 2009-12-31 |
| 20090327596 | MEMORY CONTROLLER USING TIME-STAGGERED LOCKSTEP SUB-CHANNELS WITH BUFFERED MEMORY - Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations. | 2009-12-31 |
| 20090327597 | DUAL INTERFACE MEMORY ARRANGEMENT AND METHOD - The present invention provides for a dual interface memory arrangement employing the checkered memory mapping formed from combined vertically and horizontally sliced memory mapping, and including 2D access means arranged for access to the mapping memory wherein the said to the access means is arranged such that the access overlaps memory mapped to both interfaces both horizontally and vertically, and which arrangement preferably provides for two DTL channels for each interface wherein a highly efficient unified memory arrangement can be achieved for all processing aspects such as CPU, audio, video and gfx processing. | 2009-12-31 |
| 20090327598 | DISK STORAGE APPARATUS AND PROGRAM - Disclosed is a disk storage apparatus to control writing to a storage medium having a storage area to which a first address space is allocated and whose transfer rate spatially changes, including a command reception section and control section. The command reception section receives a write command from a host apparatus and containing an address of the first address space. The control section performs control to divide the storage area into zones, pre-define a second address space where blocks are successively allocated to the zones from a beginning address of the first address space, replace, for each of the write commands received by the command reception, an address of the first address space contained therein with an address of the second address space, select one of the zones as a write target zone by cyclical changing, and perform a writing process to the storage medium for each selected zone. | 2009-12-31 |
| 20090327599 | VIRTUAL TAPE DEVICE, DATA BACKUP METHOD, AND RECORDING MEDIUM - To provide a virtual tape device to reduce power consumption by utilizing a disk array device conforming to MAID. Two or more disk devices are divided into an information managing disk group whose power is kept on at all times and to two or more recording disk groups whose power is turned on/off as necessary when managing data. The virtual tape device includes: a volume information managing part which manages positions of virtual tapes allotted to storage areas of the recording disk groups; and a data managing part which rearranges, in the recording disk group whose power is on, the virtual tape for storing the data to the recording disk group whose power is off based on writing/reading information stored in the information managing disk group and positional information of the virtual tapes, and executes a control to write backup data to the recording disk group whose power is on. | 2009-12-31 |
| 20090327600 | OPTIMIZED CACHE COHERENCY IN A DUAL-CONTROLLER STORAGE ARRAY - Data is cached in a dual-controller storage array having a first cache controlled by a first controller, a second cache controlled by a second controller, and a shared array of persistent storage devices, such as disk drives. When one of the controllers receives a write request, it stores the data in persistent storage, stores a copy of that data in the first cache, and transmits identification data to the second controller that identifies the data written to persistent storage. Using the identification data, the second controller invalidates any data stored in the second cache that corresponds to the data that the first controller wrote to persistent storage. If a controller receives a read request, and the requested data is validly stored in its cache, the controller retrieves it from the cache; otherwise, the controller reads the requested data from persistent storage and caches a copy of the requested data. | 2009-12-31 |
| 20090327601 | ASYNCHRONOUS DATA MIRRORING WITH LOOK-AHEAD SYNCHRONIZATION RECORD - A data storage system is provided. The system includes a primary storage subsystem, which includes first non-volatile storage media and a secondary storage subsystem, which includes second non-volatile storage media, wherein the primary storage subsystem is arranged to receive data from a host processor for writing to a specified location, and to store the data in the specified location on the first non-volatile storage media while copying the data to the second storage subsystem, which is arranged to store the data in the specified location on the second non-volatile storage media so as to create a mirror on the secondary storage subsystem of the data received by the primary storage subsystem, and wherein the primary storage subsystem is arranged to maintain a record of locations to which data are expected to be written on the primary storage subsystem by the host processor, as indicated by a predetermined prediction algorithm based on the locations to which the data have already been written, and upon receiving the data from the host processor, to update the record using the prediction algorithm so that the record includes both the specified location and one or more further locations that have not yet been specified by the host processor if the specified location is not included in the record, and to output an acknowledgement to the host processor to indicate that the data have been stored in the data storage system after receiving the data and, after updating the record if the specified location was not included in the record prior to-updating the record. | 2009-12-31 |
| 20090327602 | METHOD AND SYSTEM FOR MANAGING WEAR-LEVEL AWARE FILE SYSTEMS - A method for wear level-based allocation in a storage pool. The method includes receiving a first request to write a first data item in a storage pool, where the storage pool includes a number of physical locations associated with the storage devices, and where each of the storage devices includes metadata regarding a level of wear of the storage device. The method further includes determining a first target physical location selected from the plurality of physical locations by using a wear-level selection policy and a wear cost for each of the storage devices, where the wear cost is determined based on a type of the storage device. The method further includes allocating a first data block to the first target physical location writing the first data block to the first target physical locations, wherein the first data block comprises a first portion of the first data item. | 2009-12-31 |
| 20090327603 | System including solid state drives paired with hard disk drives in a RAID 1 configuration and a method for providing/implementing said system - The present invention is a storage system. The storage system includes a disk array. The disk array includes a disk drive pair which includes a hard disk drive and a solid state disk drive, such as a NAND flash drive. The storage system also includes a disk array controller. The disk array controller may be communicatively coupled with a host server and with the disk array. Further, the disk array controller may be configured for reading from the disk array and writing to the disk array based upon read commands and write commands received from the host server. The disk array may be configured as a Redundant Array of Inexpensive Disks (RAID) configuration, such as a Level 1 RAID configuration (RAID 1). Thus, the disk drive pair may be a RAID disk drive pair, such as a RAID 1 disk drive pair. Further, all the read commands may be directed exclusively to the solid state disk drive and the write commands may be directed to both the solid state disk drive and the hard disk drive. | 2009-12-31 |
| 20090327604 | STORAGE DEVICE, CONTROL DEVICE, STORAGE SYSTEM, AND STORAGE METHOD - A size storage unit stores therein a block size of a memory element. A buffering unit executes buffer processing configured to store data received from a RAID (Redundant Arrays of Inexpensive/Independent Disks) controller into a buffer, and to write the data stored in the buffer into the memory element. A stripe-size receiving unit receives a stripe size that indicates a size of a unit of access at time of access to the memory element by the RAID controller. Writing processing is configured to write data received from the RAID controller into the memory element without executing the buffer processing by the buffering unit, when the stripe size is n times of the block size (n is a positive integer). | 2009-12-31 |
| 20090327605 | DISK ARRAY APPARATUS, CONTROLLER AND CONTROLLING METHOD THEREFOR, AND RECORDING MEDIUM IN WHICH CONTROLLING PROGRAM IS STORED - A disk array apparatus includes a first converting unit that performs first conversion on storing object data received in a first control unit from a controller to convert the storing object data into data in a second control unit, the controller including a selecting section that selects, on the basis of the access state monitored by a monitoring section, one from the controller and said first converting unit, and a second converting unit that performs, if the controller is selected by the selecting section, a second conversion, different from the first conversion, on the object data to convert the object data managed in the first control unit into the data in the second control unit. With this configuration, the disk array apparatus accomplishes the object to improve the accessibility to different types of storage units that manage data storing in different control units. | 2009-12-31 |
| 20090327606 | METHOD AND SYSTEM FOR EXECUTION OF APPLICATIONS IN CONJUNCTION WITH DISTRIBUTED RAID - Systems and methods are disclosed which allow various applications which may utilize a distributed RAID system (or other types of applications) to be executed on the same set of computing devices which implement that distributed RAID system. More particularly, in certain embodiments a virtualization layer may be executed on a data bank. A set of desired application programs may be executed using this virtualization layer, where the context for each instance of the applications executing on the virtualization layer may be stored in a volume kept utilizing the distributed RAID system. | 2009-12-31 |
| 20090327607 | Apparatus and method for cache utilization - In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed. | 2009-12-31 |
| 20090327608 | Accelerated resume from hibernation in a cached disk system - Various embodiments of the invention use a non-volatile (NV) memory to store hiberfile data before entering a hibernate state, and retrieve the data upon resume from hibernation. Unlike conventional systems, the reserve space in the NV memory (i.e., the erased blocks available to be used while in the run-time mode) may be used to store hiberfile data. Further, a write-through cache policy may be used to assure that all of the hiberfile data saved in cache will also be stored on the disk drive during the hibernation, so that if the cache and the disk drive are separated during hibernation, the full correct hiberfile data will still be available for a resume operation. | 2009-12-31 |
| 20090327609 | Performance based cache management - Methods and apparatus to manage cache memory are disclosed. In one embodiment, an electronic device comprises a first processing unit, a first cache memory, and a first cache controller, and a power management module, wherein the power management module determines at least one operating parameter for the cache memory and passes the at least one operating parameter for the cache memory to a cache controller. Further, the first cache controller manages the cache memory according to the at least one operating parameter, and the power management module evaluates, in the power management module, operating data for the cache memory from the cache controller, and generates, in the power management module, at least one modified operating parameter for the cache memory based on the operating data for the cache memory from the cache controller. | 2009-12-31 |
| 20090327610 | Method and System for Conducting Intensive Multitask and Multiflow Calculation in Real-Time - The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit (ESCU) for assigning threads of an application, the non-critical threads being run by the central processor core (SPP), whereas the intensive or specialized threads are assigned to an auxiliary processing part (APP) comprising a set of N auxiliary calculation units (APU | 2009-12-31 |
| 20090327611 | DOMAIN-BASED CACHE MANAGEMENT, INCLUDING DOMAIN EVENT BASED PRIORITY DEMOTION - Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing. | 2009-12-31 |
| 20090327612 | Access Speculation Predictor with Predictions Based on a Domain Indicator of a Cache Line - An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM. | 2009-12-31 |
| 20090327613 | System and Method for a Software Managed Cache in a Multiprocessing Environment - A method for implementing a software-managed cache comprises determining an object identifier (ID) for each of a first set of objects of a plurality of objects resident in a local memory, to generate a first cache table, the first cache table comprising a plurality of entries. Each object comprises an object ID and an effective address. The method receives a request for an object, the request comprising an object ID. The method compares the received object ID with the entries in the first cache table. In the event the received object ID matches an entry in the first cache table, the method returns the matching entry in response to the request. In the event the received object ID does not match an entry in the first cache table, the method calculates an effective address in the local memory of the object associated with the object ID. | 2009-12-31 |
| 20090327614 | CACHE TENTATIVE READ BUFFER - An apparatus having a cache and a circuit. The cache may store old lines having old instructions. The circuit may (i) receive a first read command, (ii) fetch-ahead a new line having new instructions into a buffer sized to hold a single line, (iii) receive a second read command, (iv) present through a port a particular new instruction in response to both (a) a cache miss of the second read command and (b) a buffer hit of the second read command and (v) overwrite a particular old line with the new line in response to both (a) the cache miss of the second read command and (b) the buffer hit of the second read command such that (1) the first new line resides in all of the cache, the buffer and the memory and (2) the particular old line resides only in the memory. | 2009-12-31 |
| 20090327615 | Access Speculation Predictor with Predictions Based on a Scope Predictor - An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary. | 2009-12-31 |
| 20090327616 | SNOOP FILTERING MECHANISM - A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated directory storage, directory entries may be stored in designated locations of a shared cache memory subsystem, such as an L3 cache. Directory entries are stored within the shared cache memory subsystem to provide indications of lines (or blocks) that may be cached in exclusive-modified, owned, shared, shared-one, or invalid coherency states. The absence of a directory entry for a particular line may imply that the line is not cached anywhere in a computing system. | 2009-12-31 |
| 20090327617 | Shared Object Control - Methods, systems, and computer program products for controlling information read/write processing. The method includes assigning a plurality of division areas to a shared storage area for storing a shared object: specifying a division area used for read/write processing in accordance with user identification information for identifying a user; and executing the read processing for reading information from a specified division area and the write processing for writing information to the specified division area. The shared object is shared among a plurality of processes. | 2009-12-31 |
| 20090327618 | Method for Self Optimizing Value Based Data Allocation Across A Multi-Tier Storage System - A method, apparatus, and article of manufacture are provided to support dynamic assignment of data from a continuous stream of data to one or more storage devices in a storage network. The storage network is configured with one or more tiers in a hierarchy, with at least one storage device in each tier. Similarly, the storage network is in communication with both a storage manager and a data manager. The storage manager sorts the storage devices, maintains a demand function of each device, and calculates a burn rate for each storage device. The data manager is in communication with the storage manager and assigns data from the received stream of data to at least one of the storage devices. | 2009-12-31 |
| 20090327619 | Access Speculation Predictor with Predictions Based on Memory Region Prior Requestor Tag Information - An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag. | 2009-12-31 |
| 20090327620 | CIRCUIT STRUCTURE AND METHOD FOR DIGITAL INTEGRATED CIRCUIT PERFORMANCE SCREENING - Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met. | 2009-12-31 |
| 20090327621 | VIRTUAL MEMORY COMPACTION AND COMPRESSION USING COLLABORATION BETWEEN A VIRTUAL MEMORY MANAGER AND A MEMORY MANAGER - Enhanced performance and functionality in virtual memory is possible when a virtual memory manager and a memory manager are configured to collaborate. | 2009-12-31 |
| 20090327622 | Method and Apparatus for Computer Memory Traversal - A method, apparatus and computer program product is provided for traversing computer memory. In one example embodiment, a method comprises determining whether a next cluster associated with a file is located in contiguous memory and obtaining a location of a next cluster from a file allocation table when the next cluster associated with the file is not located in contiguous memory. For example, the determining step may comprise reading from a cluster descriptor that is associated with the file wherein the cluster descriptor comprises an indication that a contiguous cluster in a data region is associated with the file. In one embodiment, the file allocation table is located in a first memory and the cluster descriptor is located in a second memory. | 2009-12-31 |
| 20090327623 | COMMAND REORDERABLE MEMORY CONTROLLER - A memory controller includes a plurality of bus interfaces and a memory controller core configured to control a command and data issued from the plurality of bus interfaces and to write or read the command and the data into and from the memory. The memory controller core includes a command control unit configured to receive a plurality of commands issued from the plurality of bus interfaces and to reorder and store the plurality of commands and a write data control unit configured to receive a plurality of pieces of write data issued from the plurality of bus interfaces in a sequence that the command control unit receives the write commands and to output the write data based on the reordered result of the command control unit. Accordingly, latency can be minimized between the memory controller and the memory and downsizing of a circuit of the memory controller can be achieved. | 2009-12-31 |
| 20090327624 | INFORMATION PROCESSING APPARATUS, CONTROLLING METHOD THEREOF, AND PROGRAM - An information processing apparatus controls writing to a disk. A command reception section receives from a host apparatus a write command and a control command controlling a cache about the write command. A queue storage section stores a queue for the write command and the control command received by the command reception section. A control section determines which of a first write command for data of a file and a second write command for metadata corresponding to the file the write command stored in the queue is, groups, when the control command is received by the command reception section, at least one first write command and at least one second write command that have been received and stored in the queue, assigns an execution sequence numbers to the first write command and the second write command in the group such that data write of the first write command to the disk is executed in priority to the data write of the second write command, and controls execution of the first write command and the second write command according to the assigned execution sequence numbers. | 2009-12-31 |
| 20090327625 | MANAGING METADATA FOR DATA BLOCKS USED IN A DEDUPLICATION SYSTEM - Provided are a method, system, and article of manufacture for managing metadata for data blocks used in a deduplication system. File metadata is maintained for files having data blocks in a computer readable device. Data block metadata is maintained for each data block in the computer readable device. The data block metadata for one data block includes a data block reference and content identifier identifying content of the data block. The file metadata for each file includes the data block reference to each data block in the file. A determination is made of an unreferenced data block in the computer readable device that has become unreferenced. Indication is made that the data block metadata for the determined unreferenced data block as unreferenced metadata. The data block reference of the unreferenced metadata is maintained in the computer readable device in response to determining that a includes the data block indicated in the unreferenced metadata. | 2009-12-31 |
| 20090327626 | METHODS AND SYSTEMS FOR MANAGEMENT OF COPIES OF A MAPPED STORAGE VOLUME - Methods and systems for rapid creation of copies of a mapped storage volume. A new copy of a mapped storage volume is created by copying the mapping table and updating meta-data associated with the new copy and any ancestral parents thereof. The physical blocks remain untouched when creating a new copy as does any meta-data associated with the physical blocks. Rather, reference meta-data associated with each physical block is updated only in response to processing of a write request to an identified block of an identified copy of the mapped storage volume. Thus copy creation is rapid as compared to prior techniques reliant on reference counters. | 2009-12-31 |
| 20090327627 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR COPYING DATA - A storage system and a method for copying data is provided. The method includes storing data at a first storage unit of a primary site, transferring the data from the first storage unit to a second storage unit of a remote site and updating shadow storage unit metadata to reflect the storing of the data at the first storage unit, and copying, in response to the updating of the shadow storage unit metadata, the data from an entity that differs from the shadow storage unit to a third storage unit. | 2009-12-31 |
| 20090327628 | SYSTEM AND METHOD FOR RESUMING BACKUP OF A VOLUME AFTER A BACKUP OPERATION PREMATURELY TERMINATES - A first snapshot of a volume is created at a first point in time. A first backup operation to backup the volume to a first backup image using the first snapshot is initiated. The first backup operation terminates before completion, e.g., due to a failure. A second snapshot of the volume representing the state of the volume at a second point in time is then created. The second snapshot is used by a second backup operation to resume backing up the volume to a second backup image. The first backup image is then merged with the second backup image. | 2009-12-31 |
| 20090327629 | Remote Copy Method and Remote Copy System - In a configuration in which it is necessary to transfer data from a first storage system to a third storage system through a storage system between the storage systems, there is a problem that it is inevitable to give an excess logical volume to a second storage system between the storage systems. A remote copy system includes first storage system that sends and receives data to and from an information processing apparatus, a second storage system, and a third storage system. The second storage system virtually has a second storage area in which the data should be written and has a third storage area in which the data written in the second storage area and update information concerning the data are written. Data sent from the first storage system is not written in the second storage area but is written in the third storage area as data and update information. The data and the update information written in the third storage area are read out from the third storage system. | 2009-12-31 |
| 20090327630 | SOFTWARE CONFIGURATION ITEM BACK-UP FACILITY - A system may identify a second software configuration item for possible backup in response to selection of a first software configuration item for backup, where the first and second software configuration items are related. The system may include a detecting unit for detecting information regarding at least one hardware and at least two software configuration items. A repository may store a set of data for each configuration item based on the detected information. The set of data may include a predetermined attribute of the configuration item and a relation between the configuration item and another configuration item. An identifying unit may then identify the second software configuration item from the attribute and/or the relation upon selection of the first software configuration item for backup. | 2009-12-31 |
| 20090327631 | STORAGE SYSTEM, COPY CONTROL METHOD, AND COPY CONTROL UNIT - A system and method of controlling copying including a management table for managing an update target data in a first storage volume and stored locations of before-update data of the update target data in a second storage volume, and relocating data in the second storage volume upon confirming a predetermined range of the first storage volume has been copied into the second storage volume using the management table. | 2009-12-31 |
| 20090327632 | COPYING WORKLOAD FILES TO A VIRTUAL DISK - The present invention is directed to a system and method for transferring workload files on a host to a Virtual Machine (VM) destination disk without the need for the VM to be running. This accomplished by creating a VM disk device interface to move data from the workload files to the VM destination disk. The VM disk device interface comprises a device driver to interact with the VM destination disk and destination access software utilizing standard operating system procedures to access the VM destination disk. | 2009-12-31 |
| 20090327633 | Verifying data integrity in a data storage device - A data storage device may include one or more pages, each page having a fixed number of memory cells, each memory cell being adapted to store one unit of data; a verification page, the verification page having a corresponding fixed number of verification cells, each verification cell storing a predetermined value; and a controller configured to 1) receive a read command having an address value, and 2) upon receiving the read command, a) retrieve a predetermined value from a verification cell corresponding to the address value, b) determine whether the retrieved predetermined value is an expected value, and c) if so, providing a retrieved unit of data, and if not, initiating a protective action. Determining whether the retrieved predetermined value is the expected value may include applying a function to the address value to obtain a result and determining whether the result corresponds to the retrieved predetermined value. | 2009-12-31 |
| 20090327634 | SECURE CONFIGURATION OF TRANSIENT STORAGE DEVICES - Extension fields in a provisioning certificate in the authentication silo of a transient storage device (TSD) are used to provide secure configuration options for TSDs while operating within the constraints of the current IEEE 1667 standard. Immutable values for configurable settings of the storage device are set in extension fields of a provisioning certificate. The provisioning certificate is then installed on the storage device. The method takes advantage of properties unique to the IEEE 1667 certificate silo specification and ITU-T X.509 certificate specification. The method is implemented while satisfying the security requirements for device configuration and taking advantage of the existing standards definitions as they are, without modification. The method allows particular features present in the device firmware to be enabled or disabled. An administrator may choose to set several device settings, for example, the number of addressable command targets (ACTs), the portion of total data storage area allocated to each ACT, and access settings. The method provides for these features to be implemented by the user, post retail sale, in a secure manner. | 2009-12-31 |
| 20090327635 | Data security for use with a file system - An embodiment of the invention provides an apparatus and method for providing data security for use with a file system. The apparatus and method performs acts including: applying a mapping function to data block numbers that are associated with a file; and obtaining mapped data block numbers after applying the mapping function, wherein the mapped data block numbers are addresses of data of the file in a storage device. | 2009-12-31 |
| 20090327636 | COMPRESSED TRANSACTIONAL LOCKS IN OBJECT HEADERS - A software transactional memory system is provided that generates and stores compressed transactional locks in a portion of object headers. The software transactional memory system allocates preferred write log memory with a predefined size of memory that corresponds to a number of bits in the compressed transactional locks. The compressed transactional locks identify write log entries in corresponding write logs in the preferred write log memory. If the preferred write log memory becomes full, additional write log memory is allocated for write log entries and subsequent transactional locks are stored uncompressed in an auxiliary memory. A pointer that may be used to locate the uncompressed transactional lock is stored in the header. If an object header with a compressed transactional lock is needed for another use, the compressed transactional lock is uncompressed and stored in the auxiliary memory. A pointer that may be used to locate the uncompressed transactional lock is stored in the header. | 2009-12-31 |
| 20090327637 | SECURITY SYSTEM FOR COMPUTERS - A security system designed to trap computer viruses is described. The system storage has an external alarm configured to monitor the time every file takes to load by monitoring the drive activity LED of the storage device. The document storage location is hidden and can optionally be accessed via password. If a virus spends an unexpected amount of time attempting to access storage the alarm will trigger. Downloads and other untrusted files are stored in quarantine storage. Documents can only be transferred from the quarantine storage to the system storage via a copy and paste program. | 2009-12-31 |
| 20090327638 | Securely clearing an error indicator - In one embodiment, a controller can perform a secure clear of a poisoned indicator associated with an uncorrectable error (after recovery from the error). To this end, the controller may access a register storing an address of a memory location associated with indicator, determine whether the address corresponds to an entry in a table storing a list of such errors, and perform the clear based at least in part on the determination. Other embodiments are described and claimed. | 2009-12-31 |
| 20090327639 | Optimized Memory Allocation Via Feature Extraction - A method and system for recovering embedded system memory contained within an embedded system includes a software image in embedded system memory and identifying unneeded software features in the software image; identifying memory portions containing the unneeded software features; and reallocating the memory portions containing the unneeded features. | 2009-12-31 |
| 20090327640 | METHOD FOR EXPANDING LOGICAL VOLUME STORAGE SPACE - A method for expanding a logical volume (LV) storage space includes creating an LV by using an LV manager, and allocating a storage space for the LV according to a certain proportion; reserving a continuous expanding space behind the allocated storage space; determining in real time whether the LV storage space needs to be expanded or not during a data writing process till the data has been completely written; if the LV storage space needs to be expanded, obtaining a size of a new expanding space required to be reserved by calculating an increment coefficient of space expansion according to a using situation of the previously reserved expanding space, thereby further reserving a continuous expanding space within a space scope managed by the LV manager; and if the LV storage space does not need to be expanded, directly writing the data. | 2009-12-31 |
| 20090327641 | Dynamic Allocation of a Buffer Across Multiple Clients in a Threaded Processor - A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data. | 2009-12-31 |
| 20090327642 | Storage management program, storage management method, and storage management apparatus - In a computer executing processes based on a storage management program, an attribute collection unit collects attributes of storage nodes. A group creation unit creates at least two groups that include the storage nodes, in accordance with the attributes of the storage nodes collected by the attribute collection unit. A data allocation unit allocates distributed data and redundant distributed data to the groups created by the group creation unit in such a manner that the distributed data and the redundant distributed data having the same content as the distributed data are placed in different groups. | 2009-12-31 |
| 20090327643 | Information Handling System Including Dynamically Merged Physical Partitions - An information handling system includes instruction processing nodes in respective physical partitions. A communications bus couples two information processing nodes together. Each node includes hardware resources such as CPUs, memories and I/O adapters. Prior to a command to merge the physical partitions, the communication bus exhibits a disabled state such that the two information processing nodes are effectively disconnected. After receiving a command to merge the physical partitions, the system enables the communication bus to effectively hot-plug the two nodes together. A modified master hypervisor in one node stores data structures detailing the hardware resources of the two nodes. The modified master may assign resources from one node to a logical partition in another node. | 2009-12-31 |
| 20090327644 | CPU AND MEMORY CONNECTION ASSEMBLY TO EXTEND MEMORY ADDRESS SPACE - Disclosed is a CPU and memory connection assembly to extend memory address space without extending address pins. The CPU and memory connection assembly extends entire accessible memory address of a CPU using a small number of address pins by synthesizing a final memory address by receiving an offset address setting command inputted from a CPU through an offset address decoder to generate an offset address and by receiving CPU max address bit setting command directly inputted from the CPU through an address synthesizer to combine the CPU max address bit setting command with the address directly inputted from the CPU. | 2009-12-31 |
| 20090327645 | SWITCH, INFORMATION PROCESSING APPARATUS, AND ADDRESS TRANSLATION METHOD - A switch connects and disconnects an input and output control device to and from an input and output device. The switch includes a storage unit that stores therein a translation table for use in translating a physical address used on a virtual machine that a guest operating system specifies as a direct memory access transfer destination to the input and output device, into a physical address used on a real machine; and an address translating unit that translates an address contained in a direct memory access request issued by the input and output device into a physical address used on the real machine by referring to the translation table. | 2009-12-31 |
| 20090327646 | Minimizing TLB Comparison Size - In one embodiment, a system comprises one or more registers configured to store a plurality of values that identify a virtual address space (collectively a tag), a translation lookaside buffer (TLB), and a control unit coupled to the TLB and the one or more registers. The control unit is configured to detect whether or not the tag has changed and in response to a change in the tag, map the changed tag to an identifier having fewer bits than the total number of bits in the tag, and provide the current identifier to the TLB. The TLB is configured to detect a hit/miss in response to the identifier. A similar method is also contemplated. | 2009-12-31 |
| 20090327647 | Memory Management Unit Directed Access to System Interfaces - A memory management unit (MMU) for servicing transaction requests from one or more processor threads is described. The MMU can include a translation lookaside buffer (TLB). The TLB can include a storage module and a logic circuit. The storage module can store a bit indicating one of a plurality of interfaces. The bit can be associated with a physical address range. The logic circuit can route a physical address within the physical address range to the one of the plurality of interfaces. | 2009-12-31 |
| 20090327648 | GENERATING MULTIPLE ADDRESS SPACE IDENTIFIERS PER VIRTUAL MACHINE TO SWITCH BETWEEN PROTECTED MICRO-CONTEXTS - Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage. The translation lookaside buffer is to store translations. Each translation lookaside buffer entry includes an address source identifiers. Each address source identifier is to identify a unique micro-context. Each address source identifier is based on a virtual partition identifier. At least two of the of virtual partition identifiers are associated with one of the virtual machines | 2009-12-31 |
| 20090327649 | Three-Tiered Translation Lookaside Buffer Hierarchy in a Multithreading Microprocessor - A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB. | 2009-12-31 |
| 20090327650 | DEVICE AND METHOD FOR BYPASSING A FIRST PROGRAM CODE PORTION WITH A REPLACEMENT PROGRAM CODE PORTION - A device comprises a processor configured to execute a sequence of program instructions, a first storage configured to store a first memory address, a second storage configured to store a second memory address, a program counter configured to determine a memory address of program instructions to be executed, and a program counter manipulator configured to set the program counter to a value corresponding to a content of the second storage in response to the program counter reaching a value corresponding to a content of the first storage. | 2009-12-31 |
| 20090327651 | Information Handling System Including A Multiple Compute Element Processor With Distributed Data On-Ramp Data-Off Ramp Topology - A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip. | 2009-12-31 |
| 20090327652 | METHOD FOR CONSTRUCTING A VARIABLE BITWIDTH VIDEO PROCESSOR - A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation. | 2009-12-31 |
| 20090327653 | RECONFIGURABLE COMPUTING CIRCUIT - A reconfigurable computing circuit for reducing amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block | 2009-12-31 |
| 20090327654 | Method of Handling Duplicate or Invalid Node Controller IDs in a Distributed Service Processor Environment - A method for enabling a Node Controller (NC), which claims a duplicate or invalid service processor Node Controller Identification (NCID) in a distributed service processor system, to be integrated into the system includes reading an NCID by the NC after the NC is booted, saving the NCID into a non-volatile storage and broadcasting an NC Present Message (NPM) to a Service Processor (SC) repeatedly until the SC initiates communication, updating the NCID for the NC in the non-volatile storage when the NC receives an NCID change message from the SC and rating any future NPM as a new NCID, and checking a record of an new NC in the non-volatile storage when the SC receives the NPM from the NC. If the SC has a record of a recorded NC with the same NCID as the new NC, then the SC checks its role as a primary SC. If the SC does not have the record of the recorded NC with the same NCID as the new NC, then the SC checks validity of the NCID. | 2009-12-31 |
| 20090327655 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD PERFORMED BY SEMICONDUCTOR DEVICE - The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information. | 2009-12-31 |
| 20090327656 | EFFICIENCY-BASED DETERMINATION OF OPERATIONAL CHARACTERISTICS - Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core) awaiting a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. Other embodiments are described and claimed. | 2009-12-31 |
| 20090327657 | GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops) - A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports. | 2009-12-31 |
| 20090327658 | COMPARE, SWAP AND STORE FACILITY WITH NO EXTERNAL SERIALIZATION - A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation. | 2009-12-31 |
| 20090327659 | TRAP-BASED MECHANISM FOR TRACKING MEMORY ACCESSES - In general, the invention relates to a method. The method includes receiving notification, which includes context information, of a trap. The method further includes accessing, based at least partially upon the context information, a particular instruction that caused the trap, determining, based at least partially upon the context information, a particular address that is to be accessed by the particular instruction, updating a set of log information to indicate accessing of the particular address, causing subsequent accesses of the particular address to not give rise to a trap, after causing subsequent accesses of the particular address to not give rise to a trap, accessing the particular address, after accessing the particular address, causing subsequent accesses of the particular address to give rise to a trap, and causing the particular instruction to not be executed. | 2009-12-31 |
| 20090327660 | MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT - Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three separate precharge timings may be used, e.g., optimized per memory bank, per memory bank group, and/or per a memory device. Other embodiments are also disclosed and claimed. | 2009-12-31 |
| 20090327661 | MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS - Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed. | 2009-12-31 |
| 20090327662 | Managing active thread dependencies in graphics processing - A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be executed before the first thread's execution. Thread execution may be freely reordered, subject only to the rule that a second thread, whose execution is dependent on execution of a first thread, can only be executed after the first thread. | 2009-12-31 |
| 20090327663 | Power Aware Retirement - In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated with an executed instruction if information associated with the executed instruction is stored in an on-demand portion of at least one of arrays. Other embodiments are described and claimed. | 2009-12-31 |
| 20090327664 | Arithmetic processing apparatus - An arithmetic processing apparatus includes an operation circuit group that performs encryption and a redundant operation circuit group configured the same as the operation circuit group. The arithmetic processing apparatus, while performing encryption, performs normal encryption in the operation circuit group, and performs an encryption mask processing program by using data and the like randomly generated by a random data generating unit and the like in the redundant operation circuit group. The arithmetic processing apparatus, when not performing encryption, performs normal arithmetic processing in the redundant operation circuit group. | 2009-12-31 |
| 20090327665 | Efficient parallel floating point exception handling in a processor - Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication. | 2009-12-31 |
| 20090327666 | METHOD AND SYSTEM FOR HARDWARE-BASED SECURITY OF OBJECT REFERENCES - A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item, determining a data type supported by the first destination, comparing the data type of the first data item with the data type supported by the first destination to test a validity of the first instruction, and moving the first data item from the first source to the first destination based on the validity of the first instruction. | 2009-12-31 |
| 20090327667 | System and Method to Perform Fast Rotation Operations - Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value. | 2009-12-31 |
| 20090327668 | Multi-Threaded Processes For Opening And Saving Documents - Tools and techniques are described for multi-threaded processing for opening and saving documents. These tools may provide load processes for reading documents from storage devices, and for loading the documents into applications. These tools may spawn a load process thread for executing a given load process on a first processing unit, and an application thread may execute a given application on a second processing unit. A first pipeline may be created for executing the load process thread, with the first pipeline performing tasks associated with loading the document into the application. A second pipeline may be created for executing the application process thread, with the second pipeline performing tasks associated with operating on the documents. The tasks in the first pipeline are configured to pass tokens as input to the tasks in the second pipeline. | 2009-12-31 |
| 20090327669 | INFORMATION PROCESSING APPARATUS, PROGRAM EXECUTION METHOD, AND STORAGE MEDIUM - According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including preceding and succeeding information of the program module, an adding module extracting graph data structure creation information to which the input data is given, creating a node, and adding the created node to a formerly created graph data structure, and an execution module subjecting the graph data structure to at least one of depth-first search and breadth-first search with a restricted breadth, selecting one node from nodes stored in the node memory, and executing a program module corresponding to the selected node. | 2009-12-31 |
