53rd week of 2009 patent applcation highlights part 17 |
Patent application number | Title | Published |
20090321776 | Multi-chip package for LED chip and multi-chip package LED device including the multi-chip package - Provided is a multi-chip package light emitting diode (LED) device including a plurality of LED chips within a single package. The LED device may include a base substrate, a multi-chip package for a LED on the base substrate, and a light radiator surrounding the multi-chip package and radiating light emitted by the multi-chip package for a LED, wherein the multi-chip package for a LED may include a plurality of LED chips on a single wafer substrate. | 2009-12-31 |
20090321777 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor package and a semiconductor light-emitting device including the semiconductor package. The semiconductor package includes: a frame for mounting a semiconductor light-emitting element; and a lead integral with the frame. The frame and the lead are made of a resin. A metal film is located in a predetermined area on the frame. | 2009-12-31 |
20090321778 | FLIP-CHIP LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A flip-chip light emitting diode includes a substrate, an LED chip and a plurality of conductive bumps. The substrate has at least one recess defined in the surface of the substrate, and at least a part of the conductive bumps is embedded the at least one recess. The LED chip is mounted on a surface of the substrate by a flip-chip mounting process. The conductive bumps are sandwiched between the substrate and the LED chip to bond and electrically connect the LED chip to the substrate. | 2009-12-31 |
20090321779 | SIDE VIEW LIGHT EMITTING DIODE PACKAGE - A side view LED package for a backlight unit includes a package body having a cavity with an inclined inner sidewall, first and second lead frames arranged in the package body, the cavity of the package body exposing a portion of at least one of the first and second lead frames placed in a bottom of the cavity to outside, a light emitting diode chip mounted on the bottom of the cavity to be electrically connected to the first and second lead frames, and a transparent encapsulant arranged in the cavity surrounding the light emitting diode chip. The cavity has a depth larger than a mounting height of the light emitting diode chip and not exceeding six times of the mounting height. The height of the sidewall is shortened to improve beam angle characteristics of emission light, increase light quantity, and prevent a molding defect of the sidewall. | 2009-12-31 |
20090321780 | GALLIUM NITRIDE-BASED LIGHT EMITTING DEVICE WITH ROUGHENED SURFACE AND FABRICATING METHOD THEREOF - A gallium nitride-based light emitting device with a roughened surface is described. The light emitting device comprises a substrate, a buffer layer grown on the substrate, an n-type III-nitride semiconductor layer grown on the buffer layer, a III-nitride semiconductor active layer grown on the n-type III-nitride semiconductor layer, a first p-type III-nitride semiconductor layer grown on the III-nitride semiconductor active layer, a heavily doped p-type III semiconductor layer grown on the first p-type III-nitride semiconductor, and a roughened second p-type III-nitride semiconductor layer grown on the heavily doped p-type III semiconductor layer. | 2009-12-31 |
20090321781 | QUANTUM DOT DEVICE AND METHOD OF MAKING THE SAME - A semiconductor device includes an Al | 2009-12-31 |
20090321782 | Apparatus And Method For Nanowire Optical Emission - An optical emitter includes at least one nanowire connected in a circuit such that current selectively flows into the nanowire. The nanowire has a length-to-diameter ratio of ten or less. A method for generating optical emission includes applying a voltage across a nanowire to inject charge carriers into the nanowire, the nanowire having a length-to-diameter ratio of ten or less; and confining the charge carriers within the nanowire by placing a high bandgap material at each end of the nanowire, wherein the charge carriers recombine to emit optical energy. | 2009-12-31 |
20090321783 | Semiconductor Device - A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the semiconductor chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the semiconductor chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the semiconductor chip and the base electrode, wherein both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member. | 2009-12-31 |
20090321784 | Semiconductor Device and Method of Forming Lateral Power MOSFET with Integrated Schottky Diode on Monolithic Substrate - A monolithic semiconductor device has an insulating layer formed over a first substrate. A second substrate is disposed over the first insulating layer. A power MOSFET with body diode is formed over the second substrate. A Schottky diode is formed over the second substrate in proximity to the MOSFET. An insulation trench is formed within the second substrate between the MOSFET and Schottky diode. The isolation trench surrounds the MOSFET and first Schottky diode. A first electrical connection is formed between a source of the MOSFET and an anode of the Schottky diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the Schottky diode. The Schottky diode reduces charge build-up within the body diode and reverse recovery time of the first power MOSFET. The power MOSFET and integrated Schottky can be used in power conversion or audio amplifier circuit. | 2009-12-31 |
20090321785 | LIGHT RECEIVING DEVICE - A light receiving device having small dark current and capable of sensing light in the wavelength range of 2.0 μm to 3.0 μm with high sensitivity is provided. The light receiving device has an InP substrate, and a light receiving layer formed by alternately stacking a larger layer formed of GaInNAsSbP mixed crystal having nitrogen content of at most 5% in 5 group, larger lattice constant than that of InP and thickness between hc and 11hc, the critical thickness hc being determined as hc=b(1−ν cos | 2009-12-31 |
20090321786 | Band Gap Modulated Optical Sensor - A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided. | 2009-12-31 |
20090321787 | High voltage GaN-based heterojunction transistor structure and method of forming same - A semiconductor device includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A flash layer is disposed on the second active layer and source, gate and drain contacts are disposed on the flash layer. | 2009-12-31 |
20090321788 | DIELECTRIC LEDGE FOR HIGH FREQUENCY DEVICES - High frequency performance of (e.g., silicon) bipolar devices ( | 2009-12-31 |
20090321789 | Triangle two dimensional complementary patterning of pillars - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape. | 2009-12-31 |
20090321790 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT - A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion. | 2009-12-31 |
20090321791 | Integrated Circuits, Standard Cells, and Methods for Generating a Layout of an Integrated Circuit - An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output. | 2009-12-31 |
20090321792 | SEPARATIVE EXTENDED GATE FIELD EFFECT TRANSISTOR BASED URIC ACID SENSING DEVICE, SYSTEM AND METHOD FOR FORMING THEREOF - A separative extended gate field effect transistor based uric acid sensing device is provided, including: a substrate; a conductive layer including a silver paste layer on the substrate and a graphite-based paste layer on the silver paste layer; a conductive wire extended from the conductive layer; a titanium dioxide layer on the conductive layer; and a uric acid enzyme sensing film on the titanium dioxide layer. | 2009-12-31 |
20090321793 | DEVICE SENSITIVE TO A MOVEMENT COMPRISING AT LEAST ONE TRANSISTOR - The invention relates to a detection device using at least one transistor ( | 2009-12-31 |
20090321794 | CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS - The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer. | 2009-12-31 |
20090321795 | SELECTIVE FORMATION OF DIELECTRIC ETCH STOP LAYERS - Methods to selectively form a dielectric etch stop layer over a patterned metal feature. Embodiments include a transistor incorporating such an etch stop layer over a gate electrode. In accordance with certain embodiments of the present invention, a metal is selectively formed on the surface of the gate electrode which is then converted to a silicide or germanicide. In other embodiments, the metal selectively formed on the gate electrode surface enables a catalytic growth of a silicon or germanium mesa over the gate electrode. At least a portion of the silicide, germanicide, silicon mesa or germanium mesa is then oxidized, nitridized, or carbonized to form a dielectric etch stop layer over the gate electrode only. | 2009-12-31 |
20090321796 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer. | 2009-12-31 |
20090321797 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode. | 2009-12-31 |
20090321798 | CMOS Image Sensor and Method of Manufacturing the Same - Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process. | 2009-12-31 |
20090321799 | Method and apparatus for increasing conversion gain in imagers - A method, apparatus, and system providing a pixel having increased conversion gain by decreasing the size of an output charge storage region to less than that of a photosensor. A pixel readout is executed by multiple sampling signals based on portions of charge transferred from the photosensor to the storage region and combining the sampled signals in either the analog domain or the digital domain into a representative pixel output signal. | 2009-12-31 |
20090321800 | SEMICONDUCTOR DEVICE INCLUDING SOLID STATE IMAGE PICKUP DEVICE, AND PORTABLE ELECTRONIC APPARATUS - A semiconductor device includes: a plurality of pixel units disposed in a matrix shape, each of the plurality of pixel units including: a first photoelectric conversion element for converting incident light of a first color into signal charges; a second photoelectric conversion element for converting incident light of a second color into signal charges; a third photoelectric conversion element for converting incident light of a third color into signal charges; and a detector circuit shared by the first to third photoelectric conversion elements for detecting the signal charges converted by each of the first to third photoelectric conversion elements, wherein the plurality of pixel units are pixel units adjacently disposing a row (column) juxtaposing the first photoelectric conversion element and detector circuit and a row (column) juxtaposing the second and third photoelectric conversion elements. | 2009-12-31 |
20090321801 | CAPACITOR INSULATING FILM, METHOD FOR FABRICATING THE SAME, CAPACITOR ELEMENT, METHOD FOR FABRICATING THE SAME, SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR FABRICATING THE SAME - A capacitor insulating film is composed of a ferroelectric film formed on a substrate and containing an element functioning as a crystal nucleus which allows the growth of a crystal in a random crystal orientation. | 2009-12-31 |
20090321802 | PUMPING MOS CAPACITOR - A pumping MOS capacitor includes a substrate which is conductive and includes an irregular surface, a dielectric film formed along the irregular surface of the substrate and a gate formed on the dielectric film. | 2009-12-31 |
20090321803 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a substrate having a cell array region and a peripheral circuit region, a lower structure on the substrate in the cell array region, a first insulation layer on the substrate across the cell array region and the peripheral circuit region, the lower structure being covered with the first insulation layer, a capacitor on the first insulation layer in the cell array region, the capacitor including a lower electrode, a dielectric layer patter, and an upper electrode, a second insulation layer on the first insulation layer, the capacitor being covered with the second insulation layer, a first upper wiring structure on the second insulation layer, the first upper wiring structure being electrically connected to the capacitor and including an upper wiring and a mask pattern, and at least one dummy structure in the peripheral circuit region. | 2009-12-31 |
20090321804 | SEMICONDUCTOR COMPONENT INCLUDING A DRIFT ZONE AND A DRIFT CONTROL ZONE - A semiconductor component including a drift zone and a drift control zone. One embodiment provides a transistor component having a drift zone, a body zone, a source zone and a drain zone. The drift zone is arranged between the body zone and the drain zone. The body zone is arranged between the source zone and the drift zone. | 2009-12-31 |
20090321805 | INSULATOR MATERIAL OVER BURIED CONDUCTIVE LINE - One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed. | 2009-12-31 |
20090321806 | NONVOLATILE MEMORY WITH FLOATING GATES WITH UPWARD PROTRUSIONS - Substrate isolation regions ( | 2009-12-31 |
20090321807 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM - A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film and in which a coupling capacitance of the first semiconductor region is larger than that of the second semiconductor region, first source and drain layers formed on the first semiconductor region to interpose the floating gate electrode therebetween, a first and second wiring lines connected to the first source and drain layers, respectively, second source and drain layers formed on the second semiconductor region to interpose the floating gate electrode therebetween, and a third wiring line connected to the second source and drain layers in common. | 2009-12-31 |
20090321808 | STRUCTURES, FABRICATION METHODS, AND DESIGN STRUCTURES FOR MULTIPLE BIT FLASH MEMORY CELLS - A semiconductor structure, a fabrication method, and a design structure of the same. The semiconductor structure includes (i) a semiconductor substrate which includes a top substrate surface perpendicular to the top substrate surface, (ii) a control gate electrode region and a first semiconductor body region on the semiconductor substrate, and (iii) a second semiconductor body region on the first semiconductor body region. The semiconductor structure further includes (i) a first gate dielectric region sandwiched between the first semiconductor body region and the control gate electrode region and (ii) a second gate dielectric region sandwiched between the second semiconductor body region and the control gate electrode region. The second semiconductor body region overlaps the first semiconductor body region in the reference direction. A first thickness of the first gate dielectric region is different from a second thickness of the second gate dielectric region. | 2009-12-31 |
20090321809 | GRADED OXY-NITRIDE TUNNEL BARRIER - Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed. | 2009-12-31 |
20090321810 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM - Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer. | 2009-12-31 |
20090321811 | MEMORY CELL TRANSISTORS HAVING BANDGAP-ENGINEERED TUNNELING INSULATOR LAYERS, NON-VOLATILE MEMORY DEVICES INCLUDING SUCH TRANSISTORS, AND METHODS OF FORMATION THEREOF - A memory cell transistor comprises: an active region, the active region being elongated in a first direction of extension; a tunnel layer on the active region, the tunnel layer comprising a first tunnel insulating layer, a second tunnel insulating layer on the first tunnel insulating layer and a third tunnel insulating layer on the second tunnel insulating layer; a charge storage layer on the tunnel layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer, the control gate electrode being elongated in a second direction of extension that is transverse the first direction of extension, the active region having a first width in the second direction of extension, the second tunnel insulating layer having a second width in the second direction of extension, the second width being different than the first width. | 2009-12-31 |
20090321812 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof. | 2009-12-31 |
20090321813 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar. | 2009-12-31 |
20090321814 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor memory device includes, in a memory region, a plurality of bit line diffusion layers, a plurality of word lines, and a plurality of memory elements composed of a bit line diffusion layer pair, a gate insulating film, and a gate electrode. The plurality of bit line diffusion layers are divided into plural in respective columns, and are connected electrically to each other through bit line contact diffusion layers. The width of sidewall insulating films on the sides of the bit line contact diffusion layers formed at the word lines arranged adjacent to the bit line contact diffusion layers is smaller than that of the sidewall insulating films formed on the opposite sides of the bit line contact diffusion layers. | 2009-12-31 |
20090321815 | Non-volatile memory device and method of fabricating the same - A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type. | 2009-12-31 |
20090321816 | Vertical-type non-volatile memory device - In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars. | 2009-12-31 |
20090321817 | Structure and Method for Forming a Shielded Gate Trench FET with an Inter-Electrode Dielectric Having a Nitride Layer Therein - A shielded gate field effect transistor (FET) comprises a plurality of trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench, and a gate electrode is disposed over the shield electrode in each trench. An inter-electrode dielectric (IED) extends between the shield electrode and the gate electrode. The IED comprises a first oxide layer and a nitride layer over the first oxide layer. | 2009-12-31 |
20090321818 | SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE - A semiconductor component with a two-stage body zone. One embodiment provides semiconductor component including a drift zone, and a compensation zone of a second conduction type. The compensation zone is arranged in the drift zone. A source zone and a body zone is provided. The body zone is arranged between the source zone and the drift zone. A gate electrode is arranged adjacent to the body zone. The body zone has a first body zone section and a second body zone section, which are adjacent to one another along the gate dielectric and of which the first body zone section is doped more highly than the second body zone section. | 2009-12-31 |
20090321819 | Semiconductor device having super junction - A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative. | 2009-12-31 |
20090321820 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including: a gate electrode formed in a recess dug in the surface of a semiconductor substrate, with a gate insulating film interposed between the gate electrode and the semiconductor substrate; a source-drain diffusion layer formed on that surface of the semiconductor substrate which is adjacent to both sides of the gate electrode; and a stress applying layer which is formed deep from the surface of the semiconductor substrate in such a way as to cover the surface of the source-drain diffusion layer. | 2009-12-31 |
20090321821 | SEMICONDUCTOR DEVICE HAVING RECESS GATE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a recess gate includes a semiconductor substrate having a recess, a conductive pattern for a gate electrode filled into the recess, and having an extension portion protruding higher than a surface of the semiconductor substrate, an epitaxial semiconductor layer having a top surface disposed over the semiconductor substrate, and a gate insulating layer disposed between the epitaxial semiconductor layer and the conductive pattern, and between the semiconductor substrate and the conductive pattern. Further, a method of fabricating the same is disclosed. | 2009-12-31 |
20090321822 | HIGH-VOLTAGE TRANSISTOR WITH IMPROVED HIGH STRIDE PERFORMANCE - A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible. | 2009-12-31 |
20090321823 | Semiconductor Device and Manufacturing Method Thereof - A high voltage semiconductor device and a manufacturing method thereof are provided. The high voltage semiconductor device comprises: second conductive type drift regions disposed spaced from each other on a first conductive type well region formed on a first conductive type semiconductor substrate; a gate electrode on a channel region between the second conductive type drift regions with a gate insulating film disposed therebetween; second conductive type high-concentration source and drain each disposed in the second conductive type drift regions, spaced from a side of a gate electrode; a gate spacer having a spacer part covering the side of the gate electrode and a spacer extending part to cover a spaced portion of the second conductive type high-concentration source and drain from the side of the gate electrode; and a silicide formed on the gate electrode and the second conductive type high-concentration source and drain. | 2009-12-31 |
20090321824 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate insulating film formed over a semiconductor substrate, a gate electrode formed over the gate insulating film, a source region formed in the semiconductor substrate, a first drain region formed on the other side of the gate electrode and formed in the semiconductor substrate, the first drain region having one end extending below the gate electrode, the first drain region having a first impurity concentration, a second drain region formed in the first drain region and spaced apart from the gate electrode by a first distance, the second drain region having a second impurity concentration higher than the first impurity concentration, a third drain region formed in the first drain region and spaced apart from the gate electrode by a second distance, the second distance being greater than the first distance, the third drain region having a third impurity concentration. | 2009-12-31 |
20090321825 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, BIPOLAR-CMOS-DMOS AND METHOD FOR FABRICATING THE SAME - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions. | 2009-12-31 |
20090321826 | METHOD FOR MANUFACTURING A HIGH INTEGRATION DENSITY POWER MOS DEVICE - A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure comprising said thick dielectric layer and said gate oxide. | 2009-12-31 |
20090321827 | SEMICONDUCTOR DEVICE REDUCING OUTPUT CAPACITANCE DUE TO PARASITIC CAPACITANCE - Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result. | 2009-12-31 |
20090321828 | STRUCTURES, FABRICATION METHODS, DESIGN STRUCTURES FOR STRAINED FIN FIELD EFFECT TRANSISTORS (FINFETS) - A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region. | 2009-12-31 |
20090321829 | LOW-COST DOUBLE-STRUCTURE SUBSTRATES AND METHODS FOR THEIR MANUFACTURE - In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates. | 2009-12-31 |
20090321830 | INTEGRATED CIRCUIT DEVICE, SYSTEM, AND METHOD OF FABRICATION - A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portions that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion. | 2009-12-31 |
20090321831 | PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION - Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET. | 2009-12-31 |
20090321832 | Semiconductor Device - A semiconductor device according to this invention is provided with a MOS transistor of at least one type, wherein the MOS transistor has a semiconductor layer (SOI layer) provided on an SOI substrate and a gate electrode provided on the SOI layer and is normally off by setting the thickness of the SOI layer so that the thickness of a depletion layer caused by a work function difference between the gate electrode and the SOI layer becomes greater than that of the SOI layer. | 2009-12-31 |
20090321833 | VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC - Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure. | 2009-12-31 |
20090321834 | Substrate fins with different heights - A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. | 2009-12-31 |
20090321835 | THREE-DIMENSIONAL TRANSISTOR WITH DOUBLE CHANNEL CONFIGURATION - A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional three-dimensional transistor architectures. The double channel three-dimensional transistors may be used for forming a static RAM cell with a reduced number of transistors, while also providing scalability by taking advantage of the enhanced controllability of FinFETS and nano pipe transistor architectures. | 2009-12-31 |
20090321836 | DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR - Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations. | 2009-12-31 |
20090321837 | CONTACT TRENCHES FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS - Scalability of a strain-inducing mechanism on the basis of a stressed dielectric overlayer may be enhanced by forming a single stress-inducing layer in combination with contact trenches, which may shield a significant amount of a non-desired stress component in the complementary transistor, while also providing a strain component in the transistor width direction when the contact material may be provided with a desired internal stress level. | 2009-12-31 |
20090321838 | CMOS DEVICE AND METHOD OF MANUFACTURING SAME - A CMOS device includes NMOS ( | 2009-12-31 |
20090321839 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a silicon substrate; an N-channel field-effect transistor including a first gate insulating film on the silicon substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and a P-channel field-effect transistor including a second gate insulating film on the silicon substrate, a second gate electrode on the second gate insulating film and a second source/drain region. Each of the first and second gate electrodes includes a crystallized nickel silicide region containing an impurity element, the crystallized nickel silicide region being contact with the first or second gate insulating film, and a barrier layer region in an upper portion including an upper surface of the gate electrode, the barrier layer region containing an Ni diffusion-preventing element higher in concentration than that of a lower portion below the upper portion. | 2009-12-31 |
20090321840 | STRAINED SEMICONDUCTOR DEVICE - A semiconductor device having: a semiconductor substrate; an isolation trench formed in a surface portion of the semiconductor substrate and defining an NMOSFET active region and a PMOSFET active region; a silicon oxide film burying only a lower portion of the isolation trench and defining a recess above the lower portion; an NMOSFET structure formed in the NMOSFET active region and having an insulated gate electrode structure and n-type source/drain regions; a PMOSFET structure formed in the PMOSFET active region and having an insulated gate electrode structure and p-type source/drain regions; a tensile stress film covering the NMOSFET structure and extending to the recess surrounding the NMOSFET active region and to the recess outside the PMOSFET active region along a gate width direction; and a compressive stress film covering the PMOSFET structure and extending to the recess outside the PMOSFET active region along a channel length direction. | 2009-12-31 |
20090321841 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS - A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used. | 2009-12-31 |
20090321842 | Method for manufacturing semiconductor device including metal gate electrode and semiconductor device - A first metal film mainly including Ta is formed on a gate insulating film in a region excluding an n MOS transistor formation region and then a polysilicon film is formed to cover the gate insulating film and the first metal film. A first dummy electrode is formed by selectively removing the gate insulating film and the polysilicon film by etching, and a second dummy gate is formed by selectively removing the gate insulating film, the first metal film and the polysilicon film. An insulating layer is formed to embed the dummy gate electrodes and to expose an upper surface of the dummy gate electrodes. The polysilicon film of the dummy gate electrodes is removed to form recesses in the insulating layer, then a second metal film is formed within the recesses and on the insulating layer, and the second metal film is selectively polished. | 2009-12-31 |
20090321843 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND A SI/GE MATERIAL IN THE DRAIN AND SOURCE AREAS OF THE PMOS TRANSISTOR - The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques. | 2009-12-31 |
20090321844 | SEMICONDUCTOR DEVICE - A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric. | 2009-12-31 |
20090321845 | SHORT CHANNEL LV, MV, AND HV CMOS DEVICES - Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region. | 2009-12-31 |
20090321846 | Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device - A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate. | 2009-12-31 |
20090321847 | HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME - The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having gapped dual stressors with dielectric gap fillers. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A tensilely stressed dielectric layer overlays the n-FET, and a compressively stressed dielectric layer overlays the p-FET. A gap is located between the tensilely and compressively stressed dielectric layers and is filled with a dielectric filler material. In one specific embodiment of the present invention, both the tensilely and compressively stressed dielectric layers are covered by a layer of the dielectric filler material, which is essentially free of stress. In an alternatively embodiment of the present invention, the dielectric filler material is only present in the gap between the tensilely and compressively stressed dielectric layers. | 2009-12-31 |
20090321848 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate | 2009-12-31 |
20090321849 | SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT, AND SEMICONDUCTOR MANUFACTURING METHOD - A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness. | 2009-12-31 |
20090321850 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 2009-12-31 |
20090321851 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device | 2009-12-31 |
20090321852 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A P type drift layer is formed in an N type epitaxial layer from under a drain layer to under an N type body layer under a source layer through under an element isolation insulation film. This P type drift layer is shallower immediately under the drain layer than under the element isolation insulation film, and gradually shallows from under the element isolation insulation film to the N type body layer to be in contact with the bottom of the N type body layer. Since the P type drift layer is thus diffused in a wide region, a wide current path is formed from the N type body layer to the drain layer, and the current drive ability is enhanced and the drain breakdown voltage is also increased. | 2009-12-31 |
20090321853 | HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE - The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) | 2009-12-31 |
20090321854 | MIS FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An MIS field effect transistor includes a nitride semiconductor multilayer structure including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type which is arranged on the first group III-V nitride semiconductor layer, and a third group III-V nitride semiconductor layer of the first conductivity type which is arranged on the second group III-V nitride semiconductor layer. A gate insulating film is formed on a wall surface ranging over the first, second and third group III-V nitride semiconductor layers so that the film stretches over the first, second and third group III-V nitride semiconductor layer. A gate electrode made of a conductive material is formed so that it faces the second group III-V nitride semiconductor layer via the gate insulating film. A drain electrode is provided to be electrically connected to the first group III-V nitride semiconductor layer, and a source electrode is provided to be electrically connected to the third group III-V nitride semiconductor layer. | 2009-12-31 |
20090321855 | Boundaries with elevated deuterium levels - A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium. | 2009-12-31 |
20090321856 | SELF-ALIGNED INSULATING ETCHSTOP LAYER ON A METAL CONTACT - A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer. | 2009-12-31 |
20090321857 | SYSTEMS AND METHODS FOR REDUCED STRESS ANCHORS - Anchor systems and methods anchor components of a Micro-Electro-Mechanical Systems (MEMS) device to a substrate. An exemplary embodiment has a trace anchor bonded to a substrate, a device anchor bonded to the substrate, and an anchor flexure configured flexibly couple the trace anchor and the device anchor to substantially prevent transmission of a stress induced in the trace anchor from being transmitted to the device anchor. | 2009-12-31 |
20090321858 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING AND INSPECTION THEREOF - An accelerator sensor includes a semiconductor substrate having a main front surface and a main rear surface, a first groove portion being formed along a front surface pattern, in the main front surface, a second groove portion being formed along a rear surface pattern, in the main rear surface, a through-hole being formed because of connection between at least parts of the first groove portion and the second groove portion and at least one groove width variation portion being formed in at least one of inner walls of the first groove portion. An offset of the rear surface pattern to the front surface pattern can be inspected easily by existence of the groove width variation portion. | 2009-12-31 |
20090321859 | System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, the method includes depositing a cap layer on a magnetic tunnel junction (MTJ) structure, depositing a first spin-on material layer over the cap layer, and etching the first spin-on material layer and at least a portion of the cap layer. | 2009-12-31 |
20090321860 | INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD - An integrated circuit having a magnetic tunnel junction and method. One embodiment provides an integrated circuit having a magnetic tunnel junction is provided. The magnetic tunnel junction includes a barrier layer. The barrier layer includes carbon, pyrolytic carbon, or graphene, or graphite. | 2009-12-31 |
20090321861 | MICROELECTRONIC IMAGERS WITH STACKED LENS ASSEMBLIES AND PROCESSES FOR WAFER-LEVEL PACKAGING OF MICROELECTRONIC IMAGERS - Microelectronic imagers including stacked lens assemblies and process for wafer-level packaging of microelectronic imagers. One embodiment of a method for manufacturing stacked lens assemblies for integrated imagers comprises attaching a first lens substrate to a base spacer, fixing an intermediate spacer to the first lens substrate, and mounting a second lens substrate to the intermediate spacer. In a specific embodiment, the first lens substrate can be a component of a first lens unit and the second lens substrate can be a component of a second lens unit. Additionally, the first and second lens substrates can have one or more lens elements, aperture layers and/or filters on the substrates as described above or in other combinations. | 2009-12-31 |
20090321862 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method for fabricating an image sensor, which includes the following steps, is provided. A semiconductor substrate including a sensor array, a pad and a passivation layer is provided, and the passivation layer covers the sensor array and the pad. An opening, which comprises tapered sidewalls not perpendicular to a bared surface of the pad, is formed in the semiconductor substrate to expose the pad. An under layer is formed on the semiconductor substrate, and covers the pad and the passivation layer. A color filter array is formed on the under layer and over the corresponding sensor array. A planar layer is formed on the color filter array. A portion of the under layer is removed to expose the pad. A plurality of U-lenses is formed on the planar layer. | 2009-12-31 |
20090321863 | Method and apparatus providing an imager module with a permanent carrier - Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer. | 2009-12-31 |
20090321864 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SENSOR - A CMOS image sensor manufacturing method may include forming an interlayer insulating film over a semiconductor substrate in which a plurality of photodiodes are formed, forming a plurality of color filter layers corresponding to the photodiodes over the interlayer insulating film, forming a flattening layer over an entire surface of the semiconductor substrate including the respective color filter layers, forming gap insulating films over the flattening layer and over boundaries of the color filter layers, and forming micro-lenses over the flattening layer between the gap insulating films, to correspond to the respective photodiodes. | 2009-12-31 |
20090321865 | SOLID-STATE IMAGING DEVICE AND CAMERA - A solid-state imaging device having a color filter with high color reproducibility even in the case of using lighting of low color temperatures. The solid-state imaging device has a plurality of pixels arranged two-dimensionally, and comprises a color separation filter which allows transmission of light of a predetermined wavelength in incident light for each of the plurality of pixels, wherein the color separation filter includes: a visible-light and near-infrared filter having transmission bands in regions of a visible lo wavelength band and a near-infrared wavelength band; and a near-infrared normalization filter laminated with the visible-light and near-infrared filter, wherein the near-infrared normalization filter is substantially transparent in the visible wavelength band and a first near-infrared wavelength band, and is substantially not transparent in a second near-infrared wavelength band between the visible wavelength band and the first near-infrared wavelength band. | 2009-12-31 |
20090321866 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor of a semiconductor and a method for fabricating the same includes a photodiode; an interlayer dielectric layer formed over the photodiode; a wave guide including an ion implantation layer formed in the interlayer dielectric; a color filter formed over the interlayer dielectric layer; and a micro lens formed over the color filter. | 2009-12-31 |
20090321867 | Method for production of packaged electronic components, and a packaged electronic component - The invention relates to a method for production of packaged electronic, in particular optoelectronic, components in a composite wafer, in which the packaging is carried out by fitting microframe structures of a cover substrate composed of glass, and the composite wafer is broken up along trenches which are produced in the cover substrate, and to packaged electronic components which can be produced using this method, comprising a composite of a mount substrate and a cover substrate, with at least one functional element and at least one bonding element, which makes contact with the functional element, being arranged on the mount substrate, with the cover substrate being a microstructured glass which is arranged on the mount substrate, and forms a cavity above the functional element, and with the bonding elements being located outside the cavity. | 2009-12-31 |
20090321868 | WAVEGUIDE PHOTODETECTOR - A waveguide photodetector detecting light incident on a light detecting end face includes: a substrate; and a layer stack structure on the substrate and including a semiconductor layer of a first conductivity type, an undoped semiconductor layer, and a semiconductor layer of a second conductivity type. The undoped semiconductor layer includes two or more undoped light absorbing layers and undoped non-light-absorbing layers. One non-light-absorbing layer is disposed between adjacent undoped light absorbing layers. The non-light-absorbing layers have a bandgap wavelength shorter than the wavelength of the incident light that is detected. | 2009-12-31 |
20090321869 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device has a structure including the first semiconductor region | 2009-12-31 |
20090321870 | SHUTTLE WAFER AND METHOD OF FABRICATING THE SAME - A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the wafer. After that, a shuttle mask having a number of IC designs is provided. A first IC design corresponds to a first die of each of the shots. A portion of the IC designs on the shuttle mask is covered for exposing the first IC design. Thereafter, the first IC designs of the shuttle mask are transferred onto the material layer, so as to form at least an effective IC pattern on the first die of each of the shots and to form an ineffective IC pattern on each of the other dies of each of the shots. | 2009-12-31 |
20090321871 | Chip Pad Resistant to Antenna Effect and Method - A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC. | 2009-12-31 |
20090321872 | LOW COST SUBSTRATES AND METHOD OF FORMING SUCH SUBSTRATES - In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate. | 2009-12-31 |
20090321873 | LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE - In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates. | 2009-12-31 |
20090321874 | EPITAXIAL WAFER AND PRODUCTION METHOD THEREOF - A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer. | 2009-12-31 |
20090321875 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer. | 2009-12-31 |