52nd week of 2010 patent applcation highlights part 71 |
Patent application number | Title | Published |
20100332776 | COMPUTER SYSTEM REMOTE COPYING SYSTEM AND COMPUTER SYSTEM - When a virtual tape of the main storage system is updated, journal data is created. The journal data is transmitted to the disaster recovery storage system asynchronously with the timing at which the write data is received. The journal data includes a marker to notify of the start of updating and a marker to notify of the completion of updating. The disaster recovery storage system prohibits the use of the copy destination data during the period from start of updating until completion of updating, and permits referencing the copy destination data during other periods. | 2010-12-30 |
20100332777 | DATA BACKUP APPARATUS AND DATA BACKUP METHOD - A data backup apparatus includes a host interface, a first storage medium interface, a second storage medium interface and a controller. The host interface is utilized to be electrically connected with a host, the first storage medium interface is utilized to be electrically connected with a first storage medium, and the second storage medium interface is utilized to be electrically connected with a second storage medium. The controller is coupled to the host interface, the first storage medium interface and the second storage medium interface, and is utilized for copying data from the first storage medium to the second storage medium without passing through the host interface. | 2010-12-30 |
20100332778 | CONTROL UNIT FOR STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE - A storage device includes storage units, a management section that manages a logically defined storage area as a real logical volume by associating the storage area with a physical storage area created using the storage units in advance and manages the logically defined storage area as a virtual logical volume by associating the storage area with a physical storage area when data is added, a determination section that determines whether the activity ratio of the virtual logical volume exceeds a threshold and whether the physical storage area associated with a storage area of the virtual logical volume is managed by another control unit, and a migration section that migrates data stored in the virtual logical volume to a real logical volume when the activity ratio exceeds the threshold and the physical storage area associated with the storage area of the virtual logical volume managed by another control unit. | 2010-12-30 |
20100332779 | STORAGE CONTROL APPARATUS - A method for a storage control apparatus for controlling a plurality of storage units, each of the plurality of storage units having data area for storing data includes receiving a first command for copying data stored in a first data area of the storage units into a second data area of the storage units from an exterior, executing copying in accordance with the first command, receiving a second command for copying data stored in the second data area into the first data area from the exterior, executing copying in accordance with the second command, receiving a third command for cancelling copying corresponding to the first command and a fourth command for cancelling copying corresponding to the second command from the exterior until completion of copying process corresponding to at least one of the first and second command, and invalidating one of the third command and the fourth command. | 2010-12-30 |
20100332780 | STORAGE SYSTEM, CONTROL APPARATUS AND METHOD OF CONTROLLING CONTROL APPARATUS - A storage system has a storage pool for at least one of a logical volume having a plurality of slices, a memory for storing a slice table indicating whether each slices of the logical volume is assigned from the storage pool or not, and a controller for receiving a release command for releasing one of the slices, sending out a response indicating the releasing of one of the slices corresponding to the release command has completed regardless of an execution of processing corresponding to the release command, duplicating a copy target area included in the one of the slices corresponding to the release command into a copy target volume included in the storage pool, and releasing the one of the slices upon completely duplicating the copy target area into the copy target volume. | 2010-12-30 |
20100332781 | Secure Document Processing Using Removable Data Storage - The subject application is directed to a system and method for secure document processing. A removable storage, such as a flash drive, magnetic storage, IC card, is installed in document processing device. A selected document processing operation, such as copying, scanning, and the like, is then performed. Data files resultant from the selected document processing operations are directed to the removable storage for being stored temporary, instead of being sent to the storage inherent to the document processing device. Data files temporary stored in the removable storage are then deleted. | 2010-12-30 |
20100332782 | Virtualization system and area allocation control method - A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation. | 2010-12-30 |
20100332783 | SEMICONDUCTOR DEVICE HAVING MULTI ACCESS LEVEL AND ACCESS CONTROL METHOD THEREOF - An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide. | 2010-12-30 |
20100332784 | STORAGE SYSTEM AND STORAGE SYSTEM DATA MIGRATION METHOD - This storage system modifies the migration plan in accordance with the state of the migration destination when a plurality of volumes are migrated all at once. Migration-source volumes are migrated collectively to volumes inside the migration-destination storage apparatus. The user can make settings related to migration-source volumes and migration-destination volumes in a migration plan, and can establish a mid-process control plan for modifying the migration plan in the middle of processing. If a failure occurs in the migration-destination storage apparatus subsequent to the commencement of data migration processing, a processing method controller either cancels or temporarily halts the data migration processing, or changes the migration destination, on the basis of the mid-process control plan. When changing the migration destination, a previously selected alternate storage apparatus is selected as the new migration-destination storage apparatus. When a failure occurs in the alternate storage apparatus, yet another alternate storage apparatus is selected. | 2010-12-30 |
20100332785 | MEMORY MANAGEMENT SYSTEM AND METHOD THEREOF - A system for managing memory of an electronic device includes a storage unit, a calculation unit, a determination unit, and an allocation unit. The storage unit stores a dynamic allocation list. The calculation calculates a real time usage status of the memory and stores the real time usage status in the storage unit. The determination unit determines whether the electronic device is turned on for the first time. The allocation unit adjusts a partition of the memory according to the dynamic allocation list if the electronic device is not turned on for the first time. | 2010-12-30 |
20100332786 | System and Method to Invalidate Obsolete Address Translations - A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied. | 2010-12-30 |
20100332787 | System and Method to Manage Address Translation Requests - A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush. | 2010-12-30 |
20100332788 | AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION - In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault resulted from a stack access, to create a superpage table entry if the page fault did result from a stack access, and to create a TLB entry for the superpage. Other embodiments are described and claimed. | 2010-12-30 |
20100332789 | Network Use of Virtual Addresses Without Pinning or Registration - A system comprising a compute node and coupled network adapter (NA) that allows the NA to directly use CPU virtual addresses without pinning pages in system memory. The NA performs memory accesses in response to requests from various sources. Each request source is assigned to context. Each context has a descriptor that controls the address translation performed by the NA. When the CPU wants to update translation information it sends a synchronization request to the NA that causes the NA to stop fetching a category of requests associated with the information update. The category may be requests associated with a context or a page address. Once the NA determines that all the fetched requests in the category have completed it notifies the CPU and the CPU performs the information update. Once the update is complete, the CPU clears the synchronization request and the NA starts fetching requests in the category. | 2010-12-30 |
20100332790 | PROCESSOR AND ADDRESS TRANSLATING METHOD - An address translation buffer of a processor including a memory unit that has a first area with first entries storing first address translation pairs of a virtual address and a physical address corresponding to the virtual address, each of the first address translation pairs is subjected to a index tag which is a part of the virtual address, and a second area with second entries storing second address translation pairs, each of the second address translation pairs is subjected to a whole part of the virtual address, and a search unit that searches the first area for an address translation pair by using a index tag included in a virtual address to be translated, and searches the second area for the address translation pair by using a whole part of the virtual address when the address translation pair is not found in the first area. | 2010-12-30 |
20100332791 | SYSTEM, METHOD, AND COMPUTER-READABLE MEDIUM FOR OPTIMIZING PROCESSING OF GROUP-BY QUERIES FEATURING MAXIMUM OR MINIMUM EQUALITY CONDITIONS IN A PARALLEL PROCESSING SYSTEM - A system, method, and computer-readable medium for optimized processing of queries that feature maximum or minimum equality conditions are provided. The disclosed mechanisms provide for a single-scan of the table on which the group-by query is applied. When the table is scanned, each processing module dynamically keeps track of the row(s) having a value of the attribute on which the equality condition is applied that equals or exceeds the maximum attribute value (assuming a maximum equality condition is applied) previously encountered by the processing module. Subsequently, a global aggregation process is then performed to compute the query's result without rescanning the table. Queries featuring a minimum equality condition are similarly processed in accordance with the disclosed embodiments. | 2010-12-30 |
20100332792 | Integrated Vector-Scalar Processor - Systems and methods for improved vector data processing based on separately processing elements of a vector in multiple simultaneously executing vector element processing units are disclosed. One embodiment of the present invention is a vector processing system including a plurality of vector element processing units and a routing infrastructure. The routing infrastructure is configured to route each element of a received vector to a respective one of the vector element processing units. The received vector may be from a memory which is coupled to the vector element processing units by the routing infrastructure. Each vector element processing unit is configured to simultaneously process two or more elements, wherein each of the two or more elements is from a separate vector. Embodiments of the present invention also provide for forwarding of data and results of computation between vector element processing units. | 2010-12-30 |
20100332793 | METHOD FOR SCHEDULING START-UP AND SHUT-DOWN OF MAINFRAME APPLICATIONS USING TOPOGRAPHICAL RELATIONSHIPS - The illustrative embodiments provide for a computer-implemented method for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and columns. Ones of the columns represent corresponding ones of computer applications that can start or stop in parallel with each other in a data processing system. Ones of the rows represent corresponding ones of sequences of actions within a corresponding column. Additionally, the table represents a definition of relationships among memory address spaces, wherein the table represents when each particular address space is started or stopped during one of a start-up process, a recovery process, and a shut-down process. The resulting table is stored. | 2010-12-30 |
20100332794 | UNPACKING PACKED DATA IN MULTIPLE LANES - Receiving an instruction indicating first and second operands. Each of the operands having packed data elements that correspond in respective positions. A first subset of the data elements of the first operand and a first subset of the data elements of the second operand each corresponding to a first lane. A second subset of the data elements of the first operand and a second subset of the data elements of the second operand each corresponding to a second lane. Storing result, in response to instruction, including: (1) in first lane, only lowest order data elements from first subset of first operand interleaved with corresponding lowest order data elements from first subset of second operand; and (2) in second lane, only highest order data elements from second subset of first operand interleaved with corresponding highest order data elements from second subset of second operand. | 2010-12-30 |
20100332795 | COMPUTER SYSTEM INCLUDING RECONFIGURABLE ARITHMETIC DEVICE AND RECONFIGURABLE ARITHMETIC DEVICE - A computer system includes a central processing unit, a random-access-memory interface, a random-access memory in which addresses are allocated in an address space of the random-access-memory interface and a reconfigurable arithmetic device whose arithmetic function is capable of being dynamically changed in accordance with configuration data. The reconfigurable arithmetic device includes input terminals, output terminals, a plurality of processor elements that perform individual arithmetic processes in synchronization with a clock, an inter-processor-element network which connects the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, a random-access memory built into the reconfigurable arithmetic device and a control unit that sets the plurality of processor elements and the inter-processor-element network. | 2010-12-30 |
20100332796 | Method and System for a CPU-Local Storage Mechanism - Described herein are systems and methods for implementing a processor-local (e.g., a CPU-local) storage mechanism. An exemplary system includes a plurality of processors executing an operating system, the operating system including a processor local storage mechanism, wherein each processor accesses data unique to the processor based on the processor local storage mechanism. Each of the plurality of processors of the system may have controlled access to the resource and each of the processors is dedicated to one of a plurality of tasks of an application. The application including the plurality of tasks may be replicated using the processor local storage mechanism, wherein each of the tasks of the replicated application includes an affinity to one of the plurality of processors. | 2010-12-30 |
20100332797 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND PROGRAM - An information processing apparatus includes a first processing unit, a second processing unit which is different from the first processing unit, a supply unit configured to supply a clock to the first processing unit and the second processing unit, and a control unit configured to control the supply unit in such a manner as to stop a supply of the clock to the second processing unit in response to completion of activation of the second processing unit, and to resume the supply of the clock to the second processing unit in response to completion of activation of the first processing unit. | 2010-12-30 |
20100332798 | Digital Processor and Method - A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator. | 2010-12-30 |
20100332799 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - According to an aspect of the present invention, there is provided an information processing apparatus including: a first processor; a second processor that has an information processing capability and a power consumption higher than those of the first processor; a temperature monitoring module configured to acquire an operating temperature of the second processor; and a processor switching control module configured to perform, when the operating temperature of the second processor is equal to or higher than a given temperature: stopping an operation of the second processor; causing the first processor to perform an information process; and prohibiting the operation of the second processor. | 2010-12-30 |
20100332800 | Instruction control device, instruction control method, and processor - An instruction control device connects to a cache memory that stores data frequently used among data stored in a main memory. The instruction control device includes: a first free-space determining unit that determines whether there is free space in an instruction buffer; a second free-space determining unit that manages an instruction fetch request queue that stores an instruction fetch data to be sent from the cache memory to the main memory, and determines whether a move-in buffer in the cache memory has free space for at least two entries if the first free-space determining unit determines that there is free space; and an instruction control unit that outputs an instruction prefetch request to the cache memory in accordance with an address boundary corresponding to a line size of the cache line, if the second free-space determining unit determines that the move-in buffer has free space. | 2010-12-30 |
20100332801 | Adaptively Handling Remote Atomic Execution - In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed. | 2010-12-30 |
20100332802 | Priority circuit, processor, and processing method - A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station. | 2010-12-30 |
20100332803 | PROCESSOR AND CONTROL METHOD FOR PROCESSOR - A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction after two instructions written to the second area respectively, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit. | 2010-12-30 |
20100332804 | UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPECULATIVE INSTRUCTIONS - Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields. | 2010-12-30 |
20100332805 | Remapping source Registers to aid instruction scheduling within a processor - An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard. | 2010-12-30 |
20100332806 | DEPENDENCY MATRIX FOR THE DETERMINATION OF LOAD DEPENDENCIES - Systems and methods for identification of dependent instructions on speculative load operations in a processor. A processor allocates entries of a unified pick queue for decoded and renamed instructions. Each entry of a corresponding dependency matrix is configured to store a dependency bit for each other instruction in the pick queue. The processor speculates that loads will hit in the data cache, hit in the TLB and not have a read after write (RAW) hazard. For each unresolved load, the pick queue tracks dependent instructions via dependency vectors based upon the dependency matrix. If a load speculation is found to be incorrect, dependent instructions in the pick queue are reset to allow for subsequent picking, and dependent instructions in flight are canceled. On completion of a load miss, dependent operations are re-issued. On resolution of a TLB miss or RAW hazard, the original load is replayed and dependent operations are issued again from the pick queue. | 2010-12-30 |
20100332807 | PERFORMING ESCAPE ACTIONS IN TRANSACTIONS - Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction. | 2010-12-30 |
20100332808 | MINIMIZING CODE DUPLICATION IN AN UNBOUNDED TRANSACTIONAL MEMORY SYSTEM - Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes. | 2010-12-30 |
20100332809 | Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor - Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state. | 2010-12-30 |
20100332810 | Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions - A functional unit is described. The functional unit includes a reconfigurable logic circuitry and instruction context storage circuitry to store instruction context information generated from instructions executed by the reconfigurable logic circuitry within the reconfigurable functional unit. The instructions include speculatively executed instructions. | 2010-12-30 |
20100332811 | SPECULATIVE MULTI-THREADING FOR INSTRUCTION PREFETCH AND/OR TRACE PRE-BUILD - The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread. | 2010-12-30 |
20100332812 | METHOD, SYSTEM AND COMPUTER-ACCESSIBLE MEDIUM FOR LOW-POWER BRANCH PREDICTION - Examples of a method, system, and computer-accessible medium are provided which can utilize a neural branch predictor on, e.g., an analog circuit. For example, a current summation can be used instead of the digital dot-product generally used in traditional neural predictor designs. A scaling factor may also be used to increase prediction accuracy. | 2010-12-30 |
20100332813 | SYSTEM AND METHOD FOR UTILIZING A PROTECTED/HIDDEN REGION OF SEMICONDUCTOR BASED MEMORY/STORAGE - A method for accessing a protected area of a solid-state storage device via firmware control is described. During system initialization, firmware components are loaded and executed to initialize a computer system. These firmware components include a firmware driver for accessing solid-state storage devices connected to the computer system. The system firmware enables a protected area on a solid-state storage device's media to be accessed under firmware control. After firmware accesses, the protected area is closed from access by non-firmware entities by “hiding” the true size of the media such that those entities are unaware of this area of the media. Mechanisms are disclosed for providing firmware access to the protected area only during pre-boot, and for both pre-boot and run-time operations. The firmware-controlled media access scheme may be used to load firmware stored on solid-state media during pre-boot and to store system information in the protected area during pre-boot and/or run-time operations. | 2010-12-30 |
20100332814 | PORTABLE LIGHT WEIGHT LDAP DIRECTORY SERVER AND DATABASE - A lightweight embedded directory server with portable LDAP data is disclosed. The directory server and database comprises a processing chip, an on-chip processing unit, an on-chip memory system, and an on chip input/output system. The memory system stores an embedded operating system and an embedded directory server, and is also used for storing data to be processed by the processing unit. The input/output system is provided for connecting the processor chip to one or more applications for supplying directory services to the one or more applications. A portable memory device stores a directory database, and, in use, this memory device is releasably connected to the on chip input/output system. An on-chip driver is used to perform read and write operations on the portable memory device; and a boot loader software program is used for starting execution of the embedded directory service. | 2010-12-30 |
20100332815 | PERIPHERAL CONTROL MODULE, COMPUTER SYSTEM, AND OPERATION METHOD THEREOF - This invention provides a peripheral control module, a computer system, and an operation method thereof. The peripheral control module is for a computer system. The computer system includes a power switch capable of outputting a power signal. The peripheral control module includes a control unit and a control circuit. The control unit has a program code for controlling a peripheral module. The control circuit is coupled with the power switch and the control unit for receiving the power signal and outputting a switching signal to the control unit, and the control circuit resets the program code to an initial state before the control unit receives the switching signal. This invention further provides a computer system using the peripheral control module and an operation method thereof. | 2010-12-30 |
20100332816 | RESILIENCY AGAINST FIELD-UPDATED SECURITY ELEMENTS - User terminal resilience to application elements may be provided. Upon initialization, a user terminal may detect elements associated with the user terminal's operation. The user terminal may load each of the elements in turn and determine whether the element causes a fault in the user terminal. Elements that result in a fault may be disabled from being loaded in the future. | 2010-12-30 |
20100332817 | CONTENT RECORDING SYSTEM, CONTENT RECORDING METHOD, CONTENT RECORDING DEVICE, AND CONTENT RECEVING DEVICE - Provided is a content receiving device, connected to a content recording device that records content data, including a receiving section that receives the content data, a recording folder specifying section that specifies a dedicated folder as a recording destination of the content data when a parental level is set on the content data and an normal folder as the recording destination of the content data when no parental level is set on the content data, and a transmitting section that transmits the content data so that the content data is recorded in a folder specified by the recording folder specifying section of a storage medium contained in the content recording device. | 2010-12-30 |
20100332818 | CLOUD STORAGE AND NETWORKING AGENTS, INCLUDING AGENTS FOR UTILIZING MULTIPLE, DIFFERENT CLOUD STORAGE SITES - Systems and methods are disclosed for performing data storage operations, including content-indexing, containerized deduplication, and policy-driven storage, within a cloud environment. The systems support a variety of clients and cloud storage sites that may connect to the system in a cloud environment that requires data transfer over wide area networks, such as the Internet, which may have appreciable latency and/or packet loss, using various network protocols, including HTTP and FTP. Methods are disclosed for content indexing data stored within a cloud environment to facilitate later searching, including collaborative searching. Methods are also disclosed for performing containerized deduplication to reduce the strain on a system namespace, effectuate cost savings, etc. Methods are disclosed for identifying suitable storage locations, including suitable cloud storage sites, for data files subject to a storage policy. Further, systems and methods for providing a cloud gateway and a scalable data object store within a cloud environment are disclosed, along with other features. | 2010-12-30 |
20100332819 | DIGITAL CONTENT ACCESS CONTROL - Control of access to at least one digital content is managed as a function of at least one access criterion. The digital content is transmitted to at least one terminal in the form a data stream. The access criterion is stored in the terminal as a function of an identifier. The terminal receives the data stream in association with a control message indicating the identifier. It then retrieves the stored access criterion as a function of the identifier received in the control message. Finally, it verifies whether the stored access criterion is satisfied in order, where appropriate, to authorize access to the content. | 2010-12-30 |
20100332820 | INFORMATION SECURITY DEVICE AND INFORMATION SECURITY SYSTEM - The present invention provides a migration apparatus that realizes safe migration of data between devise that use different encryption algorithms and different security authentication levels. The fourth electronic terminal device | 2010-12-30 |
20100332821 | Mobile IP Over VPN Communication Protocol - The present invention supports a communication protocol for transmission of information packets between a mobile node and a virtual private network. Information packets are encapsulated and decapsulated along the route as the information packet is forwarded among the various networks on its path to the destination address; either the mobile node on a foreign network or a correspondence node on a virtual private network. A home agent on the virtual private network supports transmitting the information packets, and the information packets are transmitted from the virtual private network from the home agent or a virtual private network gateway. | 2010-12-30 |
20100332822 | WIRELESS MULTIBAND SECURITY - A network device includes a first physical layer (PHY) module, a second physical layer (PHY) module, and a security module. The first PHY module is configured to operate in a first frequency band. The second PHY module is configured to operate in a second frequency band. The security module is configured to establish security for the first frequency band responsive to the network device operating in the first frequency band. The security module is further configured to establish security for the second frequency band prior to the network device switching operation from the first frequency band to the second frequency band. | 2010-12-30 |
20100332823 | MULTI-FUNCTIONAL PERIPHERAL, AUTHENTICATION SERVER AND SYSTEM - In a multi-functional peripheral capable of performing user authentication processing in cooperation with an authentication server and processing in cooperation with an external application, a user is able to easily access a screen of a previously used function immediately after logging in without necessity of switching a screen of the function of the multi-functional peripheral itself and a screen of the external application function. | 2010-12-30 |
20100332824 | SYSTEM AND METHOD OF MOBILE LIGHTWEIGHT CRYPTOGRAPHIC DIRECTORY ACCESS - A system for handling an LDAP service request to an LDAP server for an LDAP service comprises a client program executable on a client system and a handler program executable on a handler system. The client program is operable to generate LDAP service request data corresponding to the LDAP service and provide the LDAP service request data for transmission from the client system, and further operable to receive LDAP service reply data in response to the LDAP service request data. The handler program is operable to receive the LDAP service request data transmitted from the client system and execute the LDAP service request to the LDAP server, receive LDAP service reply data from the LDAP server during one or more passes, and upon completion of the LDAP service, provide the LDAP service reply data for transmission to the client system in a single pass. | 2010-12-30 |
20100332825 | System and Method for Dynamic Multi-Attribute Authentication - In accordance with the teachings of the present invention, a system and method for dynamic, multi-attribute authentication are provided. In a particular embodiment, a method for authentication includes receiving, at an authentication web server, an authentication request comprising a workstation message and a user message, wherein the workstation message comprises a workstation object and a workstation signature, the workstation object comprises a workstation certificate associated with a workstation, the user message comprises a user object and a user signature, and the user object comprises a copy of the workstation message and a user certificate associated with a user of the workstation. The method further includes verifying the workstation signature and user signature, validating the workstation certificate and the user certificate, retrieving one or more caveats associated with the workstation and one or more caveats associated with the user, and determining one or more caveats associated with both the workstation and the user. | 2010-12-30 |
20100332826 | Memory Device and Method for Updating a Security Module - A memory device and method for updating a security module are disclosed. In one embodiment, a memory device is provided comprising a memory operative to store content and a controller in communication with the memory. The controller is configured to send an identification of the memory device's security module to a host and receive an identification of the host's security module. If the memory device's security module is out-of-date with respect to the host's security module, the memory device receives a security module update from the host. If the host's security module is out-of-date with respect to the memory device's security module, the memory device sends a security module update to the host. | 2010-12-30 |
20100332827 | CREATING AND USING SECURE COMMUNICATIONS CHANNELS FOR VIRTUAL UNIVERSES - A system and method provides secure channels for communication in a virtual universe by employing a packet interception layer for incoming and outgoing data packets. A data path is defined and is sequentially encrypted with the public keys of servers in the path. Decryption and identification of the next server occurs in a sequential manner in which the path is known only to the sender. | 2010-12-30 |
20100332828 | APPARATUS AND METHOD FOR SHARING OF AN ENCRYPTION KEY IN AN AD-HOC NETWORK - It is so arranged that an encryption key can be shared with a communication apparatus that participates in a network anew, even in an ad-hoc-mode type of environment. In order to achieve this, a communication apparatus determines whether it possesses an encryption key shared with another communication apparatus and, in accordance with the result of the determination, initiates sharing process for sharing the encryption key with a first communication apparatus from the communication apparatus after the sharing process for sharing the encryption key has been initiated from the first communication apparatus. | 2010-12-30 |
20100332829 | Method for detecting the use of a cloned user unit communicating with a server - A method to prevent, detect and fight against cloning attacks by using payload keys to encrypt request and response messages exchanged between user units and server. In an initialization phase, the user unit generates locally an initial payload key and sends to the server in a secure way a request comprising a unique identifier of the user unit, check data, the initial payload key and a request instruction encrypted with a payload key retrieved from the memory of the user unit. Each time the server receives a request from a user unit; it will retrieve the payload key by searching in its memory according to the unique identifier of the user unit. The obtained payload key is then used to decrypt the request instruction. The server then generates a derivation key as response key which will be used by the user unit to compute a new payload key. Doing this way, the payload key is modified preferably during each data exchange between user unit and server, allowing thus the server to check in the next incoming request from the same user unit if the payload key is the expected one. The server also stores a fallback payload key, which is the last one used by the user unit. By checking a status parameter at decryption with the expected payload key or with the fallback key, the server can, by applying predefined business rules, distinguish correct behaviors or authorized user units from unexpected system failures (network, storage, interferences, application software crash, etc.) and from true cloning attacks. | 2010-12-30 |
20100332830 | SYSTEM AND METHOD FOR MUTUAL AUTHENTICATION BETWEEN NODE AND SINK IN SENSOR NETWORK - Disclosed a system and method for mutual authentication between a node and a sink in a sensor network. At least one sink periodically creates a neighboring sink list including information on at least one adjacent sink, and the sink requests node authentication to a base station when receiving an authentication request from the node and transmits its own neighboring sink list to the node when the node authentication has been completed. When the node moves and requests authentication to another sink, the another sink stores a neighboring sink list received from the node, determines if a node-authenticable sink exists in its own neighboring sink list according to the authentication request, and requests re-authentication of the node to the node-authenticable sink when the node-authenticable sink exists, so that re-authentication between the node and the sink is easily performed. | 2010-12-30 |
20100332831 | METHOD AND APPARATUS FOR AUTHENTICATING A SENSOR NODE IN A SENSOR NETWORK - A method and apparatus for authenticating a sensor node in a sensor network. The method for authenticating a sensor node by a first sink node in a sensor network includes receiving an authentication request using an authentication ticket from the sensor node, identifying a second sink node which has issued the authentication ticket, decoding the authentication ticket using a group key, which is previously stored in correspondence to the second sink node to confirm the validity of the authentication ticket, when the second sink node is included in a neighboring node list, normally processing authentication for the sensor node, generating an authentication ticket using a group key of the first sink node, and transmitting the generated authentication ticket to the sensor node. | 2010-12-30 |
20100332832 | TWO-FACTOR AUTHENTICATION METHOD AND SYSTEM FOR SECURING ONLINE TRANSACTIONS - A two-factor authentication system is provided for securing online transactions. In the two-factor authentication system, a transaction server provides online transaction services. A mobile communication device receives short messages. A client computing device applies a first authentication function to communicate with the transaction server, receives, via short messages, a first authentication code used to authenticate the transaction server, and applies a second authentication function to generate a second authentication code. Next, the transaction server authenticates the client computing device with the second authentication function and second authentication code. | 2010-12-30 |
20100332833 | LINK KEY INJECTION MECHANISM FOR PERSONAL AREA NETWORKS - According to one embodiment, a method is disclosed. The method includes generating a link key at a secure component within a first personal area network device and injecting the link key into a protocol stack component database within the first device. The link key may further be transmitted to a second device. Other embodiments are described and claimed. | 2010-12-30 |
20100332834 | METHOD AND APPARATUS FOR PROVIDING A SCALABLE SERVICE PLATFORM USING A NETWORK CACHE - An approach is provided for building a scalable service platform by initiating transmission of encrypted data from a public network cache. An access control server platform determines a first authorization key for a user and a second authorization key for a resource, and then encrypts the resource with the second authorization key, and encrypts the second authorization key with the first authorization key. The access control server platform initiates distribution of the encrypted second authorization key with the encrypted resource over a network. The access control server platform further initiates caching the encrypted second authorization key with the encrypted resource that meets a predefined threshold value (e.g., a data size, an access frequency, a modification frequency, or an auditing requirement) in a cache in the network, and initiates transmission of the cached and encrypted second authorization key with the cached and encrypted resource from the cache to at least one authorized entity. | 2010-12-30 |
20100332835 | METHOD AND SYSTEM FOR SECURE COMMUNICATION BETWEEN COMPUTERS - Method, system and computer program for exchanging data between a client computer and a storage device are described, in which the storage device may send a long-term DH-component to an intermediate server. The client computer may send a first short-term DH-component to the storage device through the intermediate server that adds a communication expiration time. The storage device may send a second short-term DH-component to the client computer. The client computer and the storage device may calculate a symmetric key from the long-term component and from both short-term DH-components to exchange data and may delete the short-term DH-components upon reaching the expiration time. | 2010-12-30 |
20100332836 | METHOD AND APPARATUS FOR RECOVERING SESSIONS - A method for recovering sessions includes storing, by a client, session information after a session is established between the server and the client. When the session needs to be recovered upon interruption, the client sends all state information before interruption of the session and the session information to the server, and the server recovers the session upon the received session information and all state information before interruption of the session. After a session is interrupted, the server does not need to store any session-related information, thus saving the resources of the server, and all information about the previous session can be recovered completely. | 2010-12-30 |
20100332837 | WEB APPLICATION SECURITY FILTERING - User inputs and/or Uniform Resource Identifier (URI), historically and popularly referred to as Universal Resource Locator (URL), requests in a content description language are passed through a security service (Web application firewall or a reverse Web proxy server) that is placed in front of Web application servers in order to protect the servers from hacking attempts. For validating Webform user inputs and/or URI requests and parameters the content description language is enriched by the security service with additional security tokens that are dynamically created based on the content being transferred. The user receives the information and returns input with the security tokens. The security service can then verify all provided user input data against the constraints described in the corresponding security token. As a result, the method may block the HTTP request or create log messages or notification events in reaction to violations of the user input data compared to the constraints in the security token. | 2010-12-30 |
20100332838 | SYSTEMS AND METHODS FOR AUTHENTICATING AND PROVIDING ANTI-COUNTERFEITING FEATURES FOR IMPORTANT DOCUMENTS - A method for authenticating a document comprises obtaining the contents of a document, obtaining biometric characteristics from an individual, forming a message based on the contents of the document and the biometric characteristics of the individual, generating a digital signature based on the message and a key, and writing the digital signature to an Radio Frequency Identification (RFID) tag affixed to the document. | 2010-12-30 |
20100332839 | METHOD AND SYSTEM FOR THE SUPPLY OF DATA, TRANSACTIONS AND ELECTRONIC VOTING - A method and system for supply of data, including generating a first digital certificate referred (empowerment certificate) signed with a first signing entity's electronic signature. The empowerment certificate includes attributes of the described entity, information identifying the first signing entity, indication of data relating to the described entity, indication of a source of the data, and identification of a relying entity to which the data can be supplied. The relying entity forwards the empowerment certificate to a source supplying the data indicated in the empowerment certificate. The data may be supplied to the relying entity by a second digital certificate (custom certificate), signed with a second signing entity's electronic signature. Custom certificates may appear in custom certificate revocation lists. A system and method for transfer of ownership of electronic property from a first entity to a second entity, and a method and system for electronic voting are also provided. | 2010-12-30 |
20100332840 | Systems and Methods for Electronic Postmarking of Data Including Location Data - Systems and methods for electronic postmarking of location data are provided. Electronic postmarking of location data (S. | 2010-12-30 |
20100332841 | Authentication Method and System - Disclosed are methods related to controlling user access to a first computer device, using a second computer device. One method comprises generating authentication data in accordance with a first algorithm and generating acceptable response data in accordance with a second algorithm using the authentication data and information shared with a second computer device. The authentication data is received at the second computer device, where response data is generated in accordance with the second algorithm using the shared information and the received authentication data. The response data generated by the second device is received at the first computer device and compared with the acceptable response data. Access to the first computer device is granted if the response data is identical to the acceptable response data. | 2010-12-30 |
20100332842 | DETERMINING A MOOD OF A USER BASED ON BIOMETRIC CHARACTERISTIC(S) OF THE USER IN AN ONLINE SYSTEM - Techniques are described herein that enable a determination of a user's mood based on biometric characteristic(s) of the user in an online system. An online system is a system that supports the transfer of information via the Internet. The mood of the user at a time instance (i.e., a mood instance) is determined based on the biometric characteristic(s) of the user and a substantially real-time instance(s) associated with the user. A substantially real-time instance associated with the user is any occurrence with respect to the user that is determined in substantially real-time. The mood instance of the user and the substantially real-time instance that is associated with the user may (or may not) occur at the same time instance. Online content may be provided to the user and/or action(s) may be recommended to the user in response to determining the mood instance of the user. | 2010-12-30 |
20100332843 | SUPPORT FOR SECURE OBJECTS IN A COMPUTER SYSTEM - A method and structure in a computer system, including a mechanism supporting a Secure Object that includes code and data that is cryptographically protected from other software on the computer system. | 2010-12-30 |
20100332844 | MAGNETIC DISK DEVICE AND COMMAND EXECUTION METHOD FOR MAGNETIC DISK DEVICE - According to one embodiment, a magnetic disk device includes a receiver, an encrypting-and-decrypting module, a read-and-write controller, a setting module, an order controller, an executing module. The receiver receives a command to write data to or read data from a recording medium segmented into a plurality of storage areas each corresponding to an encryption key. The command causes an access to at least one of the storage areas. The encrypting-and-decrypting module encrypts the data or decrypts the data using the encryption key. The read-and-write controller controls writing the data to the recording medium and reading data therefrom. The setting module sets the encryption key corresponding to the storage area accessed by the command to the encrypting-and-decrypting module. The order controller controls the execution order in which commands are executed and brings up the execution order of the command causing an access to the storage area. The executing module executes the commands in the execution order. | 2010-12-30 |
20100332845 | INFORMATION PROCESSING SERVER, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD - Methods and apparatuses for selectively performing at least one of encryption or decryption of data and for requesting a process. An information processing server includes a communication unit configured to receive from an information processing apparatus a processing request and a cryptographic key, and includes first and second storage units configured to temporarily store the received cryptographic key and to store data. The information processing server also includes a process determining unit configured to determine a type of process requested based on the processing request, and an encryption processing unit configured to selectively perform, based on the determined type of process requested, at least one of encryption or decryption on the stored data using the cryptographic key. The cryptographic key temporarily stored in the first storage unit is deleted after the at least one of encryption or decryption on the stored data has been selectively performed. | 2010-12-30 |
20100332846 | SCALABLE INDEXING - Method and apparatus for constructing an index that scales to a large number of records and provides a high transaction rate. New data structures and methods are provided to ensure that an indexing algorithm performs in a way that is natural (efficient) to the algorithm, while a non-uniform access memory device sees IO (input/output) traffic that is efficient for the memory device. One data structure, a translation table, is created that maps logical buckets as viewed by the indexing algorithm to physical buckets on the memory device. This mapping is such that write performance to non-uniform access SSD and flash devices is enhanced. Another data structure, an associative cache is used to collect buckets and write them out sequentially to the memory device as large sequential writes. Methods are used to populate the cache with buckets (of records) that are required by the indexing algorithm. Additional buckets may be read from the memory device to cache during a demand read, or by a scavenging process, to facilitate the generation of free erase blocks. | 2010-12-30 |
20100332847 | ENCRYPTING PORTABLE MEDIA SYSTEM AND METHOD OF OPERATION THEREOF - A portable media system for a host computer system, and method of operation thereof, that includes: a controller in the portable media system for communicating clear information between the portable media system and the host computer system; and an encryption system in the portable media system for providing an encryption algorithm for the controller to decrypt cipher information for the host computer system. | 2010-12-30 |
20100332848 | SYSTEM AND METHOD FOR CODE SIGNING - A system and method for code signing. The entities may be software application developers or other individuals or entities that wish to have applications digitally signed. Signing of the applications may be required in order to enable the applications to access sensitive APIs and associated resources of a computing device when the applications are executed on the computing device. | 2010-12-30 |
20100332849 | INFORMATION PROCESSING APPARATUS, INFORMATION RECORDING MEDIUM MANUFACTURING APPARATUS, INFORMATION RECORDING MEDIUM, INFORMATION PROCESSING METHOD, INFORMATION RECORDING MEDIUM MANUFACTURING METHOD, AND COMPUTER PROGRAM - An information processing apparatus includes: a data processing unit that acquires content codes including a data processing program recorded in an information recording medium and executes data processing according to the content codes; and a memory that stores an apparatus certificate including an apparatus identifier of the information processing apparatus. The data processing unit is configured to execute an apparatus checking process applying the apparatus certificate stored in the memory on the basis of a code for apparatus checking process included in the content codes, acquire the apparatus identifier recorded in the apparatus certificate after the apparatus checking process, and execute data processing applying content codes corresponding to the acquired apparatus identifier. | 2010-12-30 |
20100332850 | CACHE STRUCTURE FOR A COMPUTER SYSTEM PROVIDING SUPPORT FOR SECURE OBJECTS - A method (and structure) of enhancing efficiency in processing using a secure environment on a computer, includes, for each line of a cache, providing an associated object identification label field associated with the line of cache, the object identification label field storing a value that identifies an owner of data currently stored in the line of cache. | 2010-12-30 |
20100332851 | METHOD FOR PROTECTING A CRYPTOGRAPHIC MODULE AND A DEVICE HAVING CRYPTOGRAPHIC MODULE PROTECTION CAPABILITIES - A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions. | 2010-12-30 |
20100332852 | Creating Secure Communication Channels Between Processing Elements - Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one processing element. A first processing element, such as a bridge, may use its cryptographic functionality to request a key exchange with a second processing element, such as a graphics engine. Each processing element may include a global key which is common to the two processing elements and a unique key which is unique to each processing element. A key exchange may be established during the boot process the first time the system boots and, failing any hardware change, the same key may be used throughout the lifetime of the two processing elements. Once a secure channel is set up, any application wishing to authenticate a processing element without public-private cryptographic function may perform the authentication with the other processing element which shares a secure channel with the first processing element. | 2010-12-30 |
20100332853 | NETWORK TRANSMISSION METHOD, NETWORK TRANSMISSION SYSTEM AND NETWORK TRANSMISSION DEVICE THEREOF - The present invention discloses a network transmission system, network transmission method, and network transmission device thereof. The network transmission device is connected to an operating center and a user device, and comprises at least one storage device. The operating center is capable of transmitting data to the network transmission device and storing the data in the storage device. Moreover, the operating center is able to control the network transmission device to transmit the data stored in the storage device to the user device | 2010-12-30 |
20100332854 | STORAGE DEVICE, METHOD OF CONTROLLING STORAGE DEVICE, AND COMPUTER PROGRAM PRODUCT - A storage device with an authentication feature providing enhanced convenience during locking. The device is a USB hard disk designed for connection to a personal computer, and includes a disk, an access controller, and a push-button. The access controller includes an encryption/decryption module | 2010-12-30 |
20100332855 | Method and Memory Device for Performing an Operation on Data - A method and memory device for implementing long operations and supporting multiple streams are provided. In one embodiment, a memory device receives data and a command from a host to perform an operation on the data, wherein a time required for the memory device to complete the operation exceeds a maximum response time for the memory device to respond to the command. The memory device begins performing the operation on the data and, before exceeding the maximum response time and before completing the operation, sends the context of the operation to the host. At a later time, the memory device receives from the host: (i) a command to resume performing the operation and (ii) the context. The memory device then resumes performing the operation on the data based on the context received from the host. | 2010-12-30 |
20100332856 | System and method for processor utilization adjustment to improve deep C-state use - In some embodiments, the invention involves modification of the processor utilization calculations that are used by operating system power management services to improve processor efficiency. An embodiment of the present invention is a system and method relating to power management policies under operating system control. In at least one embodiment, the present invention is intended to modify the processor utilization evaluation process so that C-state transition time and/or unhalted reference cycles are included in the calculation. Other embodiments are described and claimed. | 2010-12-30 |
20100332857 | Reducing power losses in a redundant power supply system - A power supply system includes at least a first power supply module and at least one redundant power supply module. The at least one power supply module supplies power to an output terminal. The at least one redundant power supply module operates in a first state and in a second state. In the first state the second power supply module supplies power to the output terminal. In the second state the second power supply module provides standby power and operates in a burst mode (for example, such as a discontinuous conduction mode). | 2010-12-30 |
20100332858 | SYSTEMS, METHODS AND DEVICES FOR REGULATION OR ISOLATION OF BACKUP POWER IN MEMORY DEVICES - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data-storage device is implemented having a memory control circuit controlling non-volatile and volatile memory. An operating power circuit carries primary-operating power from the host-system to the memories and control circuitry. A backup power circuit includes energy-storage circuitry with one or more energy storage devices. An isolation-regulation circuit provides voltage regulation of power from the host-system and also isolates the host-system provided power from the energy storage devices. A regulation power circuit carries the regulated power from the isolation-regulation circuit to the energy storage devices. | 2010-12-30 |
20100332859 | SYSTEMS, METHODS AND DEVICES FOR CONTROL AND GENERATION OF PROGRAMMING VOLTAGES FOR SOLID-STATE DATA MEMORY DEVICES - In one embodiment, a solid-state drive contains a plurality of data memory devices requiring elevated voltages for erasure and programming operations. A common voltage regulator, external to the data memory devices, provides the elevated voltage, thereby reducing the overall power consumption of the data storage device. | 2010-12-30 |
20100332860 | SYSTEMS, METHODS AND DEVICES FOR CONFIGURABLE POWER CONTROL WITH STORAGE DEVICES - Power is routed from one or more power supplies. As consistent with one or more example embodiments, a data storage device senses and/or is informed of the availability and voltage level of one or more power supplies. Based upon the availability and voltage level of power supplies, circuits in the memory device are powered using one or more of the sensed power supplies. In some applications, the power is drawn in a manner that emulates the behavior of one or more circuits that are respectively powered. | 2010-12-30 |
20100332861 | MANAGING POWER COMSUMPTION IN A DATA STORAGE SYSTEM - A method for managing power consumption in a data storage system is provided. The method comprises receiving a first input/output (I/O) request identifying an I/O operation to be performed by a storage device; delaying scheduling of the first I/O request to manage amount of power consumed by servicing the first I/O request; and forwarding the first I/O request to a storage controller associated with the storage device. The storage controller schedules the first I/O request using a scheduling mechanism, and the storage device services the first I/O request according to the scheduling mechanism. | 2010-12-30 |
20100332862 | SYSTEMS, METHODS AND DEVICES FOR POWER CONTROL IN MEMORY DEVICES STORING SENSITIVE DATA - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a memory device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A circuit carries primary operating power to the memory device. A backup power circuit has a power module having and securing a power-reservoir circuit. A capacitor holds a charge to provide operating power to the memory circuits to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit. A notification circuit provides an external user indication of the power-reservoir circuit integrity. A circuit-based structure secures the power-reservoir circuit for operation as part of the memory device and facilitates replacement of the power-reservoir circuit. | 2010-12-30 |
20100332863 | SYSTEMS, METHODS AND DEVICES FOR POWER CONTROL IN MASS STORAGE DEVICES - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage device such as a capacitive storage circuit is powered relative to the powering of one or more additional circuits from a common power supply to limit the draw upon the power supply. Certain applications involve delaying or otherwise modifying the powering of the capacitive storage circuit, which may involve an initial startup of the capacitive storage circuit. | 2010-12-30 |
20100332864 | POWER SUPPLY UNIT, PROCESSING SYSTEM, AND CONTROL METHOD - A power supply unit includes a communication unit and a control unit. The communication unit is capable of communicating with a different power supply unit. The control unit determines a number of processing units connected thereto, controls powers of the processing units connected thereto so that one of a turn-on operation and a turn-off operation is performed on the powers of the processing units in sequence, and controls the powers of the processing units connected thereto so that one of the turn-on operation and the turn-off operation is performed on the powers in a predetermined priority order in a relationship with processing units connected to the different power supply unit through communication with the different power supply unit. | 2010-12-30 |
20100332865 | PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION - A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10 | 2010-12-30 |
20100332866 | METHOD AND SYSTEM FOR OPTIMIZING POWER CONSUMPTION IN A MOBILE ENVIRONMENT - The present invention relates to a system and method adapted to optimize power consumption in a communication system used in a Gigabit Ethernet environment. The method comprises determining at least one power mode of a host from a plurality of possible host power modes. The method further comprises selecting at least one network interface power management state from a plurality of possible network interface power management states based, at least in part, on the determined power mode. | 2010-12-30 |
20100332867 | Wireless Communication Terminal and Control Method Thereof - In a PC card communication terminal that operates supplied with power from a host device, problems such as malfunctions due to a supply voltage drop at the time of high transmission output are prevented from occurring. A baseband processor ( | 2010-12-30 |
20100332868 | SQUELCH FILTRATION TO LIMIT FALSE WAKEUPS - Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed. | 2010-12-30 |
20100332869 | Method and apparatus for performing energy-efficient network packet processing in a multi processor core system - A method and apparatus for managing core affinity for network packet processing is provided. Low-power idle state of a plurality of processing units in a system including the plurality of processing units is monitored. Network packet processing is dynamically reassigned to processing units that are in a non-low power idle state to increase the low-power idle state residency for processing units that are in a low-power idle state resulting in reduced energy consumption. | 2010-12-30 |
20100332870 | ELECTRONIC DEVICE FOR REDUCING POWER CONSUMPTION OF COMPUTER MOTHERBOARD AND MOTHERBOARD THEREOF - An electronic device for reducing power consumption of a computer motherboard is disclosed. The electronic device enables the computer motherboard to compel interruption of power supply to a south bridge chip and a super input output (SIO) chip of the computer motherboard so as to save power while the computer motherboard is waiting for receipt of a Wake-on-LAN packet. A network chip of the computer motherboard sends a signal to the power-saving electronic device as soon as a Wake-on-LAN event occurs, such that a standby power is electrically connected to the south bridge chip and the SIO chip by the electronic device. The computer motherboard equipped with the electronic device is capable of executing Wake-on-LAN function while compelling interruption of power supply to the south bridge chip and the SIO chip in a power-saving state. | 2010-12-30 |
20100332871 | CAPPING POWER CONSUMPTION IN A DATA STORAGE SYSTEM - A method for capping power consumption in a data storage system is provided. The method comprises associating a power quota with a first storage medium, wherein the power quota limits amount of power consumed by the first storage medium within a given time interval; receiving a request to perform an input/output (I/O) operation on the first storage medium; and servicing the request within power limits defined by the power quota. | 2010-12-30 |
20100332872 | Priority-Based Power Capping in Data Processing Systems - A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system. | 2010-12-30 |
20100332873 | Power Supply Engagement and Method Therefor - An information handling system includes a plurality of power supply units (PSUs) to supply power to one or more system components. For each PSU of the plurality of PSUs, a power conversion efficiency profile for the PSU is determined using a power management control module of the information handling system. The power conversion efficiency profile represents a power conversion efficiency of the PSU for each of one or more power outputs capable of being supplied by the PSU. The power management control module determines a total amount of power to be supplied to a load of the information handling system, and engages a select number of PSUs to provide the total amount of power based on the total amount of power and the power conversion efficiency profiles of the PSUs. | 2010-12-30 |
20100332874 | MICROCOMPUTER AND MICROCOMPUTER SYSTEM - A microcomputer includes a CPU, a standby controller that controls setting of and recovering from a sleep mode of the CPU, an output terminal, a first timer, an output terminal controller, and a second timer. When the first timer performs predetermined time measurement when the CPU is in the sleep mode, the output terminal controller changes the level of the output terminal while maintaining the sleep mode. The second timer starts time measurement when the output terminal controller changes the level of the output terminal in the sleep mode. The standby controller performs recovering from the sleep mode of the CPU when the second timer performs a prescribed time measurement. | 2010-12-30 |
20100332875 | Fan Speed Control from Thermal Diode Measurement - Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly. | 2010-12-30 |