52nd week of 2010 patent applcation highlights part 33 |
Patent application number | Title | Published |
20100328968 | MULTI-PHASE RESONANT CONVERTER AND METHOD OF CONTROLLING IT - A PWM controlled multi-phase resonant voltage converter may include a plurality of primary windings powered through respective half-bridges, and as many secondary windings connected to an output terminal of the converter and magnetically coupled to the respective primary windings. The primary or secondary windings may be connected such that a real or virtual neutral point is floating. | 2010-12-30 |
20100328969 | RESONANT POWER CONVERTER COMPRISING A MATCHED PIEZOELECTRIC TRANSFORMER - The present invention relates to an electronic power converter comprising a piezoelectric transformer, a drive circuit arranged to generate and provide an input voltage signal to the piezoelectric transformer, said input voltage signal comprising a burst frequency and a substantially constant excitation frequency, and a rectifier module. According to the present invention the excitation frequency is selected among a plurality of excitation frequencies in such a way that an equivalent load resistance, Req, is matched to an output impedance of the piezoelectric transformer so as to minimize power losses in the piezoelectric transformer. Moreover, the present invention relates to a method for configuring an electronic power converter. | 2010-12-30 |
20100328970 | SINGLE-STAGE HIGH-VOLTAGE POWER SUPPLY WITH HIGH EFFICIENCY AND LOW NETWORK DISTORTION - The invention includes a high-voltage power supply connected, by a network input, to an AC network of frequency Fr, with n phases, and providing a high DC output voltage at at least one HV output. The power supply includes a single-phase high-voltage conversion module per phase of the network having a current rectification circuit connected, by a single-phase input of the conversion module, to a respective phase of the network and, by a rectified-current output, to a switching circuit having at least one switching transistor for switching the rectified current at a frequency Fd and p secondary HV circuits, each providing a secondary, p being an integer greater than or equal to 1, j being the rank of the secondary HV circuit ranging between 1 and p. A control and regulation unit for the power supply comprises a control circuit per conversion module. | 2010-12-30 |
20100328971 | BOUNDARY MODE COUPLED INDUCTOR BOOST POWER CONVERTER - Methods, systems, and devices are described for using coupled inductor boost circuits to operate in a zero current switching (ZCS) and/or a zero voltage switching (ZVS) boundary mode. Some embodiments include a coupled inductor boost circuit that can substantially eliminate rectifier reverse recovery effects without using a high side primary switch and a high side primary switch driver. Other embodiments include a coupled inductor boost circuit that can achieve substantially zero voltage switching. ZCS and ZVS modes may be effectuated using control techniques. For example, a magnetizing current may be sensed or otherwise represented, and a signal may be generated accordingly for controlling switching of the controller. | 2010-12-30 |
20100328972 | VOLTAGE CONVERTER CIRCUIT AND METHOD FOR A CLOCK SUPPLY OF ENERGY TO AN ENERGY STORAGE - The present invention provides a voltage converter circuit for the clocked supply of energy to an energy storage based on an input voltage applied at an input applied at an input of the voltage converter circuit. The voltage converter circuit includes an energy storage and a switch arrangement, wherein the switch arrangement has a first switch and a second switch which are connected in parallel to each other and coupled to the energy storage. The first switch of the switch arrangement has a smaller turn-on voltage according to amount than the second switch, wherein a control terminal of the first switch is wired up such that the first switch is active in a startup phase of the voltage converter circuit to supply energy to the energy storage, and wherein a control terminal of the second switch is wired up such that the second switch is active after the startup phase to supply energy to the energy storage in a clocked way. Further, the voltage converter circuit has a feedback circuit which is implemented to provide a feedback signal depending on a change of the energy stored in the energy storage or depending on an amount of energy stored in the energy storage, wherein the feedback circuit has a switchable coupling element which is implemented to couple the feedback signal to the control terminal of the second switch, and wherein the switchable coupling element is implemented to provide a stronger coupling effect in a startup phase than after the startup phase. | 2010-12-30 |
20100328973 | AC COUPLED SWITCHING POWER SUPPLY AND METHOD THEREFOR - A circuit for converting high voltage AC to low voltage DC has an input capacitor coupled an input AC source. A rectifier is coupled to the input capacitor. A switch is coupled to the rectifier. A voltage regulator is coupled to the switch. The voltage regulator regulates an output of the circuit by closing the switch when a rising edge of a rectified AC voltage is below an output voltage and opens the switch when the output voltage reaches a regulation voltage. A storage capacitor is coupled to the switch. | 2010-12-30 |
20100328974 | RESONANT CONVERTER FOR ACHIEVING LOW COMMON-MODE NOISE, ALONG WITH ISOLATED POWER SUPPLY AND METHOD EMPLOYING THE SAME - Embodiments are described for reducing common-mode current in electronic devices. In the various embodiments, a resonant converter is employed, for example in a power supply, and the resonant converter is driven by a DC input to generate an AC primary voltage on the primary windings of a power transformer. The DC input may be derived from an AC line voltage or a DC-to-DC converter. The AC primary voltage drives the primary winding of the transformer to generate an AC secondary voltage on at least one secondary winding of the transformer. The AC secondary voltage may then drive a rectifier, which in turn drives a low-pass filter to produce a DC output voltage. Phase-shift modulation is employed which, in conjunction with the resonant converter, applies a sinusoidal waveform to the primary of the transformer resulting in a reduced amount of common-mode current injected onto the secondary. | 2010-12-30 |
20100328975 | POWER CONVERTER - In a power converter for converting AC power supplied from an AC power source or DC power supplied from a DC power source to DC power or AC power having predetermined voltage and frequency including at least one switching device ( | 2010-12-30 |
20100328976 | CASCODE CONFIGURED SWITCHING USING AT LEAST ONE LOW BREAKDOWN VOLTAGE INTERNAL, INTEGRATED CIRCUIT SWITCH TO CONTROL AT LEAST ONE HIGH BREAKDOWN VOLTAGE EXTERNAL SWITCH - An electronic system includes a low breakdown voltage (LBV) switch internal to an integrated circuit controller to control conductivity of an external, high breakdown voltage (HBV) switch. In at least one embodiment, the internal LBV switch and a cascode configuration of the LBV and HBV switches allow the controller to control the LBV switch and the HBV switch using an internal (“on-chip”) control signal. In at least one embodiment, the LBV switch and the cascode configuration of the HBV switch also allows the controller to control the LBV and HBV switches with more accuracy and less parasitic losses relative to directly controlling the HBV switch. Thus, in at least one embodiment, the low breakdown voltage switch is fabricated as part of an integrated circuit controller, and the high breakdown voltage switch is fabricated separately and located external to the integrated circuit controller. | 2010-12-30 |
20100328977 | METHOD FOR CONTROLLING A VOLTAGE SOURCE CONVERTER AND A VOLTAGE CONVERTING APPARATUS - In a method for controlling a Voltage Source Converter having at least one phase leg comprising a series connection of switching elements, in which each said element has at least two semiconductor devices of turn-off type, at least two free-wheeling diodes connected in parallel therewith and at least one energy storing capacitor, each said switching element is controlled according to a Pulse Width Modulation pattern so that each switching element is switched to change between applying a zero voltage and the voltage across its capacitor across its terminals each time a saw tooth voltage wave for that switching element crosses a reference alternating voltage belonging to that switching element. | 2010-12-30 |
20100328978 | VARIABLE FREQUENCY TRANSFORMER HAVING MULTIPLE HORIZONTAL ROTARY TRANSFORMERS WITH COMMON CONTROLS AND VOLTAGE INFRASTRUCTURE AND METHOD - A variable frequency transformer including: a first parallel circuit including at least two of the rotary transformers arranged in parallel and having an isolating circuit breaker connected to a rotor winding of each of the rotary transformers, and a separate synchronizing circuit breaker connected to a stator winding in each of the rotary transformers in the first parallel circuit; a first main transformer having a first winding connectable to a first power grid and a secondary winding connectable to the isolating circuit breaker in the first parallel circuit; a second main transformer having a first winding connectable to a second power grid and a secondary winding connectable to each of the synchronizing circuit breakers in the first parallel circuit, and a control system operatively connected to each of the synchronizing circuit breakers, the isolating circuit breakers and the drive motors for each of the rotary transformers. | 2010-12-30 |
20100328979 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF - In a method of operating a nonvolatile memory device, at least one among memory cell blocks of the nonvolatile memory device is designated as a content addressable memory (CAM) block which includes a plurality of CAM cells coupled to respective word lines of the nonvolatile memory device. Chip information for operations of the nonvolatile memory device is stored in the CAM cells which are coupled to a selected word line, whereas the remaining CAM cells of the CAM block are in an erased state. | 2010-12-30 |
20100328980 | MULTI-CHIP MEMORY DEVICE - A multi-chip memory device includes a number of chips and a control circuit included in each of the chips and configured to generate an internal chip enable signal in response to set data stored therein and an external chip enable signal | 2010-12-30 |
20100328981 | CONTENT ADDRESSABLE MEMORY DEVICE FOR SIMULTANEOUSLY SEARCHING MULTIPLE FLOWS - A CAM device includes a CAM array coupled to a programmable priority encoding (PPE) logic circuit. The CAM array concurrently compares multiple input data with stored data to generate corresponding match results that are provided to the PPE logic circuit. The PPE logic circuit selectively favors the match results of a selected flow over the match results of the other flows in response to a flow select signal, which can be toggled to alternately select the match results of various flows. In this manner, the match results of the selected flow are generated and output even if the HPM index of the selected flow is of a lower priority than those of the non-selected flows, thereby ensuring an even distribution of match results reporting between different flows. | 2010-12-30 |
20100328982 | CONTENT ADDRESSABLE MEMORY DESIGN - A static CAM includes a plurality of entries E each including a number of CAM cells B and a summary S. Each CAM cell B is associated with a memory cell M and a comparator C. Generally, the CAM receives as input i number of lookup data lines. When data is received, memory cells M provide compared data for corresponding comparators C in CAM cells B to compare the compared data to the received data. If all compared data match all received data lines for an entry, then there is a hit for that entry. But if any compared data does not match the corresponding data line, then there is a miss for that line and therefore a miss for that entry. Depending on applications, the CAM returns an address if there is a hit for one or a plurality of entries. | 2010-12-30 |
20100328983 | Memory System with Multi-Level Status Signaling and Method for Operating the Same - A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level. | 2010-12-30 |
20100328984 | PIEZO-EFFECT TRANSISTOR DEVICE AND APPLICATIONS - A piezo-effect transistor (PET) device includes a piezoelectric (PE) material disposed between first and second electrodes; and a piezoresistive (PR) material disposed between the second electrode and a third electrode, wherein the first electrode comprises a gate terminal, the second electrode comprises a common terminal, and the third electrode comprises an output terminal such that an electrical resistance of the PR material is dependent upon an applied voltage across the PE material by way of an applied pressure to the PR material by the PE material. | 2010-12-30 |
20100328985 | SEMICONDUCTOR DEVICE HAVING PLURAL CIRCUIT BLOCKS LAID OUT IN A MATRIX FORM - To include an input circuit block to which a plurality of bits are input and a processing circuit block that processes an internal signal output from the input circuit block. The input circuit block includes a plurality of unit input circuits arranged in an X direction to which the bits are input, respectively. Each of the unit input circuits includes an input wiring pattern that extends in a Y direction and a transistor of which a control electrode is connected to a corresponding one of the input wiring pattern. Coordinates of the input wiring pattern and the transistor corresponding to the input wiring pattern in the X direction do not overlap with each other. With this arrangement, by sharing the input wiring pattern between circuit blocks adjacent to each other in the Y direction, it is possible to reduce the number of pre-decode wirings. | 2010-12-30 |
20100328986 | MAGNETIC SHIFT REGISTER MEMORY IN STACK STRUCTURE - A magnetic shift register memory in stack structure includes magnetic shift registering layers for forming an unit of stack structure. Each registering layer has multiple magnetic domains and each domain has a magnetization direction corresponding to a stored data. The two adjacent magnetic shift registering layers respectively have an upper magnetic domain and a lower magnetic domain forming a coupling region. By a coupling structure, the lower magnetic domain and the upper magnetic domain have the same stored data. A driving current unit is coupled to the magnetic shift registering layers for respectively providing a driving current in a predetermined direction to the magnetic shift registering layers. As a result, the stored data in the magnetic domains of the magnetic shift registering layers is shifted in a direction from a foremost registering layer to a last registering layer of the magnetic shift registering layers via the coupling structure. | 2010-12-30 |
20100328987 | E-FUSE APPARATUS FOR CONTROLLING REFERENCE VOLTAGE REQUIRED FOR PROGRAMMING/READING E-FUSE MACRO IN AN INTEGRATED CIRCUIT VIA SWITCH DEVICE IN THE SAME INTEGRATED CIRCUIT - An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode. | 2010-12-30 |
20100328988 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell. | 2010-12-30 |
20100328989 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF AND METHOD FOR WRITING MEMORY ELEMENT - An object is to provide a higher-performance and higher-reliability memory device and a semiconductor device provided with the memory device at low cost and with high yield. A semiconductor device of the invention has a memory element including an insulating layer and an organic compound layer between first and second conductive layers. When melting, an organic compound of the organic compound layer aggregates due to surface tension of the organic compound. By applying a voltage to the first and second conductive layers, writing to the memory element is carried out. | 2010-12-30 |
20100328990 | SRAM DEVICE - An SRAM device comprising a memory cell, the memory cell comprising two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, and
| 2010-12-30 |
20100328991 | SEMICONDUCTOR MEMORY DEVICE - A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses. | 2010-12-30 |
20100328992 | MEMORY - A memory includes: a plurality of memory devices, each including a tunnel magnetic resistance effect device containing a magnetization free layer in which a direction of magnetization can be reversed, a tunnel barrier layer including an insulating material, and a magnetization fixed layer provided with respect to the magnetization free layer via the tunnel barrier layer with a fixed direction of magnetization; a random access memory area in which information is recorded using the direction of magnetization of the magnetization free layer of the memory device; and a read only memory area in which information is recorded depending on whether there is breakdown of the tunnel barrier layer of the memory device or not. | 2010-12-30 |
20100328993 | RECORDING METHOD OF NONVOLATILE MEMORY AND NONVOLATILE MEMORY - A recording method of a nonvolatile memory including a recording circuit that electrically performs recording of information for an information memory device having a resistance change connected to a power supply for information recording, includes the steps of: recording information in a low-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is larger than a resistance value in the low-resistance state of the information memory device; and recording information in a high-resistance state by the recording circuit under a condition that an output impedance of the recording circuit for the information memory device is smaller than a resistance value in the high-resistance state of the information memory device. | 2010-12-30 |
20100328994 | PHASE CHANGE MEMORY WITH FINITE ANNULAR CONDUCTIVE PATH - A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance. | 2010-12-30 |
20100328995 | METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY - Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics. | 2010-12-30 |
20100328996 | PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES - A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions. | 2010-12-30 |
20100328997 | PHASE-CHANGE MEMORY ELEMENT, PHASE-CHANGE MEMORY CELL, VACUUM PROCESSING APPARATUS, AND PHASE-CHANGE MEMORY ELEMENT MANUFACTURING METHOD - A phase-change memory element includes a perovskite layer formed by a material having a perovskite structure, and a phase-change recording material layer which is formed on the perovskite layer, and changes the phase to a crystal state or amorphous state when supplied with an electric current via the perovskite layer. | 2010-12-30 |
20100328998 | MEMORY AND WRITE CONTROL METHOD - A memory includes: a memory device that has a memory layer storing data as a magnetization state of a magnetic body and a magnetization fixed layer whose direction of magnetization is fixed through a nonmagnetic layer interposed between the memory layer and the magnetization fixed layer and stores the data in the memory layer by changing a magnetization direction of the memory layer when a write current flowing in a stacked direction of the memory layer and the magnetization fixed layer is applied; and a voltage control unit that supplies the write current configured by independent pulse trains of two or more to the memory device by using a write voltage that is configured by independent pulse trains of two or more. | 2010-12-30 |
20100328999 | MEMORY AND DATA PROCESSING METHOD - A memory includes: memory devices that each store data of one bit; and a read unit that, by using one predetermined memory device of the memory devices that are included in a memory block having a predetermined unit number of the memory devices as an inversion flag device, reads out data of (the predetermined unit number −1) bits that is written in the other memory devices with the bits being inverted in a case where the data of one bit written in the inversion flag device is a first value representing any one of “0” and “1” and directly reads out the data of (the predetermined unit number −1) bits that is written in the other memory devices in a case where the data of one bit written in the inversion flag device is a second value other than the first value. | 2010-12-30 |
20100329000 | NON-VOLATILE MEMORY - Non-volatile memories can have data retention problems at high temperatures reducing the reliability of such devices. A non-volatile memory cell is described having a magnet, a ferromagnetic switching element and heating means. The non-volatile memory cell has a set position having a low resistance state and a reset position having a high resistance state. The non-volatile memory is set by applying a magnetic field to the switching element causing it to move to the set position. The non-volatile memory cell is reset by the heating means which causes the switching element to return to the reset position. The switching element is formed from a ferromagnetic material or a ferromagnetic shape memory alloy. This structure can have improved reliability at higher temperatures than previously described non-volatile memories. | 2010-12-30 |
20100329001 | Methods of operating semiconductor memory devices including magnetic films having electrochemical potential difference therebetween - Provided are a multi-purpose magnetic film structure using a spin charge, a method of manufacturing the same, a semiconductor device having the same, and a method of operating the semiconductor memory device. The multi-purpose magnetic film structure includes a lower magnetic film, a tunneling film formed on the lower magnetic film, and an upper magnetic film formed on the tunneling film, wherein the lower and upper magnetic films are ferromagnetic films forming an electrochemical potential difference therebetween when the lower and upper magnetic films have opposite magnetization directions. | 2010-12-30 |
20100329002 | FORECASTING PROGRAM DISTURB IN MEMORY BY DETECTING NATURAL THRESHOLD VOLTAGE DISTRIBUTION - Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N | 2010-12-30 |
20100329003 | MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS - A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line. | 2010-12-30 |
20100329004 | DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level. | 2010-12-30 |
20100329005 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A programming method comprised of: classifying memory cells to be programmed into first, second and third levels; applying a program inhibition voltage to an unselected bit line, applying a ground voltage to bit lines, which are coupled with memory cells that are to be programmed into the third level, among selected bit lines, and applying a first voltage, which is lower than the program inhibition voltage but higher than a ground voltage, to bit lines coupled with memory cells that are to be programmed into the second level, and applying a second voltage, which is lower than the program inhibition voltage but higher than the first voltage, to bit line coupled with memory cells that are to be programmed into the first level; and supplying a program voltage, which gradually increases, to a selected word line coupled with the memory cells while applying the voltages to the bit lines. | 2010-12-30 |
20100329006 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEMORIZING MULTIVALUED DATA - In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2 | 2010-12-30 |
20100329007 | Pointer Based Column Selection Techniques in Non-Volatile Memories - Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. to control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed. | 2010-12-30 |
20100329008 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line. | 2010-12-30 |
20100329009 | SMART CARD CAPABLE OF SENSING LIGHT - A smart card is foamed of a memory having light-sensing cells to sense externally supplied light and generate a detection signal in response to the externally supplied light being sensed by the light-sensing cells, and a reset control circuit generating a reset signal in response to the detection signal, the reset signal operating to reset the smart card. | 2010-12-30 |
20100329010 | READ OPERATION FOR MEMORY WITH COMPENSATION FOR COUPLING BASED ON WRITE-ERASE CYCLES - A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn, different sets of pass voltages are applied to WLn+1 for each control gate read voltage which is applied to WLn. The pass voltages vary in each different set so that they are a function of the control gate read voltage which is applied to WLn. The pass voltages may also be a function of a number of program-erase cycles. A higher amount of compensation is provided by increasing the pass voltages as the number of program-erase cycles increases. | 2010-12-30 |
20100329011 | MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE - A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers. | 2010-12-30 |
20100329012 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line. | 2010-12-30 |
20100329013 | SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL AND DATA WRITING METHOD THEREOF - A semiconductor memory device includes memory cells, bit lines, and first and second control circuits. The first control circuit supplies a write voltage and a write control voltage to a selected memory cell to write the data in the selected memory cell, the first control circuit changes a supply state of the write control voltage to further write the data when the selected memory cell reaches a first write state by the write, the first control circuit further changes the supply state of the write control voltage to prohibit the write when the selected memory cell reaches a second write state by the write. The second control circuit controls a rising of the write control voltage when the first control circuit starts the writing to make the selected memory cell the second write state. | 2010-12-30 |
20100329014 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING THE SAME - A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed. | 2010-12-30 |
20100329015 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes reading data stored in a main cell and a flag cell using a first read voltage, the nonvolatile memory device comprising the main cell for storing data including a least significant bit (LSB) and a most significant bit (MSB), and the flag cell for determining a program state of the main cell, determining a program state of the main cell based on the data read from the flag cell, reading data stored in the main cell and the flag cell using a second read voltage if a MSB page program has been performed on the main cell, and reading data stored in the main cell using a third or a fourth read voltage based on the data read from the flag cell using the second read voltage, if a threshold voltage of the main cell shifts. | 2010-12-30 |
20100329016 | SEMICONDUCTOR DEVICE - The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well. | 2010-12-30 |
20100329017 | SEMICONDUCTOR DEVICE FOR SHORT-CIRCUITING OUTPUT TERMINALS OF TWO OR MORE VOLTAGE GENERATOR CIRCUITS AT READ TIME AND CONTROL METHOD FOR THE SAME - According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time. | 2010-12-30 |
20100329018 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE CAPABLE OF READING TWO PLANES - A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data. | 2010-12-30 |
20100329019 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRONIC DEVICE USING THE SAME - When data is read from a memory cell of a top array block to a bit line, a switching device is closed so that the data is stored in the form of electrical charges at a bit line of a bottom array block. The switching device at a top array side is opened to drive a sense amplifier, and thus, the data read from the memory cell and retained at the bit line of the bottom array block is output to the outside. While the data is output in the above-described manner, a potential of the bit line of the top array block can be precharged to start a next read operation. | 2010-12-30 |
20100329020 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes an initial data setting step of inputting data for program inhibition to a first latch of a page buffer to which memory cells to be programmed with a second threshold voltage distribution are coupled, a first program and verification step of performing program and verification operations, a first data setting step of, when a program pulse is supplied more than N times (where N is a natural number), inputting data for performing a program operation to the first latch of the page buffer to which the memory cells to be programmed with the second threshold voltage distribution are coupled, and a second program and verification step of performing program and verification operations. | 2010-12-30 |
20100329021 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level according to the program data; when the threshold voltages of the memory cells reach the target level, performing an over-program verification operation to determine over-programmed memory cells in the memory cells; and making a determination of whether error checking and correction (ECC) processing for the over-programmed memory cells is feasible. | 2010-12-30 |
20100329022 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises performing a first program operation on first memory cells and second memory cells so that threshold voltages of the first and second memory cells have a first reference level lower than a first target level, the first memory cells having the first target level as a first target level, and the second memory cells having a second target level higher than the first target level as a second target level; performing a second program operation on the second memory cells so that the threshold voltages of the second memory cells have a second reference level lower than the second target level; and performing a third program operation on the first and second memory cells to have the respective target levels. | 2010-12-30 |
20100329023 | SENSE AMPLIFIER APPARATUS AND METHODS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed. | 2010-12-30 |
20100329024 | MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS - A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal. | 2010-12-30 |
20100329025 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current. | 2010-12-30 |
20100329026 | SEMICONDUCTOR MEMORY DEVICE WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes memory cells, first and second selection transistors, a source line, a temperature monitor, and a source line voltage controller. The memory cells are connected in series between a source of the first selection transistor and a drain of the second selection transistor. The temperature monitor monitors a temperature of the semiconductor substrate. The source line voltage controller applies a voltage to the source line, in a read operation, in such a manner that a potential difference between the source line and the semiconductor substrate increases according to a rise in the temperature monitored by the temperature monitor and that a reverse bias is applied between the source of the second selection transistor and the semiconductor substrate. | 2010-12-30 |
20100329027 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a control unit configured to output operation signals, including an operation command signal, a source address, a destination address, and a data signal, to each of a number of memory chips in order to operate the memory chips, a command decoder configured to decode the command signal and generate operation command information, a source address controller configured to generate source address information based on the source address, a destination address controller configured to generate destination address information based on the destination address, a chip controller configured to generate a command enable signal based on the operation command information, the source address information, and the destination address information, and a data controller configured to operate a memory cell array in response to the data signal and the command enable signal. | 2010-12-30 |
20100329028 | METHOD OF PERFORMING PROGRAM VERIFICATION OPERATION USING PAGE BUFFER OF NONVOLATILE MEMORY DEVICE - A method of performing a program verification operation in a nonvolatile memory device includes storing program data, programmed into a selected memory cell of a memory cell block, in a page buffer which is coupled to a bit line of the memory cell block via a sense node, controlling a voltage level of the sense node in response to a value of the program data, changing the voltage level of the sense node in response to a program state of the selected memory cell coupled to the bit line, and performing a program verification operation on the selected memory cell by sensing the voltage level of the sense node. | 2010-12-30 |
20100329029 | PAGE BUFFER, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND PROGRAM AND DATA VERIFICATION METHOD - A page buffer includes a sense latch, a data latch and a page buffer controller. The sense latch is connected to a bit line, and is configured to set stored data in response to a sense latch control signal, and to change the stored data in response to a signal applied to the bit line in a data verification operation. The data latch is configured to store multi-bit data to be programmed in a program operation, and to set stored data in response to a data latch control signal in the data verification operation. The page buffer controller is configured to control the bit line in accordance with the multi-bit data stored in the data latch in the program operation, and to output the sense latch control signal and the data latch control signal in accordance with the multi-bit data stored in the data latch in response to a control signal in the data verification operation. | 2010-12-30 |
20100329030 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - In a nonvolatile memory device, a cache program operation for the next data is performed in a first latch, and a verification program operation for the current data is performed using a second latch. Thus, data collision can be avoided and execution time can be reduced. | 2010-12-30 |
20100329031 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes precharging bit lines coupled to strings, supplying a first verification voltage to a selected word line and supplying a pass voltage to word lines other than the selected word line, supplying a first sense pulse to switching elements coupled between the bit lines and sense nodes and detecting memory cells, each having a threshold voltage higher than the first verification voltage, supplying a second verification voltage higher than the first verification voltage to the selected word line and supplying the pass voltage to the word lines other than the selected word line, and supplying a second sense pulse to the switching elements and detecting memory cells, each having a threshold voltage higher than the second verification voltage. | 2010-12-30 |
20100329032 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected for a program operation. Data are loaded which will be programmed into the second logical page into first to third latches of a selected page buffer, coupled to the selected memory cells, from among the page buffers. A data setting operation is performed. The second logical page is programmed so that a distribution of threshold voltages of the selected memory cells has one of first to fourth threshold voltage distributions according to states of the data of the first to third latches and performing verification operations for the first to fourth threshold voltage distributions. | 2010-12-30 |
20100329033 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In general, according to one embodiment, a nonvolatile semiconductor memory device includes: a memory cell array including memory cells; and a control unit to control a signal applied to the memory cells. Each of the memory cells are settable to: first, second and third states having first, second and third threshold voltage distributions (VD | 2010-12-30 |
20100329034 | ESTIMATING VALUES RELATED TO DISCHARGE OF CHARGE-STORING MEMORY CELLS - One or more groups of charge-storing memory cells are selected from a plurality of regular charge-storing memory cells of a storage device. The selected memory cells are initialized with initial binary data, by charging them with corresponding amounts of electric charge, or the selected memory cells are simply used as is containing user data. Then, while the selected memory cells undergo a self discharge process, collective changes in the binary states of the selected memory cells are used to estimate discharge-determining conditions such as elapsed time, wear rate or wear level of the memory cells. The adverse effects of the erratic behavior of individual charge-storing memory cells on such estimations is mitigated by using a large group of charge-storing memory cells, and the effect of temperature on the aforesaid estimations is reduced by using two or more large groups of charge-storing memory cells. | 2010-12-30 |
20100329035 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DISCHARGE CIRCUIT THEREOF - A discharge circuit of a nonvolatile semiconductor memory device includes a memory array region including a plurality of floating gate type MOS memory cell transistors each including a source, a drain and a control gate which are formed in a P-well, where the P-well is formed in an N-well of a P-type semiconductor substrate. The discharge circuit further includes a plurality of terminals formed in the memory array region, and respectively connected to the control gate, the P-well and the N-well, a plurality of constant current transistors respectively connected to the plurality of terminals, and a plurality of switching transistors respectively connected to the plurality of constant current transistors. The respective constant current transistors and switching transistors are turned on at a same timing during a discharge operation. | 2010-12-30 |
20100329036 | NONVOLATILE MEMORY DEVICE AND READING METHOD THEREOF - In a nonvolatile memory device and operating method thereof, data programmed into a second memory cell is sensed and a first memory cell adjacent the second memory cell is read in accordance with the data sensed from the second memory cell. | 2010-12-30 |
20100329037 | CIRCUIT FOR SUPPLYING WELL VOLTAGES IN NONVOLATILE MEMORY DEVICE - A circuit for supplying well voltages in a nonvolatile memory device includes an erase voltage supply unit for supplying an erase voltage to a well in response to an erase enable signal, a discharge unit for discharging the erase voltage, supplied to the well, in response to a discharge control signal, and a negative voltage supply unit for supplying a negative voltage to the well in response to a negative voltage output enable signal. | 2010-12-30 |
20100329038 | METHODS OF OPERATING MEMORY DEVICES INCLUDING DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size. | 2010-12-30 |
20100329039 | DATA BUFFER CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A data buffer control circuit and a semiconductor memory apparatus including the same are presented. The data buffer control circuit may include an internal command signal generator and a buffer enable signal generator. The internal command signal generator is configured to generate an internal command signal that is activated if delayed command signals are conditioned in a predetermined state of level combination. The buffer enable signal generator is configured to generate a buffer enable signal, which enables a data buffer receiving data in a writing mode, from the internal command signal in sync with a falling edge of an internal clock signal. | 2010-12-30 |
20100329040 | DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes. | 2010-12-30 |
20100329041 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER-SAVING EFFECT - A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array. | 2010-12-30 |
20100329042 | MEMORY CHIP PACKAGE WITH EFFICIENT DATA I/O CONTROL - A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit. | 2010-12-30 |
20100329043 | Two-Transistor Floating-Body Dynamic Memory Cell - Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density. | 2010-12-30 |
20100329044 | Assisting write operations to data storage cells - A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal. | 2010-12-30 |
20100329045 | Adjustment of Write Timing in a Memory Device - A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal. | 2010-12-30 |
20100329046 | INTEGRATED CIRCUIT MEMORY OPERATION APPARATUS AND METHODS - Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the memory cell, and a first line configured to transfer information to and from the memory cell. The control signal has a first level during a first time interval and a second level during a second time interval of a memory operation. The apparatus and methods also include a module configured to reduce difference between a value of a voltage on the second line and a value of a voltage on a node of the device during a first time portion of the second time interval. Additional apparatus and methods are disclosed. | 2010-12-30 |
20100329047 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device, including an X decoder coupling global lines to respective word lines to which memory cells are coupled, a voltage supply unit comprising voltage selection circuits corresponding to the respective global lines and configured to generate operating voltages, wherein each of the voltage selection circuits latches control signals, each determined according to a corresponding line enable signal and a corresponding voltage control signal, and selects and supplies one of the operating voltages in response to the control signals, and a control unit supplying a number of the line enable signals and a number of the voltage control signals to the voltage supply unit. | 2010-12-30 |
20100329048 | PRECHARGE SIGNAL GENERATOR AND SEMICONDUCTOR MEMORY DEVICE - A precharge signal generator having a latch signal generator, an internal signal generator, and a pulse generator is presented. The latch signal generator is configured to generate a latch signal that is activated in response to an auto-precharge command and inactivated in response to an active pulse. The internal signal generator is configured to generate an internal signal activated when a delayed active signal and the latch signal are all activated. The pulse generator is configured to generate a precharge signal including a pulse that is activated in a period for which the internal signal is being active. | 2010-12-30 |
20100329049 | SEMICONDUCTOR MEMORY DEVICE HAVING A LATENCY CONTROLLER - A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register. | 2010-12-30 |
20100329050 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal. | 2010-12-30 |
20100329051 | METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS - A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated after the sense amplifier power supply circuit is enabled. | 2010-12-30 |
20100329052 | Word line defect detecting device and method thereof - Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line. | 2010-12-30 |
20100329053 | SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY AREA - Provided is a semiconductor memory device. The semiconductor memory includes a main area and a redundancy area. The main area includes a plurality of memory blocks sharing a write bit line and a read bit line. The redundancy area includes a plurality of redundancy memory blocks sharing a redundancy write bit line and a redundancy read bit line. The redundancy area is provided to replace a component in the main area having a defect. | 2010-12-30 |
20100329054 | Memory Built-In Self-Characterization - A memory circuit includes an operational memory and a monitor circuit comprising a circuit element in the operational memory and/or a circuit element substantially identical to a corresponding circuit element in the operational memory. The monitor circuit is operative to measure at least one functional characteristic of the operational memory. A control circuit coupled to the monitor circuit is operative to generate a control signal which varies as a function of the measured characteristic of the operational memory. The memory circuit further includes a programmable voltage source coupled to the operational memory which is operative to generate at least a voltage and/or a current supplied to at least a portion of the operational memory which varies as a function of the control signal. | 2010-12-30 |
20100329055 | MEASURING ELECTRICAL RESISTANCE - A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device. | 2010-12-30 |
20100329056 | SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal. | 2010-12-30 |
20100329057 | Method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation - In a method of discharging bit-lines for a non-volatile semiconductor memory device performing a read-while-write operation. The method include discharging a global write bit-line to a ground voltage based on a write command within a first period. the method also includes maintaining the discharged voltage of the global write bit-line in the ground voltage during a second period. | 2010-12-30 |
20100329058 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line. | 2010-12-30 |
20100329059 | APPARATUS AND METHODS FOR SENSE AMPLIFIERS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed. | 2010-12-30 |
20100329060 | COUNTER CONTROL SIGNAL GENERATOR AND REFRESH CIRCUIT - A counter control signal generator comprises a first pulse signal generator configured to generate a first pulse signal including a pulse generated when a self-refresh period is terminated, a second pulse signal generator configured to generate a second pulse signal including a pulse generated in sync with a cyclic signal generated during a refresh period, and a signal generator configured to generate a counter control signal counting an address of a memory cell, corresponding to a memory cell on which a refresh operation is conducted, in response to the first and second pulse signals. | 2010-12-30 |
20100329061 | ELECTRICAL FUSE CIRCUIT FOR SECURITY APPLICATIONS - A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation. | 2010-12-30 |
20100329062 | Leakage and NBTI Reduction Technique for Memory - In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion. | 2010-12-30 |
20100329063 | DYNAMICALLY CONTROLLED VOLTAGE REGULATOR FOR A MEMORY - A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM. | 2010-12-30 |
20100329064 | SYSTEMS, METHODS AND DEVICES FOR MONITORING CAPACITIVE ELEMENTS IN DEVICES STORING SENSITIVE DATA - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a data storage device stores data in response to data accesses under the control of a memory control circuit. A solid-state memory circuit and a volatile caching memory circuit provide the memory control circuit with access to a set of common data. A power-reservoir circuit includes two or more capacitor cells that respectively hold charge to provide operating power to the data storage device to permit transfer of the data from the volatile memory circuit to the solid-state memory circuit in the event of a power loss. A detection circuit is connected to a center tap between the capacitor cells and uses the tap to detect characteristics of the cells relative to one another, and to provide an output that can be used to characterize the cells' electrical characteristics relative to one another. | 2010-12-30 |
20100329065 | SYSTEMS, METHODS AND DEVICES FOR POWER CONTROL IN MASS STORAGE DEVICES - Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, an energy storage circuit is powered using a variable voltage controlled to limit the current draw from a power supply, to charge the energy storage circuit for providing backup power to a solid state drive (SSD) type of data storage arrangement. Certain applications involve controlling the power draw from the power supply, in response to feedback and/or power drawn from other circuits, as may be applicable to an initial startup of the energy storage circuit and/or the initial startup of a larger system in which the energy storage circuit is employed. | 2010-12-30 |
20100329066 | NON-BLOCKING MULTI-PORT MEMORY FORMED FROM SMALLER MULTI-PORT MEMORIES - A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the memories, each of the subset of memories being provided in a corresponding one of the groups, a number of the copies of the data unit being greater than two. Multiplexers may be implemented, each of which being associated with a corresponding one of the groups of the memories. One of the plurality of multiplexers may be configured to selectively supply one of the copies of the data unit from one of the memories. A read port may receive the one of the copies of the data unit from the one of the multiplexers and output the one of the copies of the data unit. | 2010-12-30 |
20100329067 | CHARGE PUMP AND SEMICONDUCTOR DEVICE HAVING THE SAME - A charge pump and method of operation are provided. The charge pump includes a first boosting unit configured to receive a pre-charge voltage and electrically charge a first MOS capacitor during a pre-charge period, and to boost a voltage of a connection node to a first output voltage during a boosting operation period, and a second boosting unit configured to receive the pre-charge voltage and electrically charge a second MOS capacitor during the pre-charge period, and to receive the first output voltage and boost a voltage of an output node to a second output voltage during the boosting operation period. Here, the pre-charge voltage is applied to electrically charge a parasitic capacitor during a parasitic capacitor charging period between the pre-charge period and the boosting operation period. | 2010-12-30 |