52nd week of 2010 patent applcation highlights part 22 |
Patent application number | Title | Published |
20100327868 | SAR CALCULATION FOR MULTICHANNEL MR TRANSMISSION SYSTEMS - In a device and a method to determine SAR for a magnetic resonance tomography transmission system with multiple antenna elements, a single-column cross-correlation matrix of an antenna element matrix of antenna element values of multiple antenna elements of the magnetic resonance tomography transmission system is determined for each of multiple points in time or time periods. These single-column cross-correlation matrices are added into a sum cross-correlation matrix over a summation time period and the sum cross-correlation matrix is multiplied with a hotspot sensitivity matrix. The hotspot sensitivity matrix represents the sensitivities in at least one direction at a number of hotspot points in a subject located in the magnetic resonance tomography transmission system. The product of the sum cross-correlation matrix and the hotspot sensitivity matrix is multiplied with a value representing the dielectricity at least one hotspot point in order to determine a respective SAR value for hotspot points. If at least one SAR value exceeds a predetermined upper limit, the voltage applied to at least one antenna element or the current flowing in at least one antenna element is reduced or deactivated. | 2010-12-30 |
20100327869 | ULTRA-SENSITIVE SUSCEPTIBILITY DETECTION APPARATUS OF ANHARMONIC RESONANCE MEASUREMENT TYPE USING ATOMIC MAGNETOMETER, AND METHOD OF USING SAME - The ultra-sensitive susceptibility detection apparatus of anharmonic resonance measurement type using an atomic magnetometer detects a change in susceptibility by a specimen containing an object to be measured. The apparatus includes an atomic magnetometer. The atomic magnetometer includes a cell containing an alkaline metallic atom, a light source for magnetically polarizing the alkaline metallic atom of the cell, and a bias magnetic field applicator for applying a bias magnetic field to adjust a measuring resonance frequency of the alkaline metallic atom. The apparatus includes an excitation magnetic field applicator for applying an excitation magnetic fields of different frequencies to magnetically excite the specimen, but not to couple the excitation field directly to the measuring atomic resonance frequency, and a measuring device for measuring a change in magnetic polarization of the alkaline metallic atom, which is affected by a magnetic field caused by the specimen being magnetically excited by the excitation magnetic field. | 2010-12-30 |
20100327870 | MOVABLE TABLE FOR MAGNETIC RESONANCE IMAGING - In MR imaging, the patient is placed on the table in a configuration convenient for a surgical procedure and while in the configuration the patient is moved into the field of view by moving the magnet longitudinally and the table is moved in the bore relative to the magnet so as to optimize the part to be imaged within the field of view of the magnet. After imaging the table is moved back to the preset position and removed from the magnet for the surgical procedure to commence or continue. The movement includes movement along the longitudinal axis; transverse movement side to side; rolling movement about a longitudinal axis; tilting movement about a transverse axis and bending movement of the table relative to at least one transverse hinge line in the table at a position spaced from the ends of the table. | 2010-12-30 |
20100327871 | MAGNETIC RESONANCE IMAGING APPARATUS AND METHOD - A magnetic resonance imaging (MRI) apparatus sequentially transmits a plurality of radio frequency (RF) pulses for refocusing transverse magnetization of spins, and brings the transverse magnetization of the spins to longitudinal magnetization after the refocusing of the transverse magnetization of the spins. | 2010-12-30 |
20100327872 | Devices And Methods For LED Life Test - A life test device comprises an oven, a current source, a voltage meter, a control module, and a process module. A light-emitting diode (LED) is disposed in the oven. The temperature of the oven is gradually changed in a first period and remains at a set temperature in a second period. The current source provides a first current and a second current to the LED. The voltage meter measures forward voltages of the LED. The control module controls the current source to output the first or second current to the LED and controls the voltage meter to measure the forward voltages of the LED. The process module calculates a junction temperature of the LED according to the forward voltages and a variation relationship formula between the forward voltages and the temperature of the oven. | 2010-12-30 |
20100327873 | MULTI-DIAGNOSTIC APPARATUS FOR SUBSTRATE-LEVEL MEASUREMENTS - Described herein is a method and apparatus for diagnosing processing equipment with a multi-diagnostic device. In one embodiment, a multi-diagnostic device is located in a plasma processing environment and includes an electronic circuitry. The device includes a first array of sensors and a second array of sensors. The circuitry is used to simultaneously (or nearly simultaneously) measure the distributions of ion saturation current and the potential at the device using the first array of sensors and to measure resistances of the second array of sensors to determine the distribution of the temperature at the surface of the device. | 2010-12-30 |
20100327874 | ELECTRO-DIFFUSION ENHANCED BIO-MOLECULE CHARGE DETECTION USING ELECTROSTATIC INTERACTION - According to one aspect, the disclosure is directed to an example embodiment in which a circuit-based arrangement includes a circuit-based substrate securing a channel, with an effective width that is not limited by the Debye screening length, along a surface of the substrate. A pair of reservoirs are included in or on the substrate and configured for containing and presenting a sample having bio-molecules for delivery in the channel. A pair of electrodes electrically couple a charge in the sample to enhance ionic current flow therein (e.g., to overcome the electrolyte screening), and a sense electrode is located along the channel for sensing a characteristic of the biological sample by using the electrostatic interaction between the enhanced ionic current flow of the sample and the sense electrode. Actual detection occurs by using a charge-signal processing circuit to process the sensed charge signal and, therefrom, provide an output indicative of a signature for the bio-molecules delivered in the channel. | 2010-12-30 |
20100327875 | Integrated Circuit Thermally Induced Noise Analysis - A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz. | 2010-12-30 |
20100327876 | LAYOUT STRUCTURE OF ELECTRONIC ELEMENTS AND METHOD FOR ADDRESSING TO DETECT ELECTRONIC ELEMENTS - A layout structure of electronic elements includes M*N electronic elements in a form of a matrix, a first test pad group disposed on a first side of the matrix and all electronic elements in the same linear section in the matrix electrically connect to a corresponding test pad in the first test pad group, and a second test pad group disposed on a second side of the matrix and all electronic elements in the same linear section in the matrix electrically connect to a corresponding test pad in the second test pad group. | 2010-12-30 |
20100327877 | RADIO FREQUENCY IDENTIFICATION (RFID) DEVICE AND METHOD FOR TESTING THE SAME - A radio frequency identification (RFID) device and a test method thereof are disclosed. In this test method, the RFID device receives different kinds of tag selection addresses and memory addresses according to a time sharing scheme, so that one or more RFID tags are tested. The RFID device includes a tag chip and a test chip. The tag chip performs a test operation upon receiving a test input signal from an external node, and externally outputs a test output signal indicating a result of the test operation. The test chip tests the tag chip upon receiving an address and data from an external node via a test pad during a test mode. | 2010-12-30 |
20100327878 | Disconnection detecting device - A switch element is configured to decrease an impedance of a voltage-detection integrated circuit that detect voltage between both ends of unit cells of a higher-ordered battery block, for adjacently-connected pair of the higher-ordered battery block and a lower-ordered battery block. The voltage-detection integrated circuit is configured to detect disconnection of an electrical wire when voltage between both ends of a lowest-ordered unit cell that is detected with the switch element turned on is equal to or lower than a threshold. | 2010-12-30 |
20100327879 | CIRCUIT TEST JIG AND CIRCUIT TESTING METHOD - A circuit test jig used for a printed board that includes a circuit board on which a circuit is formed, the circuit test jig includes a holding plate disposed between the circuit board and the print board and holds a plurality of conductive members that transmit signals between a group of terminals of the printed board and a group of terminals of the circuit board, and an elastic plate in which through holes are formed therein disposed at least one of between the holding plate and the circuit board or between the holding plate and the printed board. | 2010-12-30 |
20100327880 | PULSED WAVEGUIDE SENSING DEVICE AND METHOD FOR MEASURING A PARAMETER - At least one embodiment is directed to a sensor for measuring a parameter. A signal path of the system comprises an amplifier ( | 2010-12-30 |
20100327881 | Control unit, sensing device for a capacitive touch panel and method therefor - A noise reducing device for a capacitive touch panel and a method of reducing noise for a capacitive touch panel are disclosed to solve problems related to noise generated by a conventional filter circuit and an integrating circuit or external noise. In the invention, at least one switch circuit is used so that the conventional filter circuit and integrating circuit used in the prior are omitted. Signals output from a current measurement circuit are transmitting to a control unit to calculate the location of a touch point, reducing any noise. | 2010-12-30 |
20100327882 | CAPACITIVE SENSOR INTERFERENCE DETERMINATION - In a method of determining interference in a capacitance sensor, a signal is transmitted on a transmitter sensor channel of the capacitive sensor. The signal is received on a receiver sensor channel of the capacitive sensor, the receiver sensor channel being coupled with an amplifier. Behavior of the amplifier is examined for non-linearity to determine if a level of interference has been received by the receiver sensor channel in conjunction with receipt of the signal. | 2010-12-30 |
20100327883 | INDUCTIVE DELTA C EVALUATION FOR PRESSURE SENSORS - A measuring device has a sensor unit and an evaluation unit which is electrically isolated from the sensor unit by a partition wall. The sensor unit includes a first capacitive sensor which is electrically connected to a first coil to form a first oscillating circuit, and a reference capacitor which is electrically connected to a second coil to form a second oscillating circuit. The evaluation unit includes a third coil which is inductively coupled to the first coil and the second coil, and the evaluation unit is designed to determine and output a beat frequency of a beat signal which is inductively injected into the third coil by the first oscillating circuit and the second oscillating circuit. | 2010-12-30 |
20100327884 | Liquid level and quality sensing apparatus, systems and methods using EMF wave propagation - A liquid level, composition and contamination sensor generates an RF signal across a resonant circuit that includes a variable inductor and capacitor. The resulting electromagnetic radiation is propagated into the liquid and changes in impedance and resonance of the resonant circuit that result from changes in the conductivity and dielectric properties of the liquid, which are proportional to liquid content and volume, are detected. The conductivity and dielectric properties of the liquid are measured, based on the changed impedance and resonance of the resonant circuit, and are compared to determine aging and contamination of the urea solution by other liquids. Also, an optical sensor may be submerged in the liquid to determine the refractive index of the liquid. The refractive index of the liquid may be used to determine: if the liquid is water or a urea solution; the concentration of a urea solution. | 2010-12-30 |
20100327885 | Method for estimating and removing air wave response in marine electromagnetic surveying - A method for determining resistivity distribution of formations below a bottom of a body of water from transient electromagnetic signals acquired by imparting a transient electromagnetic field into the water and detecting an electromagnetic response thereto at a plurality of spaced apart positions from a place of the imparting includes simulating an air wave response at each of the plurality of spaced apart positions. The simulated air wave response is subtracted from the detected response to produce a subsurface impulse response at each of the plurality of positions. The subsurface impulse responses are used to determine the resistivity distribution. | 2010-12-30 |
20100327886 | MEASUREMENT DEVICE, MEASUREMENT SYSTEM, AND CONCENTRATION MEASUREMENT METHOD - A first measurement device is a measurement device for measuring the concentration of a target substance in a sample deposited on a biosensor, and more particularly is constituted such that at least two kinds of voltage of mutually different levels are applied at mutually different timings to the electrode system of the biosensor, and the concentration is corrected on the basis of the amount of change in the current value. | 2010-12-30 |
20100327887 | CHOPPER-STABILIZED INSTRUMENTATION AMPLIFIER FOR IMPEDANCE MEASUREMENT - In general, this disclosure is directed to a mixer amplifier that can be utilized within a chopper stabilized instrumentation amplifier. The chopper stabilized instrumentation amplifier may be used for physiological signal sensing, impedance sensing, telemetry or other test and measurement applications. In some examples, the mixer amplifier may include a current source configured to generate a modulated current at a modulation frequency for application to a load to produce an input signal, an amplifier configured to amplify the input signal to produce an amplified signal, and a demodulator configured to demodulate the amplified signal at the modulation frequency to produce an output signal indicating an impedance of the load. | 2010-12-30 |
20100327888 | METHOD FOR DETERMINING THE SIZE AND SHAPE MEASURE OF A SOLID MATERIAL IN AN ARC FURNACE, AN ARC FURNACE, A SIGNAL PROCESSING DEVICE AND PROGRAM CODE AND A MEMORY MEDIUM - In a method for determining the size and shape value (M) for a solid material (S), in particular scrap metal, in an arc furnace ( | 2010-12-30 |
20100327889 | POSITION DETECTING DEVICE - A selector switch is provided which always connects a receiving side electrode to one of a positive electrode input terminal and a negative electrode input terminal of a differential amplifier section. This selector switch is controlled so as to form a positive electrode region in which a plurality of electrode elements connected to the positive electrode input terminal are arranged, a negative electrode region in which a plurality of electrode elements connected to the negative electrode input terminal are arranged, and an insensitive region in which electrode elements are alternately connected to the positive electrode input terminal and the negative electrode input terminal. | 2010-12-30 |
20100327890 | QUALITY CONTROL PROCESS FOR UMG-SI FEEDSTOCK - A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower. | 2010-12-30 |
20100327891 | METHOD AND APPARATUS FOR THERMALLY CONDITIONING PROBE CARDS - Embodiments of probe cards and methods for fabricating and using same are provided herein. In some embodiments, an apparatus for testing a device (DUT) may include a probe card configured for testing a DUT; a thermal management apparatus disposed on the probe card to heat and/or cool the probe card; a sensor disposed on the probe card and coupled to the thermal management apparatus to provide data to the thermal management apparatus corresponding to a temperature of a location of the probe card; a first connector disposed on the probe card and coupled to the thermal management apparatus for connecting to a first power source internal to a tester; and a second connector, different than the first connector, disposed on the probe card and coupled to the thermal management apparatus for connecting to a second power source external to the tester. | 2010-12-30 |
20100327892 | Parallel Array Architecture for Constant Current Electro-Migration Stress Testing - A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic. | 2010-12-30 |
20100327893 | Probing Structure for Evaluation of Slow Slew-Rate Square Wave Signals in Low Power Circuits - An integrated circuit probing structure ( | 2010-12-30 |
20100327894 | Dual Tip Test Probe Assembly - A dual tip test probe assembly for use in both cantilever and vertical probe applications includes first and second elongated test probes, each having a body portion and a tip portion with a tip configured to make contact with a device under test. An electrically-insulating material is disposed between but not in contact with the body portions of the first and second elongated test probes to electrically isolate the first and second elongated test probes. The first and second elongated test probes are held in alignment with respect to each other so that the tip of the first elongated test probe is adjacent to and not in contact with the tip of the second elongated test probe for making simultaneous contact with the device under test. The dual tip test probe assembly provides a low inductance and a small, stable footprint for testing small and/or non-flat test points. | 2010-12-30 |
20100327895 | MODULE FOR A PARALLEL TESTER FOR THE TESTING OF CIRCUIT BOARDS - The invention relates to a module for a parallel tester for the testing of circuit boards, and to a parallel tester comprising such modules. | 2010-12-30 |
20100327896 | PROBE ASSEMBLY AND MANUFACTURING METHOD THEREOF - A probe assembly has insertion holes formed in a base layer provided on a circuit board. Probe pins are inserted into the insertion holes and fixed by a conductive adhesive filled in the insertion holes. The probe pins can be arranged with small pitch without mechanically electrically interfering with neighboring pins using the insertion holes. Furthermore, the base layer is formed of a semiconductor material to prevent a problem caused by a difference in the coefficient of thermal expansion between the base layer and a wafer. Moreover, coplanarity and alignment accuracy of the probe pins can be improved using aligning mask layers or aligning mask in a process of manufacturing the probe assembly. In addition, probe assembly manufacturing time can be reduced by using a pin array frame into which a large number of probe pins are temporarily inserted. | 2010-12-30 |
20100327897 | WIRING SUBSTRATE AND PROBE CARD - A wiring substrate that allows wiring at a fine pitch and has a coefficient of thermal expansion close to the coefficient of thermal expansion of silicone, and a probe card that includes the wiring substrate are provided. To this end, there are provided a wiring substrate that includes a ceramic substrate having a coefficient of thermal expansion of 3×10 | 2010-12-30 |
20100327898 | PROBE CARD AND INSPECTION APPARATUS - An automatic switching mechanism is controlled by a probe card independent from a tester without limitation of the number of control signals from the tester. A probe card and an inspection apparatus include probes to be brought into contact with electrodes of inspection targets and a power supply channel electrically connecting the probes to a tester. The automatic switching mechanism divides each of the power supply channels into a plurality of power supply wiring portions, which are respectively connected to the probes; and shuts off the power supply wiring responsive to electrical fluctuation such as overcurrent. An electrical fluctuation detection mechanism detects an electrical fluctuation due to a defective product among the inspection targets. A control mechanism, responsive to detection of an electrical fluctuation, shuts off the power supply wiring portion if the electrical fluctuation is caused by the automatic switching mechanism. | 2010-12-30 |
20100327899 | DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - According to one embodiment, a design support apparatus includes a first detector configured to detect a cable connected to the printed circuit board, a second detector configured to detect a conducting component from components of a housing, a third detector configured to detect an electromagnetic wave radiating component from electronic components mounted on the printed circuit board, a fourth detector configured to detect a path which propagates the electromagnetic waves, a first setting module configured to set, as sources, the electromagnetic wave radiating component and the path, a second setting module configured to set, for the sources, intensity attributes corresponding to an operation clock frequency of the electromagnetic wave radiating component, a calculator configured to calculate spaces of the sources, the spaces includes volumes corresponding to the intensity attributes, and a determining module configured to determine whether at least one of the cable passes at least one of the spaces. | 2010-12-30 |
20100327900 | POLISHING HEAD TESTING WITH MOVABLE PEDESTAL - A polishing head is tested in a test station having a pedestal for supporting a test wafer and a controllable pedestal actuator to move a pedestal central wafer support surface and a test wafer toward the polishing head. In another aspect of the present description, the test wafer may be positioned using a positioner having a first plurality of test wafer engagement members positioned around the pedestal central wafer support surface. In another aspect, the wafer position may have a second plurality of test wafer engagement members positioned around an outer wafer support surface disposed around the pedestal central wafer support surface and adapted to support a test wafer. The second plurality of test wafer engagement members may be distributed about a second circumference of the ring member, the second circumference having a wider diameter than the first circumference. Additional embodiments and aspects are described and claimed. | 2010-12-30 |
20100327901 | POWER SUPPLY TESTING SYSTEM - A testing system for testing a conversion efficiency of a power supply unit (PSU) includes a power meter, a plurality of switches, a multimeter, a microcontroller unit, and a data processing device. The power meter is utilized to measure an input power supplied to the power supply unit. The multimeter is utilized to measure an output power of PSU. The microcontroller unit is configured for automatically switching the plurality of switches for enabling the multimeter to measure the output power of power supply. The data processing device is utilized to read data measured from the power meter and the multimeter and calculate a conversion efficiency of the PSU. | 2010-12-30 |
20100327902 | Power saving termination circuits for dram modules - The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes significant less power relative to prior art termination resistors at low frequency and behave as a matching impedance at high frequency. Similar methods and structures are also applicable for PCIe, SATA, or MIPI differential interfaces. | 2010-12-30 |
20100327903 | CIRCUIT FOR CALIBRATING IMPEDANCE AND SEMICONDUCTOR APPARATUS USING THE SAME - A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal. | 2010-12-30 |
20100327904 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level. | 2010-12-30 |
20100327905 | Method and Apparatus for Providing a Non-Volatile Programmable Transistor - A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function. | 2010-12-30 |
20100327906 | INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS - A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal. | 2010-12-30 |
20100327907 | ENHANCED PERMUTABLE SWITCHING NETWORK WITH MULTICASTING SIGNALS FOR INTERCONNECTION FABRIC - In one embodiment, an integrated circuit has an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. An (i−1)-th level of conductors comprising I | 2010-12-30 |
20100327908 | METHOD AND APPARATUS FOR DIE TESTING ON WAFER - An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second conductors, and the switch circuits for selectively connecting the bond pads to the second conductors to provide bi-directional connections between the bond pads on opposite sides of the substrate and isolating the bond pads from the functional core logic. | 2010-12-30 |
20100327909 | Keeper circuit - Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels. | 2010-12-30 |
20100327910 | Interface device and interface system - An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line. | 2010-12-30 |
20100327911 | Semiconductor Device and a Display Device - The invention provides a low cost and high performance functional circuit by reducing time required for the repetition of logic synthesis and routing of layout in a functional circuit design. A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. By forming the standard cell in this manner, a ratio that the gate delay occupies in the delay time of a functional circuit can be relatively increased. Therefore, even when wiring capacitance after the routing of layout is not estimated at high precision in advance, an operating frequency can be obtained at high precision in the logic synthesis as long as a gate delay of each standard cell can be estimated at high precision. That is, a reliability of the logic synthesis result is improved, therefore, the logic synthesis and an automatic routing of layout are not required to be repeated, which can shorten the design period. | 2010-12-30 |
20100327912 | DIGITAL PHASE-LOCKED LOOP AND DIGITAL PHASE-FREQUENCY DETECTOR THEREOF - A digital phase-locked loop and a digital phase-frequency detector thereof are provided. The digital PFD includes a divisor switch unit, a low-resolution phase-error detecting unit, an accumulating unit, a high-resolution phase-error detecting unit, a constant unit, and a selector. The divisor switch unit receives and removes partial pulses of a feedback signal for obtaining a feedback clock. The low-resolution phase-error detecting unit detects phase error between a reference signal and the feedback clock to obtain a phase-error pulse width. The accumulating unit accumulates the feedback signal during the phase-error pulse width for obtaining an output selection signal. The high-resolution phase-error detecting unit detects phase error between the reference signal and the feedback signal to obtain a phase-error value. The constant unit provides at least one constant value. The selector selects and outputs one of the phase-error value and the constant value according to the output selection signal. | 2010-12-30 |
20100327913 | DETECTION OF BAD CLOCK CONDITIONS - There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal. | 2010-12-30 |
20100327914 | Accurate Hysteretic Comparator and Method - A hysteretic comparator is proposed for comparing input signals and producing an output signal VOT with a hysteresis window V | 2010-12-30 |
20100327915 | SEMICONDUCTOR DEVICE AND METHOD FOR RESETTING THE SAME - An object is to provide a semiconductor device within which a signal which can be used as a reset signal or a mode signal is produced at an arbitrary timing to reduce the number of pads of the semiconductor device. To achieve the object, in a semiconductor device ( | 2010-12-30 |
20100327916 | FREQUENCY SYNTHESIZER NOISE REDUCTION - A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (T | 2010-12-30 |
20100327917 | OUTPUT DEVICE AND TEST APPARATUS - An output device includes a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal, and a controller. The noise driver (i) sets an output end thereof at high impedance when not supplied with an enable signal, and (ii) varies an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The controller controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched. | 2010-12-30 |
20100327918 | HIGH CURRENT EMITTER DRIVE UNIT CELL - A unit cell for a Read-In Integrated Circuit employs a signal sampling circuit with a voltage input controlled by a first switch, a capacitor charged by the voltage input and a linear amplifier connected to the capacitor. An output through a second switch samples the capacitor as the input signal for a transistor cascade for emitter current supply incorporating a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel resistor. The second transistor is maintained in saturation for a first portion of the input signal range with the first transistor acting as a source follower for that range. Linear current flow through the resistor results allowing high resolution control in the low current range. The second transistor departs saturation in a second portion of the range for the input signal resulting in saturation mode square-law behavior dominating the first transistor which, in turn, causes a rapid increase in current through its channel in response to higher input signal level thereby allowing a lower resolution but higher current for emitter drive at higher temperatures. | 2010-12-30 |
20100327919 | DIFFERENTIAL AMPLIFIER CIRCUIT - A differential amplifier main circuit amplifies, while first voltage is applied to drains of first and second transistors via a load circuit and second voltage is applied to source of third transistor, a difference between voltages applied to gates of the first and second transistors, and outputs it from a connection between the load circuit and drains of the first or second transistor. A voltage application circuit applies voltage to the gate of the third transistor so that a current between the source and drain thereof to have a predetermined magnitude. Gates of transistors of the application circuit are connected to a second common-connection of drains thereof to which the first voltage is applied via a load, the second voltage is applied to a first common-connection of sources of the transistors, and a connection of the second common-connection and the load is connected to the gate of the third transistor. | 2010-12-30 |
20100327920 | Mixing Waveforms - A local oscillator circuit for a signal transmitter or receiver, the circuit comprising: an input for receiving a master oscillating signal from a master oscillator; and signal processing circuitry configured to be clocked by the master oscillating signal to generate a local oscillator signal, the signal processing circuitry being such that the local oscillator signal has substantially no harmonic content at any integer multiple of the frequency of the master oscillator signal, which oscillates at (2n+1)/2 times the frequency of the generated local oscillator signal, with n being a positive integer. | 2010-12-30 |
20100327921 | CIRCUIT ARCHITECTURE FOR EFFECTIVE COMPENSATING THE TIME SKEW OF CIRCUIT - A circuit architecture for effective compensating the time skew of circuit is disclosed. The circuit architecture comprises a required compensation circuit, two duplicated circuits, and a time skew detection and compensation circuit, wherein these duplicated circuits are the duplicates of the required compensation circuit. A differential of logic 0 and logic 1 signals are simultaneously inputted into two duplicated circuits to output a first detection signal and a second detection signal, then the time skew detection and compensation circuit detects the time skew between a first detection signal and a second detection signal so as to generate a compensation signal to the required compensation circuit. Accordingly, the time skew existed in the required compensation circuit can be reduced or eliminated. | 2010-12-30 |
20100327922 | INTEGRATED CIRCUIT DEVICE AND DATA TRANSMISSION SYSTEM - An integrated circuit device includes: a plurality of I/O cells coupled to an external apparatus; a control signal generator configured to detect a phase relationship among data signals respectively input into the plurality of I/O cells and to generate control signals based on the phase relationship; and a drive controller circuit configured to control the driving of the I/O cells in response to the control signals. | 2010-12-30 |
20100327923 | BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency. | 2010-12-30 |
20100327924 | WAVEFORM EQUALIZATION CIRCUIT AND WAVEFORM EQUALIZATION METHOD - A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit. | 2010-12-30 |
20100327925 | CALIBRATING MULTIPLYING-DELAY-LOCKED-LOOPS (MDLLS) - Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle. | 2010-12-30 |
20100327926 | DLL circuit and semiconductor device having the DLL circuit - To include a phase-difference-amount detecting circuit that detects an amount of phase difference between an external clock signal and a replica clock signal, a variable delay circuit that delays the external clock signal based on the amount of phase difference to generate an internal clock signal, and a replica buffer that delays the internal clock signal to generate the replica clock signal. According to the present invention, the variable delay circuit is controlled based on the amount of phase difference, instead of being controlled based on whether the phase of the replica clock signal is advanced or delayed with respect to the external clock signal. Accordingly, even when the amount of phase difference is large, a DLL circuit can be locked at a high speed. | 2010-12-30 |
20100327927 | METHOD AND SYSTEM FOR CONTROLLING RADIO FREQUENCY POWER - A method for controlling pulsed power that includes measuring a first pulse of power from a power amplifier to obtain data. The method also includes generating a first signal to adjust a second pulse of delivered power, the first signal correlated to the data to minimize a power difference between a power set point and a substantially stable portion of the second pulse. The method also includes generating a second signal to adjust the second pulse of delivered power, the second signal correlated to the data to minimize an amplitude difference between a peak of the second pulse and the substantially stable portion of the second pulse. | 2010-12-30 |
20100327928 | METHOD AND APPARATUS TO IMPROVE AND CONTROL THE PROPAGATION DELAY IN A CURRENT SLEWING CIRCUIT - A circuit for independently controlling slew and propagation delay of a current DAC is provided. The circuit applies dual slope technique with feed-back control the gate (or control electrode) of a switching transistor to make propagation delay independent control from rise/fall slew rate. This allows one to adjust propagation delay and current slew rate separately to achieve better performance. | 2010-12-30 |
20100327929 | PREDETERMINED DUTY CYCLE SIGNAL GENERATOR - Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number. | 2010-12-30 |
20100327930 | SCHMITT TRIGGER WITH GATED TRANSITION LEVEL CONTROL - A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level. | 2010-12-30 |
20100327931 | Wideband programmable phase shifting circuit - The wideband programmable phase shifting circuitry includes a charge pump, a comparator, and a voltage reference generator block. An input signal controls the charge pump which charges and discharges a capacitor connected to an output of the charge pump. The comparator continuously compares the voltage across the capacitor with a reference voltage, ratio of V | 2010-12-30 |
20100327932 | FEEDBACK SYSTEM WITH IMPROVED STABILITY - Techniques for improving stability of a feedback system are described. In an exemplary design, the feedback system includes a forward path and a feedback path. The forward path receives an input signal and a rotated feedback signal and provides an output signal having a phase shift. The feedback path receives the output signal, generates a feedback signal, and rotates the feedback signal to obtain the rotated feedback signal having at least part of the phase shift removed. In another exemplary design, the feedback system includes a forward path and a feedback loop. The forward path receives a combined signal and provides an output signal having a phase shift. The feedback loop generates an error signal based on an input signal and the output signal, generates the combined signal based on the error signal and the input signal, and performs phase rotation to remove at least part of the phase shift. | 2010-12-30 |
20100327933 | ELECTRONIC DEVICE FOR MICROWAVE APPARATUSES ONBOARD A SATELLITE - The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment. | 2010-12-30 |
20100327934 | DIGITAL DELAY LINES - Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters. | 2010-12-30 |
20100327935 | DELAY CIRCUIT OF SEMICONDUCTOR DEVICE - A delay circuit of a semiconductor device increases its delay time as an external voltage increases. The delay circuit can also ensure a desired delay time according to an external voltage, without additional delay circuits. The delay circuit of the semiconductor device includes a first delay unit, and a second delay. The second delay unit has a propagation delay characteristic different from that of the first delay unit with respect to variation of a power supply voltage, wherein the first delay unit is supplied with a first power supply voltage independent of variation of an external voltage, and the second delay unit is supplied with a second power supply voltage dependent on the variation of the external voltage. | 2010-12-30 |
20100327936 | METHOD AND APPARATUS FOR DETERMINING WITHIN-DIE AND ACROSS-DIE VARIATION OF ANALOG CIRCUITS - Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property. | 2010-12-30 |
20100327937 | CONFIGURABLE PULSE GENERATOR - The described embodiments provide a circuit that can be configured as a pulse generator or as an oscillator. The circuit includes a pulse generator circuit and a test circuit that is coupled to the pulse generator circuit. In the described embodiments, an disable signal is coupled to the test circuit. When the disable signal is asserted, the test circuit is disabled, and the pulse generator circuit outputs pulses of a predetermined duration. In contrast, when the disable signal is deasserted, the test circuit is enabled, and the pulse generator circuit outputs an oscillating signal. | 2010-12-30 |
20100327938 | SYSTEM AND METHOD FOR CLOCK CONTROL FOR POWER-STATE TRANSITIONS - Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement ( | 2010-12-30 |
20100327939 | MIXER CIRCUIT - A double balanced mixer circuit comprising a differential pair of first amplifier elements responsive to an RF differential input signal, double differential pairs of second amplifier elements responsive to an LO differential input signal, and differential output terminals connected with the second amplifier paths. Coupling elements provide first and second parallel DC connections between DC voltage supply rails for the first and the double second amplifier paths respectively and a series RF connection of the first and second amplifier paths between the supply rails so as to produce a mixed differential amplified signal at the differential output terminals. The coupling elements include respective transmission lines in the first amplifier paths connected between one of the DC voltage supply rails and respective ones of the first amplifier elements and a common transmission line connected between the other of the DC voltage supply rails and both the first amplifier elements. | 2010-12-30 |
20100327940 | EMBEDDED PHASE NOISE MEASUREMENT SYSTEM - Phase noise detection systems for a device under test (DUT) are provided that can be embedded within a chip. According to one embodiment, the embedded phase noise detection system can include an active delay line cell, a phase shifter, and a phase detector. The active delay line and phase shifter separately receive the output signal of the DUT. The phase detector can include a double-balanced mixer followed by an active RC filter. The double-balanced mixer receives, as input, the outputs from the active delay line and phase shifter and can produce different dc voltages proportional to the difference from the input phase quadrature. An auto-adjustment circuit can also be included to help the input signal from the phase shifter to the mixer maintain quadrature. | 2010-12-30 |
20100327941 | Transimpedance Amplifier Input Stage Mixer - A Gilbert cell mixer design is disclosed. Instead of using a differential transconductance stage as typically done, the design employs a differential transimpedance amplifier input stage. By utilizing a transimpedance input stage to the Gilbert mixer, feedback is used to obtain higher linearity without sacrificing noise performance. The transimpedance input stage supplies a current signal to the cascode connected Gilbert switching quad, so the transimpedance amplifier output is taken from the collector of the transimpedance amplifier output transistor, instead of the emitter as normally done with transimpedance amplifiers. | 2010-12-30 |
20100327942 | SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD - A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor. | 2010-12-30 |
20100327943 | ILLUMINATED PUSHBUTTON SWITCH WITH ELECTRONIC LATCHING AND BLINKING FEATURE - Within an illuminating pushbutton switch, an electronic circuit replaces an electromagnetic holding coil for latching or releasing a state of the illuminated pushbutton switch, and further provides blinking functionality. The electronic circuit includes inputs receiving set, reset and toggle control signals, outputs delivering open, closed and blink control signals, latch logic controlled by the set and reset control signals and delivering signals maintaining the illuminated pushbutton switch in either an open or closed state, and a frequency divider and oscillator coupled together to deliver a blink control signal. The electronic circuit fits within the illuminated pushbutton switch housing in space sized to hold two snap action switching devices without increase in the length, weight or mounting depth of the illuminated pushbutton switch. The inputs and outputs are coupled to external pins from the illuminated pushbutton switch and may be remotely controlled. | 2010-12-30 |
20100327944 | Signal Buffer Amplifier - A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter. | 2010-12-30 |
20100327945 | PORTABLE OBJECT WITH SELF SWITCHING DEVICE - A portable electronic device | 2010-12-30 |
20100327946 | BOOST MECHANISM USING DRIVER CURRENT ADJUSTMENT FOR SWITCHING PHASE IMPROVEMENT - System and method for providing a boost current to a switching transistor gate is disclosed. A boost capacitor precharged to a voltage level above a gate-source voltage is coupled to a switching transistor gate at the beginning of a switch-on phase. The boost capacitor is decoupled from the switching transistor gate when a boost capacitor voltage falls below the gate-source voltage and is again precharged to the voltage level above the gate-source voltage. A second-phase resistance is coupled between a supply voltage and the switching transistor gate. The second-phase resistance value is selected based upon a current peak detected in the switching transistor. A switch-off capacitor precharged to a voltage level below the gate-source voltage may be coupled to the switching transistor gate at the beginning of a switch-of phase. | 2010-12-30 |
20100327947 | Circuit and Method for Controlling the Secondary FET of Transformer Coupled Synchronous Rectified Flyback Converter - A secondary FET | 2010-12-30 |
20100327948 | Switching Circuit - A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complimentary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output port is also provided. | 2010-12-30 |
20100327949 | ELECTRIC POWER CONVERTER - An electric power converter has a semiconductor module and a capacitor. The positive side semiconductor module has a positive terminal and the 1st intermediate terminal while the negative side semiconductor module has a negative terminal and the 2nd intermediate terminal. These terminals are formed in projected forms. The positive terminal and the negative terminal are connected to the capacitor by a positive bus bar and a negative bus bar, respectively. The 1st intermediate terminal and the 2nd intermediate terminal are connected each other by an intermediate bus bar. The positive and the negative side semiconductor modules, the capacitor, the positive, the negative and the intermediate bus bars constitute one closed circuit. The direction of the each current that flows to each of the main part portion, the positive, the negative and the intermediate bus bars opposes the neighboring current when a closed current flows in the closed circuit. | 2010-12-30 |
20100327950 | MINIMIZING NON-LINEARITY ERRORS - A system and method for minimizing non-linearity errors induced in output drive voltage of a transmitter circuit due to on-chip process, voltage, and temperature (PVT) variations. The system including an oscillator for converting an input reference bias voltage into a clock output signal, where the input reference bias voltage varies in response to PVT variations. Also included is a counter for counting the clock output signal and generating a count value corresponding to the clock output of the oscillator. A comparison module operatively coupled to the counter compares the count value with a pre-simulated count value to generate an error signal. Based on the error signal generated by the comparison module, a correction logic adjusts an output drive signal of the transmitter circuit making it immune to PVT variations. | 2010-12-30 |
20100327951 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a first circuit, a second circuit and a control circuit. The first circuit is configured by a first MOS transistor, and a threshold voltage of the first MOS transistor is a first threshold voltage. The second circuit has same logic as the first circuit, and is configured by a second MOS transistor. A threshold voltage of the second MOS transistor is a second threshold voltage, and the second threshold voltage is lower than the first threshold voltage. The control circuit makes one of the first circuit and the second circuit operate depending on a temperature of a chip. The first circuit and the second circuit are installed in a chip. | 2010-12-30 |
20100327952 | Electronic System Capable of Compensating Process, Voltage and Temperature Effects - An electronic system includes an integrated circuit, powered by a first voltage, with a first device provided therein; a detection device coupled to the first device to detect an output deviation of the first device attributed to process, voltage and temperature (PVT) effects; and a compensation device coupled to the detection device, adjusting the first voltage in response to the output deviation and outputting the first voltage to the integrated circuit to compensate for the PVT effects. The electronic system further comprises a conversion device, coupled between the detection device and the compensation device, to generate an indication signal corresponding to the output deviation for the compensation device to adjust the first voltage. In addition, the compensation device may compare and amplify a difference between a voltage level of the indication signal and a reference to linearly adjust the first voltage for compensating for the PVT effects. | 2010-12-30 |
20100327953 | AUTOMATIC IMPEDANCE ADJUSTER AND CONTROL METHOD THEREOF - Provided are an automatic impedance adjuster and a control method thereof. The automatic impedance adjuster includes: a pulse signal generating part for generating a pulse signal having a pulse width varied in response to a pulse width control signal; a signal processing part including a plurality of channels having a plurality of first input sensors and a pulse width correction channel having a second input sensor, not outputting the pulse signal when a touch object is in contact with the first and second input sensors, and outputting the pulse signal when the touch object is not in contact with the first and second input sensors; and a controller for outputting a non-contact state when the pulse signal is detected and outputting a contact state when the pulse signal is not detected during a normal mode, entering an automatic impedance adjustment mode to control the pulse width control signal when a pre-determined time elapses, and entering the automatic impedance adjustment mode to control the pulse width control signal when the pulse signal is not detected through all the plurality of channels or the pulse width correction channel. The automatic impedance adjuster includes a specific channel for checking an operating environment. When an operation signal of the specific channel is detected or operation signals of all the channels are detected, the automatic impedance adjustment operation is performed to prevent malfunction of the impedance adjustment operation. In addition, malfunction of a touch sensor due to variation of the operating environment can be prevented to improve operating reliability of the touch sensor. | 2010-12-30 |
20100327954 | SEMICONDUCTOR DEVICE - A semiconductor device includes internal voltage generating circuits, a switching circuit, load circuits, a control circuit. Each of the plurality of load circuits is supplied with voltage through the switching circuit from any one of the plurality of internal voltage generating circuits. The control circuit defines connecting combinations by the switch circuit. The control circuit supplies a control signal to the switch circuit, based on the control signal corresponding to the definitions of the connecting combinations. The control circuit allows switching the connecting combinations when the semiconductor device tests in a test mode. The control circuit prohibits switching the connecting combinations in a non-test mode. The switch circuit connects between each of m of the internal voltage generating circuits and each of n of the load circuits through a connecting combination which is selected, based on the control signal, from m | 2010-12-30 |
20100327955 | DISPLAY DEVICE AND ELECTRONIC DEVICE - It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced. | 2010-12-30 |
20100327956 | GRAPHENE DEVICE AND METHOD OF FABRICATING A GRAPHENE DEVICE - In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device. | 2010-12-30 |
20100327957 | METHOD AND SYSTEM TO FACILITATE CONFIGURABLE INPUT/OUTPUT (I/O) TERMINATION VOLTAGE REFERENCE - A method and system to facilitate configurable input/output (I/O) termination voltage reference in a transmitter or receiver. In one embodiment of the invention, the transmitter and receiver, each has a termination circuit to select a suitable termination reference voltage based on the desired coupling type. In one embodiment of the invention, the transmitter has a termination circuit coupled with a transmission driver and the transmitter selects only one of a supply voltage, a ground voltage and a half supply voltage as a termination voltage reference of the transmission driver. The receiver has a termination circuit to select either a supply voltage or a ground voltage as a termination voltage reference of the receiver. | 2010-12-30 |
20100327958 | Leakage Current Mitigation in a Semiconductor Device - A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device. | 2010-12-30 |
20100327959 | HIGH EFFICIENCY CHARGE PUMP - A charge pump circuit includes a first and second charge pumps. Each of the first and second charge pumps includes a boosting unit to respectively initialize and boost a voltage, a transmission transistor to transmit the boosting voltage to an output node, and a control unit to control the transmission transistor. The charge pump circuit has a higher voltage boosting efficiency and higher power efficiency. | 2010-12-30 |
20100327960 | INTEGRATED CIRCUIT OPERABLE IN A STANDBY MODE - An integrated circuit, comprises a wakeup terminal; a supply voltage terminal configured to receive a supply voltage; and a power control circuit. The power circuit comprises an enable circuit coupled to the wakeup terminal and configured to generate a voltage monitoring enable signal as a response to a wakeup signal received at the wakeup terminal, and a voltage monitoring circuit for generating a supply voltage level indication signal. The voltage monitoring circuit is coupled to the supply voltage terminal and comprises an operation switch controlled by the voltage monitoring enable signal. The voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and set the supply voltage level indication signal accordingly. The integrated circuit further comprises processing circuitry, with the supply voltage level indication signal controlling the switching between a normal operation state and a standby state of the processing circuitry. | 2010-12-30 |
20100327961 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY VOLTAGE CONTROL SYSTEM - A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit. | 2010-12-30 |
20100327962 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a reference voltage generating block, a circuit block, and a transmission line. The reference voltage generating block generates a first reference voltage and generates and outputs a digital code corresponding to the level of the first reference voltage. The circuit block converts the digital code into a second reference voltage and uses the second reference voltage for operation related to the function of the semiconductor integrated circuit. The transmission line is connected between the reference voltage generating block and the circuit block to allow transmission of the digital code to the circuit block. | 2010-12-30 |
20100327963 | Active Snubbers Providing Acceleration, Damping, and Error Correction - An active snubber operates, in part, to compel switching components, such as switch-mode power supplies and converters, to attain desired values rapidly, albeit temporarily, during which time there is sufficient time for a power supply's internal regulation system to sustain these values independently. The invention can dampen ringing, accelerate response time, and correct erroneous responses of the output of the switching converter. In one embodiment, the active snubber, which is operably connected to the output of a switching component that has a switching or ringing frequency, f | 2010-12-30 |
20100327964 | Semiconductor device and method of removing semiconductor device noise - A semiconductor device includes: a noise detecting circuit; an input signal delaying circuit; and a mask circuit. The noise detecting circuit detects noise superimposed on an input signal and outputs a mask signal during a predetermined time period. The input signal delaying circuit delays the input signal and outputs a delay signal thereof. The mask circuit outputs an output signal in which the delay signal is masked based on the mask signal. | 2010-12-30 |
20100327965 | RECEIVER FILTERING DEVICES, SYSTEMS, AND METHODS - Exemplary embodiments of the invention disclose receiver baseband filtering. In an exemplary embodiment, the filter device may comprise a continuous-time filter and a discrete-time filter operably coupled to the continuous time-filter. The discrete-time filter may include a passive infinite impulse response filter operably coupled between the continuous-time filter and an amplifier. The discrete-time filter may also include an active infinite impulse response filter operably coupled between an output of the amplifier and an input of the amplifier. The discrete-time filter may be configured to combine an output of the active infinite impulse response filter and an output of the passive infinite impulse response filter to form a composite signal. Furthermore, the amplifier may be configured to receive and amplify the composite signal. | 2010-12-30 |
20100327966 | SEMICONDUCTOR DEVICE HAVING CIRCUIT BLOCKS WITH MUTUALLY THE SAME CIRCUIT CONFIGURATION - To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area. | 2010-12-30 |
20100327967 | TEST APPARATUS, DEMODULATION APPARATUS, TEST METHOD, DEMODULATION METHOD AND ELECTRIC DEVICE - Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase. | 2010-12-30 |