52nd week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100327268 | ORGANIC EL DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, an organic EL device includes a pixel electrode, an organic layer disposed above the pixel electrode, a counter-electrode disposed above the organic layer, and an oxide layer disposed between the pixel electrode and the organic layer, the oxide layer including a first region formed with a first film thickness over a first area and a second region formed with a second film thickness which is less than the first film thickness, over a second area which is less than the first area. | 2010-12-30 |
20100327269 | EMISSIVE TRIARYLS - Disclosed herein are compounds represented by Formula 1. Compositions and light-emitting devices related thereto are also disclosed. | 2010-12-30 |
20100327270 | NOVEL MATERIALS FOR ORGANIC ELECTROLUMINESCENT DEVICES - The present invention relates to the compounds of the formula (1) and to organic electroluminescent devices, in particular blue-emitting devices, in which these compounds are used as host material in the emitting layer and/or as electron-transport material. | 2010-12-30 |
20100327271 | COMPOSITION AND ORGANIC PHOTOELECTRIC CONVERTER USING THE SAME - An organic photoelectric converter having excellent photoelectric conversion efficiency can be produced by using a composition containing a polymer compound A having a repeating unit represented by formula (1) and a polymer compound B having a repeating unit represented by formula (2): | 2010-12-30 |
20100327272 | Liquid Crystal Display Device And Method For Fabricating The Same - An LCD device and a method for fabricating the same is disclosed that improves a yield by decreasing processing time. The LCD device includes gate and data lines formed substantially perpendicular to each other on a substrate and defining a unit pixel region; a thin film transistor formed at a crossing of the gate and data lines; an active layer formed over the gate line, the data line, and the thin film transistor; an organic resin formed on a portion of a gate insulating layer not including the gate line, the data line, and the thin film transistor; a passivation layer formed on an entire surface of the substrate including the thin film transistor; and a pixel electrode, formed in the unit pixel region, the pixel electrode being connected with a drain electrode of the thin film transistor. | 2010-12-30 |
20100327273 | DITHIENOTHIOPHENE DERIVATIVES - An organic compound represented by the following general formula (I) wherein n is an integer from 1 to 500, inclusive, and R1 and R2 are each independently a moiety having an atom length of from about 8 atoms to about 20 atoms. | 2010-12-30 |
20100327274 | ORGANIC LIGHT-EMITTING DEVICE - An organic blue-light-emitting device having a high emission efficiency and a long continuous driving lifetime is provided. An organic light-emitting device | 2010-12-30 |
20100327275 | ORGANIC EL PANEL AND ITS MANUFACTURING METHOD - An organic EL panel includes a light-emitting part including one or a plurality of organic EL elements on a substrate and having a sealing structure sealing the light-emitting part. The organic EL element includes a light-emitting layer, an organic layer formed on a first electrode formed directly, or via another layer, on the substrate, and a second electrode formed on the organic layer. The organic EL panel includes a coating film formed on the substrate, directly at least on the second electrode, so as to coat the light-emitting part. The coating film is made of an amorphous organic material and has a thickness absorbing a surface irregularity of the contact object contacted by the surface of the coating film. | 2010-12-30 |
20100327276 | Method and system for passivation of defects in mercury cadmium telluride based optoelectric devices - Apparatus and method to improve the operating parameters of HgCdTe-based optoelectric devices by the addition of hydrogen to passivate dislocation defects. A chamber and a UV light source are provided. The UV light source is configured to provide UV radiation within the chamber. The optoelectric device, which may comprise a HgCdTe semiconductor, is placed into the chamber and may be held in position by a sample holder. Hydrogen gas is introduced into the chamber. The material is irradiated within the chamber by the UV light source with the device and hydrogen gas present within the chamber to cause absorption of the hydrogen into the material. | 2010-12-30 |
20100327277 | SEMICONDUCTOR DEVICE WITH A BULK SINGLE CRYSTAL ON A SUBSTRATE - Device and method of forming a device in which a substrate ( | 2010-12-30 |
20100327278 | LAMINATED STRUCTURES - Laminated structures having improved optical gain are provided. In one embodiment, a laminated structure includes a first cladding layer having at least two barrier layers which have different energy band gaps, an active layer formed on the first cladding layer and having an active layer energy band gap, and a second cladding layer formed on the active layer and including at least two barrier layers which have different energy band gaps. The first cladding layer and the second cladding layer may be doped with a different type of dopant. | 2010-12-30 |
20100327279 | MICRO VACUUM GAUGE - A micro vacuum gauge includes a substrate, a floating structure that is held above the substrate by a supporting structure extending from the substrate in a state where the floating structure is thermally isolated from the substrate, a heat generator that is arranged in the floating structure to generate heat, and a temperature sensor that is arranged in the floating structure to measure a difference in temperature between the substrate and the floating structure. A second member having a lower emissivity than a first member surrounding the heat generator and the temperature sensor is formed at least on a surface of the floating structure by being joined to the first member. | 2010-12-30 |
20100327280 | SCALING OF BIPOLAR TRANSISTORS - Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor; scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor; determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling; and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design to generate a stress compensated scaled design of the bipolar transistor. | 2010-12-30 |
20100327281 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current. | 2010-12-30 |
20100327282 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A semiconductor device includes: a substrate; a p-type organic transistor including an organic semiconductor layer arranged on or above the substrate; and an n-type inorganic transistor including an inorganic semiconductor layer arranged on or above the organic transistor, wherein a channel region of the inorganic transistor overlaps a channel region of the organic transistor at least partially in a plan view. | 2010-12-30 |
20100327283 | THIN FILM TRANSISTOR SUBSTRATE AND FABRICATING METHOD THEREOF - The present invention relates to a thin film transistor substrate. The thin film transistor according to one embodiment of the present invention comprises: a gate wire and a data wire formed to cross each other on an insulating substrate and define a pixel area; a thin film transistor formed on the intersection of the gate wire and the data wire; an inorganic insulating layer covering the thin film transistor and having a surface that a prominence and depression pattern formed on; and a reflective layer provided on the prominence and depression pattern. Thus, the present invention provides a thin film transistor substrate which reduces the time required in the process and enhance the productivity. | 2010-12-30 |
20100327284 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes. | 2010-12-30 |
20100327285 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE - Disclosed is a method of manufacturing a semiconductor device including: forming a photothermal conversion layer in a second area where a semiconductor layer is formed other than a first area where line is formed; and heating the semiconductor layer with the photothermal conversion layer by irradiating light on the first area and the second area. | 2010-12-30 |
20100327286 | LIGHT SENSING CIRCUIT, BACKLIGHT CONTROL APPARATUS HAVING THE SAME, AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME - A light sensing circuit capable of enhancing a reliability by lowering a dependency on a temperature change without using a resistor, a backlight control apparatus having the same, and an LCD device having the same. The light sensing circuit includes a first MOS-transistor; and a second MOS-transistor serially connected to the first MOS-transistor between a first power terminal and a ground terminal, in which a second power terminal is connected to each gate terminal of the first MOS-transistor and the second MOS-transistor, and an optical amount detecting terminal is connected to a common connection point between a drain terminal of the first MOS-transistor and a source terminal of the second MOS-transistor. | 2010-12-30 |
20100327287 | Display Device And Manufacturing Method Of The Same - A display device includes a sequentially stacked body formed of a gate signal line, an insulation film, a semiconductor layer and a conductor layer on a substrate. The conductive layer forms a drain electrode and a source electrode of a thin film transistor which are arranged with a channel region of the semiconductor layer therebetween, and one of the drain and source electrode is formed in an approximately U shape having an open-ended one end side and a connecting portion on another end side so that the one electrode surrounds a distal end portion of another electrode as viewed in a plan view, and a projecting portion is formed on a side of the connecting portion opposite to the another electrode. | 2010-12-30 |
20100327288 | TRENCH SCHOTTKY DIODE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure. | 2010-12-30 |
20100327289 | FLAT DISPLAY PANEL, UV SENSOR AND FABRICATION METHOD THEREOF - A UV sensor comprises a silicon-rich dielectric layer with a refractive index in a range of about 1.7 to about 2.5 for serving as the light sensing material of the UV sensor. The fabrication method of the UV sensor can be integrated with the fabrication process of semiconductor devices or flat display panels. | 2010-12-30 |
20100327290 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF DISPLAY DEVICE, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE - A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced. A method for manufacturing a semiconductor device which includes forming an ion-doped layer at a predetermined depth from a surface of a single-crystal semiconductor substrate and forming a first insulating layer over the single-crystal semiconductor substrate; forming a second insulating layer over part of an insulating substrate and forming a non-single-crystal semiconductor layer over the second insulating layer; bonding the single-crystal semiconductor substrate to a region of the insulating substrate where the second insulating layer is not formed, with the first insulating layer interposed therebetween; and forming a single-crystal semiconductor layer over the insulating substrate by separating the single-crystal semiconductor substrate at the ion-doped layer which acts as a separation surface so that the ion-doped layer is separated from the insulating substrate. | 2010-12-30 |
20100327291 | Single crystal group III nitride articles and method of producing same by HVPE method incorporating a polycrystalline layer for yield enhancement - In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article. | 2010-12-30 |
20100327292 | METHOD OF OBTAINING BULK MONO-CRYSTALLINE GALLIUM-CONTAINING NITRIDE, BULK MONO-CRYSTALLINE GALLIUM-CONTAINING NITRIDE, SUBSTRATES MANUFACTURED THEREOF AND DEVICES MANUFACTURED ON SUCH SUBSTRATES - The invention is related to a method of obtaining bulk mono-crystalline gallium-containing nitride, comprising a step of seeded crystallization of mono-crystalline gallium-containing nitride from supercritical ammonia-containing solution, containing ions of Group I metals and ions of acceptor dopant, wherein at process conditions the molar ratio of acceptor dopant ions to supercritical ammonia-containing solvent is at least 0.0001. According to said method, after said step of seeded crystallization the method further comprises a step of annealing said nitride at the temperature between 950° C. and 1200° C., preferably between 950° C. and 1150° C. | 2010-12-30 |
20100327293 | FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased. | 2010-12-30 |
20100327294 | LED PACKAGE STRUCTURE FOR INCREASING LIGHT-EMITTING EFFICIENCY AND CONTROLLING LIGHT-PROJECTING ANGLE AND METHOD FOR MANUFACTURING THE SAME - An LED package structure for increasing light-emitting efficiency and controlling light-projecting angle includes a substrate unit, a light-emitting unit, a light-reflecting unit and a package unit. The substrate unit has a substrate body and a chip-placing area disposed on a top surface of the substrate body. The light-emitting unit has a plurality of LED chips electrically disposed on the chip-placing area. The light-reflecting unit has an annular reflecting resin body surroundingly formed on the top surface of the substrate body by coating. The annular reflecting resin body surrounds the LED chips that are disposed on the chip-placing area to form a resin position limiting space above the chip-placing area. The package unit has a translucent package resin body disposed on the top surface of the substrate body in order to cover the LED chips. The position of the translucent package resin body is limited in the resin position limiting space. | 2010-12-30 |
20100327295 | LED PACKAGE STRUCTURE WITH EXTERNAL CUTTING CHAMFER AND METHOD FOR MANUFACTURING THE SAME - An LED package structure includes a substrate unit, a light-emitting unit, a light-reflecting unit and a package unit. The substrate unit has a substrate body and a chip-placing area, and the substrate body has a cutting chamfer formed on one side thereof. The light-emitting unit has a plurality of LED chips electrically disposed on the chip-placing area. The light-reflecting unit has an annular reflecting resin body surroundingly formed on the substrate body by coating. A distance between an outermost side of the annular reflecting resin body and an outermost side of the substrate body is between 0 and 1.5 mm, and the annular reflecting resin body surrounds the LED chips to form a resin position limiting space. The package unit has a translucent package resin body for covering the LED chips, and the position of the translucent package resin body is limited in the resin position limiting space. | 2010-12-30 |
20100327296 | DISPLAY APPARATUS - Provided is a display apparatus which can easily bond a drive panel and a sealing panel together. The drive panel includes organic electroluminescence devices on a substrate for drive and extracts light from the side of the organic electroluminescence devices. The sealing panel includes a color filter on a substrate for sealing. The drive panel and the sealing panel are disposed to face each other, and the whole facing surfaces of the drive panel and the sealing panel are bonded together with an adhesive layer. The adhesive layer is cured with at least heat, and is made of only one coating liquid or a combination of two or more coating liquids for curing. A temporary fixing portion is formed in an edge portion of the adhesive layer. The temporary fixing portion is made of, for example, an ultraviolet cure resin, and is formed so as to straddle between the sealing panel and the drive panel to align their relative positions. | 2010-12-30 |
20100327297 | ORGANIC EL DISPLAY PANEL - An organic EL display panel comprising a substrate and an organic light-emitting element R emitting red light, an organic light-emitting element G emitting green light and an organic light-emitting element B emitting blue light which are arranged on the substrate, wherein each of the organic light-emitting element has a concavely curved pixel electrode which is a reflective electrode, a functional layer formed with coating over the pixel electrode, an organic light emitting layer arranged on the functional layer, a counter electrode which is a transparent electrode arranged over the organic light emitting layer and a bank defining the functional layer formed with coating, the element R, the element G and the element B have different amount of the functional layer and the element R, the element G and the element B have different curvature radius of the concavely curved pixel electrode. | 2010-12-30 |
20100327298 | LIGHT-EMITTING ELEMENT AND METHOD OF MAKING THE SAME - A light-emitting element includes a semiconductor substrate, a light emitting portion including an active layer sandwiched between a first cladding layer of a first conductivity type and a second cladding layer of a second conductivity type different from the first conductivity type, a reflective portion provided between the semiconductor substrate and the light emitting portion for reflecting light emitted from the active layer, and a current spreading layer provided on the light emitting portion opposite to the reflective portion and including a concavo-convex portion on a surface thereof. The reflective portion includes a plurality of pair layers each including a first semiconductor layer and a second semiconductor layer different from the first semiconductor layer, and the first semiconductor layer has a thickness T | 2010-12-30 |
20100327299 | P-CONTACT LAYER FOR A III-P SEMICONDUCTOR LIGHT EMITTING DEVICE - A device includes a semiconductor structure with at least one III-P light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further includes a GaAs | 2010-12-30 |
20100327300 | CONTACT FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - Embodiments of the invention include a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. A contact disposed on the p-type region includes a transparent conductive material in direct contact with the p-type region, a reflective metal layer, and a transparent insulating material disposed between the transparent conductive layer and the reflective metal layer. In a plurality of openings in the transparent insulating material, the transparent conductive material is in direct contact with the reflective metal layer. | 2010-12-30 |
20100327301 | LED LIGHTING DEVICE - An LED lighting device includes a circuit board, a plurality of LED units, a waterproof layer and a middle layer. The LED units are disposed on the circuit board by surface mounted way. The light beam emitted from the LED units emits from the light-emitting surface. The waterproof layer wraps the circuit board and the LED units. The middle layer is located between the light-emitting surface and the water-proof layer. The middle layer extends from a direction of the LED units being disposed on the circuit board so that the middle layer fully covers the light-emitting surface. The light beams passing through the light-emitting surface enters into the waterproof layer via the middle layer. Thereby, the middle layer is located between the LED units and the waterproof layer to make the color of the light beam be more uniform. | 2010-12-30 |
20100327302 | LED MODULE - An LED module includes an LED and a lens located over and enclosing the LED. The lens includes a surface of incidence facing the LED for an incidence of light emitted from the LED and a surface of emission for an emission of the light out of the LED module. The surface of incidence has a convex spherical surface, and the surface of emission has a concave spherical surface corresponding to the convex spherical surface. The convex spherical surface refracts the light incident thereon to redirect the light to the concave spherical surface. The concave spherical surface spreads the light into a wide and uniform beam. The surface of emission further has a first cylinder extending downwardly from an outer edge of the concave spherical surface. A totally reflective coincoid extends downwards from the first cylinder to a bottom of the LED module. | 2010-12-30 |
20100327303 | Light-emitting diode lamp with uniform resin coating - LED lamps with a conformally coated LED chip and methods of manufacturing the same provides for LEDs having predictable color temperature. A conformally coated LED chip includes an LED chip with a conformal resin layer disposed over a portion of the LED chip. The LED lamp may have the characteristics of stable color temperature, substantially even and uniform distribution of illumination, and wide illumination angle. | 2010-12-30 |
20100327304 | ORGANIC EL DEVICE AND DESIGN METHOD THEREOF - An organic electroluminescence device including an organic electroluminescence display part which includes an anode, a cathode and at least a light-emitting layer disposed therebetween, and a lens which controls an optical path of light emitted from the light-emitting layer, wherein the organic electroluminescence device has a ratio of A to B (A/B) of greater than 1, where A denotes a light-extraction efficiency in terms of front brightness when the lens is placed on a surface from which the light is extracted, and B denotes a light-extraction efficiency in terms of front brightness when the lens is not placed on the surface from which the light is extracted, and wherein the organic electroluminescence device has a ratio of φ to a (φ/a) of 1.0 or greater, where a denotes the maximum length of a side of the light-emitting layer and φ denotes an effective diameter of the lens. | 2010-12-30 |
20100327305 | PHOTONIC STRUCTURES FOR EFFICIENT LIGHT EXTRACTION AND CONVERSION IN MULTI-COLOR LIGHT EMITTING DEVICES - A high efficiency light emitting diode (LED) comprised of a substrate, a buffer layer grown on the substrate (if such a layer is needed), a first active region comprising primary emitting species (PES) that are electrically-injected, a second active region comprising secondary emitting species (SES) that are optically-pumped by the light emitted from the PES, and photonic crystals, wherein the photonic crystals act as diffraction gratings to provide high light extraction efficiency, to provide efficient excitation of the SES, and/or to modulate the far-field emission pattern. | 2010-12-30 |
20100327306 | LED BASED LIGHT SOURCE FOR IMPROVED COLOR SATURATION - There is provided a light emitting device comprising a light source comprising at least one light emitting diode emitting visible radiation. The light emitting device further comprises a wavelength converting body comprising a first wavelength converting material, which is arranged to receive light emitted by said light source and which has an emission maximum in the range of from 600 to 700 nm. The first wavelength converting material comprises the elements Mg, Ge, O and Mn. A light emitting device according to the invention produces light having increased saturation of red colors. Moreover, long life and good color stability is achieved. | 2010-12-30 |
20100327307 | Optoelectronic Component - An optoelectronic component having a basic housing or frame and at least one semiconductor chip, specifically a radiation-emitting or-receiving semiconductor chip, in a cavity of the basic housing. In order to increase the efficiency of the optoelectronic component, reflectors are provided in the cavity in the region around the semiconductor chip. These reflectors are formed by virtue of the fact that a filling compound filled at least partly into the cavity is provided, the material and the quantity of the filling compound being chosen in such a way that the filling compound, on account of the adhesion force between the filling compound and the basic housing, assumes a form which widens essentially conically from bottom to top in the cavity, and the conical inner areas of the filling compound serve as reflector. | 2010-12-30 |
20100327308 | LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a light emitting apparatus includes a substrate; at least two distinct electrodes on the substrate, wherein the at least two distinct electrodes are spaced from each other; a light emitting device on one of the at least two distinct electrodes; lenses including a first lens and a second lens on the substrate, wherein the second lens is disposed on the first lens, wherein an outermost portion of the second lens is spaced from the substrate; and a supporting unit configured to directly contact the second lens, wherein the supporting unit is formed of a non-conductivity material. | 2010-12-30 |
20100327309 | VOLTAGE-OPERATED LAYERED ARRANGEMENT - A voltage-operated layered arrangement comprising a substrate ( | 2010-12-30 |
20100327310 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE/FLANGE HEAT SPREADER AND CAVITY IN FLANGE - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the flange, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, the flange extends upwardly from the post in the opening and extends laterally above the adhesive, the cavity extends into the opening and the base extends laterally from the post. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal. | 2010-12-30 |
20100327311 | GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND PRODUCTION METHOD THEREOF, AND LAMP - There are provided a group III nitride semiconductor light emitting device which is constituted of a substrate, an intermediate layer formed thereon having a favorable level of orientation properties, and a group III nitride semiconductor formed thereon having a favorable level of crystallinity, and having excellent levels of light emitting properties and productivity; a production method thereof; and a lamp,
| 2010-12-30 |
20100327312 | Group III nitride semiconductor light-emitting device and method for producing the same - A group III nitride semiconductor light-emitting device includes: a conductive support; a p-electrode positioned on the support, a p-type layer containing a group III nitride semiconductor, an active layer and an n-type layer having a first surface, which are positioned in turn on the p-electrode; and an n-electrode positioned on the first surface of the n-type layer. A groove is formed in the first surface of the n-type layer in a pattern such that the first surface of the n-type layer is continuous. A light-transmitting insulating film is formed on side surface and bottom surface of the groove. The groove has a depth at least reaching the p-type layer. The n-electrode is formed in wiring form. | 2010-12-30 |
20100327313 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate and a MOS transistor. The semiconductor substrate has the first main surface and the second main surface facing each other. The MOS transistor includes a gate electrode ( | 2010-12-30 |
20100327314 | Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method - This invention discloses an IGBT device with its collector formed with Ge/Al and associated method of fabrication. The collector is formed on the substrate layer, which is on the back of IGBT, and contains Ge and Al thin films. After thinning and etching the back side of IGBT substrate, Ge and Al are sequentially deposited to form Ge/Al thin films on the back surface of the substrate. An annealing process is then carried out to diffuse Al into Ge thin film layer to form a P-doped Ge layer functioning as the IGBT collector. The present invention is applicable to both non punch through IGBTs as well as punch through IGBTs. | 2010-12-30 |
20100327315 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR USE OF DRIVING PLASMA DISPLAY WITH USING SAME, AND PLASMA DISPLAY APPARATUS - A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density. | 2010-12-30 |
20100327316 | Method for Manufacturing an III-V Engineered Substrate and the III-V Engineered Substrate Thereof - Manufacturing an III-V engineered substrate involves providing a base substrate comprising an upper layer made of a first III-V compound with a <110> or a <111> crystal orientation, forming an intermediate layer comprising at least a buffer layer of a second III-V compound, wherein the intermediate layer is overlying and in contact with the upper layer of the base substrate. Then a pseudomorphic passivation layer made of a group IV semiconductor material is grown so as to be overlying and in contact with the intermediate layer. This can enable an unpinned interface. The substrate surface can be smoother, implying fewer problems from surface stress. It can be used in electronic devices such as metal-oxide-semiconductor field effect transistors (MOSFETs), high electron mobility transistors (HEMTs), tunneling field effect transistors (TFETs), and optoelectronic devices. | 2010-12-30 |
20100327317 | Germanium on insulator using compound semiconductor barrier layers - Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed. | 2010-12-30 |
20100327318 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer ( | 2010-12-30 |
20100327319 | CONTROL OF TUNNELING JUNCTION IN A HETERO TUNNEL FIELD EFFECT TRANSISTOR - Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current. | 2010-12-30 |
20100327320 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum. | 2010-12-30 |
20100327321 | Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling - A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions. | 2010-12-30 |
20100327322 | Transistor with Enhanced Channel Charge Inducing Material Layer and Threshold Voltage Control - High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region. | 2010-12-30 |
20100327323 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device includes: a plurality of channel structures extending in parallel in a first direction and comprising a plurality of channel layers that are alternatively stacked with a plurality of interlayer insulating layers over a substrate; a plurality of memory cells stacked along sidewalls of the channel structures and arranged in the first direction and a second direction crossing the first direction; and a plurality of word lines extending in parallel in the second direction and connected to the memory cells arranged in the second direction. | 2010-12-30 |
20100327324 | SEMICONDUCTOR CHIP - In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit. | 2010-12-30 |
20100327325 | MULTIDIRECTIONAL TWO-PHASE CHARGE-COUPLED DEVICE - A charge transfer device formed in a semiconductor substrate and including an array of electrodes distributed in rows and columns, wherein: each electrode is formed in a cavity with insulated walls formed of a groove which generally extends in the row direction, having a first end closer to an upper row and a second end closer to a lower row; and the electrodes of two adjacent rows are symmetrical with respect to a plane orthogonal to the sensor and comprising the direction of a row. | 2010-12-30 |
20100327326 | TWO-PHASE CHARGE-COUPLED DEVICE - A charge-coupled unit formed in a semiconductor substrate and including an array of identical electrodes forming rows and columns, wherein: each electrode extends in a cavity with insulated walls formed of a groove, oriented along a row, dug into the substrate thickness, and including, at one of its ends, a protrusion extending towards at least one adjacent row. | 2010-12-30 |
20100327327 | PHOTOSENSITIVE CHARGE-COUPLED DEVICE COMPRISING VERTICAL ELECTRODES - A charge transfer device formed in a semiconductor substrate and including an array of electrodes forming rows and columns, wherein: the electrodes extend, in rows, in successive grooves with insulated walls, disposed in the substrate thickness and parallel to the charge transfer direction. | 2010-12-30 |
20100327328 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME - A solid-state imaging device includes: a semiconductor substrate having a plurality of vertical transfer channel regions and a plurality of photoelectric conversion regions arranged in a matrix; a plurality of vertical transfer electrodes, each constructed of a gate electrode and a first metal light-shielding film, formed via a gate insulating film; a transparent insulating film formed in gaps existing between the vertical transfer electrodes above the vertical transfer channel regions; and a second metal light-shielding film formed via a first interlayer insulating film to cover at least the vertical transfer channel regions. | 2010-12-30 |
20100327329 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device includes a transistor, an element isolation insulating film, and a metal silicide layer. The transistor contains a gate electrode and an epitaxial crystal layer. The epitaxial crystal layer is formed on at least one side of the gate electrode in the semiconductor substrate and includes a facet having a different plane direction from a principal plane of the semiconductor substrate. The element isolation insulating film contains a lower layer and an upper layer. A horizontal distance between the upper layer and the gate electrode is smaller than a horizontal distance between the lower layer and the gate electrode. A part of the upper layer contacts with the facet. The metal silicide layer is formed on an upper surface of the epitaxial crystal layer and on a region of the facet above a contact portion of the facet with the upper layer. | 2010-12-30 |
20100327330 | SEMICONDUCTOR DEVICE WHEREIN A FIRST INSULATED GATE FIELD EFFECT TRANSISTOR IS CONNECTED IN SERIES WITH A SECOND FIELD EFFECT TRANSISTOR - A semiconductor device in which a first insulated gate field effect transistor ( | 2010-12-30 |
20100327331 | SEMICONDUCTOR DEVICE - The present invention proposes a dummy metal fill structure which makes it possible to reduce variations in transistor characteristics as much as possible even if mask misalignment occurs, as well as to ensure the intended planarizing effect of the metal CMP process. The dummy metal fill formed above the gate electrode extends in the gate length direction with both ends thereof protruding from a region corresponding to the gate electrode. Even if a mask for forming a wiring layer is misaligned and the position of the dummy metal fill is misaligned from an intended position, the shape of the dummy metal fill within a region of the gate electrode is kept symmetric with respect to the center of the gate electrode. | 2010-12-30 |
20100327332 | SOLID STATE IMAGING DEVICE - A solid state imaging device having a pixel area in which a plurality of light receiving elements are arranged, and a peripheral circuit area adjacent to the pixel area includes: a semiconductor substrate | 2010-12-30 |
20100327333 | SPIN TRANSPORT DEVICE - A spin transport device which comprises a channel, first and second insulating layers, a magnetization fixed layer, a magnetization free layer, first and second wirings, and satisfies at least one of following conditions A and B, Condition A: The first wiring includes a vertical portion which extends in a thickness direction of the magnetization fixed layer on the magnetization fixed layer, and a horizontal portion which extends from the vertical portion that is apart from the magnetization fixed layer side in a direction crossing the thickness direction of the magnetization fixed layer, and Condition B: The second wiring includes a vertical portion which extends in a thickness direction of the magnetization free layer on the magnetization free layer, and a horizontal portion which extends from the vertical portion that is apart from the magnetization free layer side in a direction crossing the thickness direction of the magnetization free layer. | 2010-12-30 |
20100327334 | FLOATING BODY MEMORY CELL APPARATUS AND METHODS - Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically isolating the body, the source, and the drain from the base, where the body is configured to store information. The base and the body include bulk semiconductor material. Additional apparatus and methods are described. | 2010-12-30 |
20100327335 | METHOD OF BUILDING COMPENSATED ISOLATED P-WELL DEVICES - Electrical device structures constructed in an isolated p-well that is wholly contained within a core n-well. Methods of forming electrical devices within an isolated p-well that is wholly contained within a core n-well using a baseline CMOS process flow. | 2010-12-30 |
20100327336 | Concentric or Nested Container Capacitor Structure for Integrated Circuits - Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly | 2010-12-30 |
20100327337 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer. | 2010-12-30 |
20100327338 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 2010-12-30 |
20100327339 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer. | 2010-12-30 |
20100327340 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film. | 2010-12-30 |
20100327341 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE STORAGE LAYERS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes first electrodes, a second and a third electrode, a first film, a first inter layer film, a second inter layer film, and a second film. The first electrodes each have a charge storage and a control electrode. The second and the third electrodes are formed above the semiconductor substrate. The first film is formed on each sidewall of the second and third electrodes and formed on the surface of the semiconductor substrate. The first inter layer film filled in a gap between the second and third electrodes. The second inter layer film filled in a gap between the first and second electrode. The second film is formed on the first to third gate electrodes, the first film and the first inter layer film, and a second inter layer insulating film to suppress diffusion of hydrogen atoms included in the first inter layer film. | 2010-12-30 |
20100327342 | TRANSIENT OVER-VOLTAGE CLAMP - In various embodiments, the invention relates to semiconductor structures, such as planar MOS structures, suitable as voltage clamp devices. Additional doped regions formed in the structures may improve over-voltage protection characteristics. | 2010-12-30 |
20100327343 | BOND PAD WITH INTEGRATED TRANSIENT OVER-VOLTAGE PROTECTION - In various embodiments, the invention relates to bond pad structures including planar transistor structures operable as over-voltage clamps. | 2010-12-30 |
20100327344 | Power Semiconductor Devices and Methods - The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this. | 2010-12-30 |
20100327345 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region. | 2010-12-30 |
20100327346 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved. | 2010-12-30 |
20100327347 | ELECTRONIC DEVICE INCLUDING A WELL REGION - An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region. | 2010-12-30 |
20100327348 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND POWER-SUPPLY DEVICE USING THE SAME - In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n | 2010-12-30 |
20100327349 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P | 2010-12-30 |
20100327350 | ELECTRONIC DEVICE INCLUDING AN INTEGRATED CIRCUIT WITH TRANSISTORS COUPLED TO EACH OTHER - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 2010-12-30 |
20100327351 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer provided therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region. | 2010-12-30 |
20100327352 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer interposed therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region. | 2010-12-30 |
20100327353 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate electrode | 2010-12-30 |
20100327354 | THIN FILM TRANSISTOR HAVING LONG LIGHTLY DOPED DRAIN ON SOI SUBSTRATE AND PROCESS FOR MAKING SAME - Methods and apparatus for producing a thin film transistor (TFT) result in: a glass or glass ceramic substrate; a single crystal semiconductor layer; a source structure disposed on the single crystal semiconductor layer; a drain structure disposed on the single crystal semiconductor layer; and a gate structure located with respect to the drain structure defining a lightly doped drain region therein, wherein a lateral length of the lightly doped drain region is such that the TFT exhibits a relatively low carrier mobility and moderate sub-threshold slope suitable for OLED display applications. | 2010-12-30 |
20100327355 | FRONT AND BACKSIDE PROCESSED THIN FILM ELECTRONIC DEVICES - This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits. | 2010-12-30 |
20100327356 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. | 2010-12-30 |
20100327357 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same. A plurality of gate patterns are formed over a first-conductivity type silicon layer of a silicon-on-insulator semiconductor substrate including a buried insulation layer, so as to be separated from each other. A plurality of silicon bodies are formed under the gate patterns, by removing a portion of the first-conductivity type silicon layer exposed between the gate patterns. A plurality of polysilicon spacers are formed over a sidewall of the silicon bodies, and each contains a second-conductivity type dopant. A contact plug is electrically connected to at least one of the polysilicon spacers. | 2010-12-30 |
20100327358 | SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU N-DOPED SEMICONDUCTOR MATERIAL - The PN junction of a substrate diode in a sophisticated semiconductor device may be formed on the basis of an embedded in situ N-doped semiconductor material thereby providing superior diode characteristics. For example, a silicon/carbon semiconductor material may be formed in a cavity in the substrate material, wherein the size and shape of the cavity may be selected so as to avoid undue interaction with metal silicide material. | 2010-12-30 |
20100327359 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n | 2010-12-30 |
20100327360 | FET With Replacement Gate Structure and Method of Fabricating the Same - A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material. | 2010-12-30 |
20100327361 | LOW COST SYMMETRIC TRANSISTORS - An integrated circuit is disclosed containing two types of MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. | 2010-12-30 |
20100327362 | NON-INSULATING STRESSED MATERIAL LAYERS IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level. | 2010-12-30 |
20100327363 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Sidewalls are formed on side surfaces of fin-shaped active regions, and then substrate regions surrounded by a device isolation groove are formed, where the widths of each substrate region in a channel length direction and in a channel width direction are respectively larger than those of the active region. Next, the sidewalls are removed, the device isolation groove and regions between the active regions are filled with an insulator film, and the insulator film is etched such that upper surfaces of the substrate regions are exposed. Next, an impurity is implanted in an upper portion of the substrate regions to form a punch through stopper diffusion layer, thereby forming fin transistors. | 2010-12-30 |
20100327364 | SEMICONDUCTOR DEVICE WITH METAL GATE - A semiconductor device includes: a substrate and an n-channel MIS transistor. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, wherein a first source/drain region is formed in the p-type semiconductor region and separated from each other. The n-channel MIS transistor includes a first gate insulating film on the p-type semiconductor region between the first source/drain regions. The n-channel MIS transistor further includes a first gate electrode having a stack structure formed with a gate dielectric, a first metal layer and a first compound layer, the first metal layer having a thickness less than 2 nm and having a work function of 4.3 eV or smaller, the first metal layer being formed on the metallic layer having a work function larger than 4.4 eV and the first compound layer containing Al and a second metal that is different from the first metal. | 2010-12-30 |
20100327365 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a gate insulating film over a semiconductor substrate; forming a mask that has an opening at a position corresponding to the gate insulating film formed in an NMOSFET forming region and covers the gate insulating film; forming a first metal layer over the gate insulating film disposed in the NMOSFET forming region and the mask formed in a PMOSFET forming region; and performing a heat treatment to thermally diffuse a metal material forming the first metal layer into the gate insulating film formed in the NMOSFET forming region. | 2010-12-30 |
20100327366 | SEMICONDUCTOR DEVICE - A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor. | 2010-12-30 |
20100327367 | CONTACT OPTIMIZATION FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS - By appropriately designing the geometric configuration of a contact level of a sophisticated semiconductor device, the tensile stress level of contact elements in N-channel transistors may be increased, while the tensile strain component of contact elements caused in the P-channel transistor may be reduced. | 2010-12-30 |