52nd week of 2011 patent applcation highlights part 16 |
Patent application number | Title | Published |
20110316081 | finFETS AND METHODS OF MAKING SAME - A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates. | 2011-12-29 |
20110316082 | SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF - An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate. | 2011-12-29 |
20110316083 | FET with Self-Aligned Back Gate - A back-gated field effect transistor (FET) includes a substrate, the substrate comprising top semiconductor layer on top of a buried dielectric layer on top of a bottom semiconductor layer; a front gate located on the top semiconductor layer; a channel region located in the top semiconductor layer under the front gate; a source region located in the top semiconductor layer on a side of the channel region, and a drain region located in the top semiconductor layer on the side of the channel region opposite the source regions; and a back gate located in the bottom semiconductor layer, the back gate configured such that the back gate abuts the buried dielectric layer underneath the channel region, and is separated from the buried dielectric layer by a separation distance underneath the source region and the drain region. | 2011-12-29 |
20110316084 | FET WITH REPLACEMENT GATE STRUCTURE AND METHOD OF FABRICATING THE SAME - A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material. | 2011-12-29 |
20110316085 | INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric layer is disposed over the substrate and the transistor. At least one of the isolation region or the pre-metal dielectric layer includes a O | 2011-12-29 |
20110316086 | Wafer Scale Package for High Power Devices - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages arc mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction. | 2011-12-29 |
20110316087 | MOS TRANSISTOR, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type. | 2011-12-29 |
20110316088 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The structure comprises a semiconductor substrate ( | 2011-12-29 |
20110316089 | SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION - A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure. | 2011-12-29 |
20110316090 | BOOST CONVERTER WITH INTEGRATED HIGH POWER DISCRETE FET AND LOW VOLTAGE CONTROLLER - A boost converter for high power and high output voltage applications includes a low voltage controller integrated circuit and a high voltage, vertical, discrete field effect transistor, both of which are packed in a single package on separate electrically isolated die pads. | 2011-12-29 |
20110316091 | Semiconductor Devices, Assemblies And Constructions - Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material. | 2011-12-29 |
20110316092 | Mask Rom - A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type. | 2011-12-29 |
20110316093 | SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION - A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off. | 2011-12-29 |
20110316094 | SEMICONDUCTOR DEVICES WITH ASYMMETRIC HALO IMPLANTATION AND METHOD OF MANUFACTURE - a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the least one of the at least one of the gate structures. | 2011-12-29 |
20110316095 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a silicon substrate, an SiO film, and a High-K film. The SiO film is first formed on the silicon substrate and then subjected to a nitridation process to obtain an SiON film from the SiO film. The nitridation process is performed such that nitrogen concentration in the SiO film decreases from an interface with the silicon substrate below and an interface with the High-K film above, and nitrogen having predetermined concentration or more is introduced in a thickness within a range of 0.2 nm to 1 nm from the interface with the silicon substrate. The SiON film is etched up to a depth to which nitrogen of the predetermined concentration or more is introduced. The High-K film is then formed on the SiON film. | 2011-12-29 |
20110316096 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O | 2011-12-29 |
20110316097 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS. | 2011-12-29 |
20110316098 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower sacrificial material used to form a lower cavity. The method further includes forming a cavity via connecting the lower cavity to an upper cavity. The cavity via is formed with a top view profile of rounded or chamfered edges. The method further includes forming an upper sacrificial material within and above the cavity via, which has a resultant surface based on the profile of the cavity via. The upper cavity is formed with a lid that is devoid of structures that would interfere with a MEMS beam, including: depositing a lid material on the resultant surface of the upper sacrificial material; and venting the upper sacrificial material to form the upper cavity such the lid material forms the lid which conforms with the resultant surface of the upper sacrificial material. | 2011-12-29 |
20110316099 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires from the lower wiring layer. The method further includes forming an electrode beam over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition. | 2011-12-29 |
20110316100 | MEMS MICROPHONE AND METHOD FOR MANUFACTURING SAME - A micro electro mechanical systems (MEMS) microphone, and a method of manufacturing the MEMS microphone having an interval between a membrane and a back plate, the interval being correctly adjusted by forming the membrane and the back plate after an air-gap forming portion on a silicon substrate. Since the membrane and/or the back plate are/is formed by electroless plating, a sacrificial layer is easily planarized, and a residual stress is easily removed or controlled. The MEMS microphone includes a silicon substrate in which a back chamber is formed and on which an air-gap forming portion is formed above the chamber by etching the silicon substrate to a predetermined depth above the chamber; a membrane formed on the air-gap forming portion of the silicon substrate or the silicon substrate; and a back plate that is formed on the air-gap forming portion or the silicon substrate so as to be spaced apart from the membrane, wherein an air gap is formed between the membrane and the back plate. | 2011-12-29 |
20110316101 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof. | 2011-12-29 |
20110316102 | STORAGE ELEMENT AND STORAGE DEVICE - A storage element includes: a storage layer configured to retain information based on a magnetization state of a magnetic material and include a perpendicular magnetization layer whose magnetization direction is in a direction perpendicular to a film plane, a non-magnetic layer, and a ferromagnetic layer that has an axis of easy magnetization along a direction in the film plane and has a magnetization direction inclined to a direction perpendicular to the film plane by an angle in a range from 15 degrees to 45 degrees, the storage layer being configured by stacking of the perpendicular magnetization layer and the ferromagnetic layer with intermediary of the non-magnetic layer and magnetic coupling between the perpendicular magnetization layer and the ferromagnetic layer; a magnetization pinned layer; and a non-magnetic intermediate layer. | 2011-12-29 |
20110316103 | STORAGE ELEMENT, METHOD FOR MANUFACTURING STORAGE ELEMENT, AND MEMORY - Disclosed herein is a storage element, including: a storage layer configured to retain information based on a magnetization state of a magnetic material; and a magnetization pinned layer configured to be provided for the storage layer with intermediary of a tunnel barrier layer, wherein the tunnel barrier layer has a thickness not less than or equal to 0.1 nm to not more than or equal to 0.6 nm and interface roughness less than 0.5 nm, and information is stored in the storage layer through change in direction of magnetization of the storage layer by applying a current in a stacking direction and injecting a spin-polarized electron. | 2011-12-29 |
20110316104 | MAGNETO-RESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magnetization is pinned to be substantially anti-parallel to the direction of magnetization of the first magnetization pinned layer, and; a non-magnetic layer. When the second magnetization pinned layer is made of ferromagnetic material including Co, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Rh, Ag, and Au; when the second magnetization pinned layer is made of ferromagnetic material including Fe, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Rh, Pt, Ir, Al, Ag, and Au; and when the second magnetization pinned layer is made of ferromagnetic material including Ni, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Au, and Ag. | 2011-12-29 |
20110316105 | Monolithic Nuclear Event Detector and Method of Manufacture - A PIN diode-based monolithic Nuclear Event Detector and method of manufacturing same for use in detecting a desired level of gamma radiation, in which a PIN diode is integrated with signal processing circuitry, for example CMOS circuitry, in a single thin-film Silicon On Insulator (SOI) chip. The PIN diode is implemented in either a p-, intrinsic, or n-substrate layer. The signal processing circuitry is located in a thin semiconductor layer and is in electrical communication with the PIN diode. The PIN diode may be integrated with the signal processing circuitry onto a single chip, or may be fabricated stand alone using SOI methods according to the method of the invention. | 2011-12-29 |
20110316106 | LIGHT PIPE ETCH CONTROL FOR CMOS FABRICATION - In accordance with at least some embodiments of the present disclosure, a process for fabricating a light pipe (LP) is described. The process may be configured to construct a semiconductor structure having an etch-stop layer above a photodiode region and a first dielectric layer above the etch-stop layer. The process may be configured to etch a LP funnel through the first dielectric layer. And the process may be further configured to stop the etching of the LP funnel upon reaching and removing of the etch-stop layer. | 2011-12-29 |
20110316107 | SOLID-STATE IMAGE SENSOR AND MANUFACTURING METHOD OF THE SENSOR - A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer. | 2011-12-29 |
20110316108 | PHOTOELECTRIC CONVERSION DEVICE, PACKAGE STRUCTURE THEREFOR, AND METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - The present disclosure provides a method of manufacturing a photoelectric conversion device, including, a first step of forming a plurality of photoelectric conversion regions on a surface on one side of a semiconductor wafer, a second step of preparing a light-blocking wafer having insertion openings, a third step of bonding the one-side surface of the semiconductor wafer and a surface on the opposite side to a surface on the one side of the light-blocking wafer to each other to form a bonded wafer body, and a fourth step of dividing the bonded wafer body in peripheries of the photoelectric conversion regions, to obtain bonded-body chips each having the photoelectric conversion region. | 2011-12-29 |
20110316109 | SOLID STATE IMAGING DEVICE - A solid-state imaging device includes photoelectric conversion units, vertical transfer units including vertical transfer electrodes, a horizontal transfer unit, a distribution transfer unit including distribution transfer electrodes, and first light-shield layers and second light-shield layers provided on the vertical transfer units and the distribution transfer unit. The first light-shield layers and the second light-shield layers are conductive. The first light-shield layers are provided in a layer different from a layer in which the second light-shield layers are provided. At least one of the first light-shield layers serves as an interconnect electrically connected to the vertical transfer electrodes included in the same row, and at least one of the first light-shield layers on the distribution transfer unit serves as an interconnect electrically connected the distribution transfer electrodes. The first light-shield layers are disposed so as not to overlap with the horizontal transfer unit. | 2011-12-29 |
20110316110 | ATOMIC LAYER DEPOSITION OF CHEMICAL PASSIVATION LAYERS AND HIGH PERFORMANCE ANTI-REFLECTION COATINGS ON BACK-ILLUMINATED DETECTORS - A back-illuminated silicon photodetector has a layer of Al | 2011-12-29 |
20110316111 | PYROELECTRIC DETECTOR, PYROELECTRIC DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A pyroelectric detector includes a pyroelectric detection element mounted on a first side of a support member with a second side facing a cavity. The pyroelectric detection element has a capacitor including a first electrode, a pyroelectric body and a second electrode, and an interlayer insulation layer forming first and second contact holes passing respectively through to the first and second electrodes. First and second plugs are respectively embedded in the first and second contact holes, with first and second electrode wiring layers are respectively connected to the first and second plugs. A thermal conductivity of material of the second electrode wiring layer is lower than a thermal conductivity of material of a portion of the second electrode connected to the second plug. | 2011-12-29 |
20110316112 | PYROELECTRIC DETECTOR, PYROELECTRIC DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A pyroelectric detector includes a pyroelectric detection element, a support member and a support part. The pyroelectric detection element has a capacitor including a first electrode, a second electrode, and a pyroelectric body. The support member includes first and second sides with the pyroelectric detection element being mounted on the first side and the second side facing a cavity. The support part, the support member, and the pyroelectric detection element are laminated in this order in a first direction with the cavity being formed between the support part and the support member. The support member has at least a first insulation layer on the first side contacting the first electrode, with the first insulation layer having a hydrogen content rate smaller than a hydrogen content rate of a second insulation layer positioned further in a second direction than the first insulation layer, the second direction being opposite the first direction. | 2011-12-29 |
20110316113 | PYROELECTRIC DETECTOR, PYROELECTRIC DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A pyroelectric detector includes a pyroelectric detection element, a support member, and a support part. The pyroelectric detection element has a capacitor including a first electrode, a second electrode, and a pyroelectric body disposed between the first and second electrodes, and a first reducing gas barrier layer that protects the capacitor from reducing gas. The support member includes first and second sides with the pyroelectric detection element being mounted on the first side and the second side facing a cavity. The support member has a mounting member on which the capacitor is mounted and an arm member linked to the mounting member. The support part supports a portion of the support member. An outer peripheral edge of the first reducing gas barrier layer is disposed between and spaced apart from an outer peripheral edge of the mounting member and an outer peripheral edge of the capacitor in plan view. | 2011-12-29 |
20110316114 | SIMPLIFIED PITCH DOUBLING PROCESS FLOW - A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material. | 2011-12-29 |
20110316115 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type cathode region on a surface of the P-type semiconductor substrate, a P-type anode region in the N-type cathode region, a P-type contact region and an N-type contact region in the P-type anode region, a cathode electrode connected to the N-type cathode region, and an anode electrode connected to the P-type contact region and the N-type contact region. | 2011-12-29 |
20110316116 | PHOTOSENSITIVE RESIN COMPOSITION, ADHESIVE FILM AND LIGHT-RECEIVING DEVICE - An object of the present invention is to provide a photosensitive resin composition which leaves a small amount of resin residues after patterning by light-exposure and development and can reduce condensation between the semiconductor wafer and the transparent substrate under a high temperature and high humidity environment, an adhesive film made of the photosensitive resin composition and a light-receiving device including the adhesive film. The photosensitive resin composition of the present invention contains an alkali soluble resin (A), a photopolymerization initiator (B) and a compound (C) having a phenolic hydroxyl group and a carboxyl group. | 2011-12-29 |
20110316117 | DIE PACKAGE AND A METHOD FOR MANUFACTURING THE DIE PACKAGE - A die package and a method for manufacturing the die package are provided. The die package includes a second die arranged above a first die, the first die comprising an interconnect region on a surface facing the second die, wherein the second die is arranged laterally next to the interconnect region of the first die; a first package-internal free-standing interconnect structure disposed above the interconnect region of the first die; a second package-internal free-standing interconnect structure disposed above an interconnect region of the second die, the interconnect region of the second die being on a surface of the second die facing away from the first die; and package material formed partially around the first package-internal free-standing interconnect structure and the second package-internal free-standing interconnect structure such that a connecting portion of the first package-internal free-standing interconnect structure and a connecting portion of the second package-internal free-standing interconnect structure remains uncovered to be electrically connected to a package-external interconnect structure. | 2011-12-29 |
20110316118 | Semiconductor device - A semiconductor device includes a substrate including a diffusion region, a device isolation region, an inductor region, and a guard ring region, a guard ring formed on the substrate to be connected to the diffusion region in the guard ring region, an insulating film formed on the substrate, in which the insulating film includes an interconnect, and an inductor formed in the inductor region, in which the guard ring region surrounds the inductor region and the device isolation region. | 2011-12-29 |
20110316119 | SEMICONDUCTOR PACKAGE HAVING DE-COUPLING CAPACITOR - Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device. | 2011-12-29 |
20110316120 | Release Strategies for Making Transferable Semiconductor Structures, Devices and Device Components - Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components. | 2011-12-29 |
20110316121 | METHOD FOR MANUFACTURING TRENCH TYPE SUPERJUNCTION DEVICE AND TRENCH TYPE SUPERJUNCTION DEVICE - A method for manufacturing trench type super junction device is disclosed. The method includes the step of forming one or more P type implantation regions in the N type epitaxial layer below the bottom of each trench. By using this method, a super junction device having alternating P type and N type regions is produced, wherein the P type region is formed by P type silicon filled in the trench and P type implantation regions below the trench. The present invention can greatly improve the breakdown voltage of a super junction MOSFET. | 2011-12-29 |
20110316122 | WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME - A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon. | 2011-12-29 |
20110316123 | Laminated semiconductor substrate, laminated chip package and method of manufacturing the same - In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions. | 2011-12-29 |
20110316124 | SEMICONDUCTOR DEVICE - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 2011-12-29 |
20110316125 | INTERMEDIATE STRUCTURES FOR FORMING CIRCUITS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon. | 2011-12-29 |
20110316126 | Semiconductor element and method of manufacturing the semiconductor element - A semiconductor element includes a semiconductor layer, an electrode, an adhesion layer, and an insulating layer. The electrode is disposed over the semiconductor layer and has a first upper surface and a second upper surface disposed further away from the semiconductor layer than the first upper surface. The adhesion layer is disposed on the first upper surface of the electrode so that the second upper surface of the electrode is disposed further away from the semiconductor layer than an upper surface of the adhesion layer. The insulating layer covers from the upper surface of the adhesion layer to the semiconductor layer. | 2011-12-29 |
20110316127 | SPACER FORMATION FILM, SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE - A spacer formation film is adapted to be used for forming a spacer defining air-gap portions on a side of one surface of a semiconductor wafer and by being cut into a desired shape, the spacer formation film includes: a support base having a sheet-like shape; a spacer formation layer provided on the support base and having a bonding property, the spacer formation layer formed of a material containing an alkali soluble resin, a thermosetting resin and a photo polymerization initiator; and a cutting line along which the spacer formation film is to be cut, wherein the spacer formation layer is provided inside the cutting line so that a peripheral edge thereof is not overlapped to the cutting line. | 2011-12-29 |
20110316128 | Semiconductor Wafers Of Silicon and Method For Their Production - Semiconductor wafers of silicon are produced by pulling a single crystal growing on a phase boundary from a melt contained in a crucible and cutting of semiconductor wafers therefrom, wherein during pulling of the single crystal, heat is delivered to a center of the phase boundary and a radial profile of a ratio V/G from the center to an edge of the phase boundary is controlled, G being the temperature gradient perpendicular to the phase boundary and V being the pull rate. The radial profile of the ratio V/G is controlled so that the effect of thermomechanical stress in the single crystal adjoining the phase boundary, is compensated with respect to creation of intrinsic point defects. The invention also relates to defect-free semiconductor wafers of silicon, which can be produced economically by this method. | 2011-12-29 |
20110316129 | MULTILAYER STRUCTURES FOR MAGNETIC SHIELDING - A magnetic shield is presented. The shield may be used to protect a microelectronic device from stray magnetic fields. The shield includes at least two layers. A first layer includes a magnetic material that may be used to block DC magnetic fields. A second layer includes a conductive material that may be used to block AC magnetic fields. Depending on the type of material that the first and second layers include, a third layer may be inserted in between the first and second layers. The third layer may include a non-conductive material that may be used to ensure that separate eddy current regions form in the first and second layers. | 2011-12-29 |
20110316130 | THIN SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a thin semiconductor package includes providing a lead frame with a removable substrate that has an attaching surface attached to a first surface of the lead frame. The lead frame is formed from an electrically conductive sheet and has leads that extend inwardly from a lead frame boundary towards a central region of the lead frame. A semiconductor die is mounted on the removable substrate at the central region. The semiconductor die has a connection pad surface with die pads on it, and the connection pad surface is attached to the attaching surface of the removable substrate. The lead frame and die are encapsulated with a first encapsulant so that the lead frame is sandwiched between the first encapsulant and the removable substrate. The removable substrate is removed from the lead frame to expose the first surface of the lead frame and then the die pads are electrically connected to respective ones of the leads. The die and lead frame then are encapsulated with a second encapsulant so that the lead frame and die are sandwiched between the first and second encapsulants. Part of the first encapsulant is then removed to reduce the thickness of the package and expose the leads. | 2011-12-29 |
20110316131 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 2011-12-29 |
20110316132 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure. | 2011-12-29 |
20110316133 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a penetrable layer; partially immersing leads in the penetrable layer; coupling an integrated circuit die to the leads; molding a package body on the integrated circuit die, the leads, and the penetrable layer; and exposing stand-off leads from the leads by removing the penetrable layer including establishing a stand-off height between a bottom of the package body and the bottom of the stand-off leads. | 2011-12-29 |
20110316134 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction. | 2011-12-29 |
20110316135 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided. | 2011-12-29 |
20110316136 | SEMICONDUCTOR DEVICE WITH LEAD TERMINALS HAVING PORTIONS THEREOF EXTENDING OBLIQUELY - A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion. | 2011-12-29 |
20110316137 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view. | 2011-12-29 |
20110316138 | HIGH FREQUENCY FAST RECOVERY DIODE - A high-frequency fast recovery diode that includes a diode chip set, solder lugs, lead wires, lead terminals, a silicone coating layer and a plastic package body. The diode chip set includes n-diode chips arranged in the same polarity order sequentially, a part of the n-diode chips can be fast recovery diode chips and others can be conventional. Solder lugs are placed on both sides of, and connected with, each diode chip. Lead wires are connected with the solder lugs on the ends of the diode chip set, respectively. The silicone coating layer is provided around the diode chip set and the lugs. The plastic package body is provided around the lead terminals and the silicone coating layer. The shape of the plastic package body can be a cylindrical or square column. The reverse recovery time of the high-frequency fast recovery diode can be shortened, and the voltage resistance performance improved. | 2011-12-29 |
20110316139 | PACKAGE FOR A WIRELESS ENABLED INTEGRATED CIRCUIT - An integrated circuit (IC) device is provided. The IC device includes a substrate, an IC die coupled to the substrate, and a first wirelessly enabled functional block formed on the IC die. The first wirelessly enabled functional block is configured to wirelessly communicate with a second wirelessly enabled functional block formed on the substrate. | 2011-12-29 |
20110316140 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a substrate ( | 2011-12-29 |
20110316141 | LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING SAME - A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip. | 2011-12-29 |
20110316142 | SEMICONDUCTOR MODULE WITH RESIN-MOLDED PACKAGE OF HEAT SPREADER AND POWER SEMICONDUCTOR CHIP - A semiconductor module is provided which includes a resin molded package which is made by a resinous mold assembly. The resin molded package is clamped by covers through a fastener to make the semiconductor module. The resinous mold assembly has formed therein a coolant path that is a portion of a coolant passage through which a coolant flows to coal a semiconductor chip embedded in the resin molded package. The resinous mold assembly is made up of a first mold and a second mold. The first mold has the semiconductor chip, heat spreaders, and electric terminals embedded therein. The second mold is wrapped around an outer periphery of the first mold. The second mold is made of resin which is lower in softening temperature than that of the first mold, thereby facilitating ease of removing the first mold from the resin molded package for reusing the resin molded package. | 2011-12-29 |
20110316143 | SEMICONDUCTOR MODULE WITH COOLING MECHANISM AND PRODUCTION METHOD THEREOF - A semiconductor module is provided which includes a semiconductor unit which is made by a resin mold. The resin mold has formed therein a coolant path through which a coolant flows to cool a semiconductor chip embedded in the resin mold. The resin mold also includes heat spreaders, and electric terminals embedded therein. Each of the heat spreaders has a fin heat sink exposed to the flow of the coolant. The fin heat sink is welded to a surface of each of the heat spreaders through an insulator, thus minimizing an electrical leakage from the heat spreader to the coolant. | 2011-12-29 |
20110316144 | FLEXIBLE HEAT SINK HAVING VENTILATION PORTS AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A heat sink includes a first adhesive layer, and a heat dissipation layer disposed on the first adhesive layer, and has ventilation ports that extend therethrough including through the first adhesive layer and the heat dissipation layer. The heat sink forms an outermost part of a semiconductor package. Thus, when the heat sink is bonded via its adhesive layer to underlying structure during a manufacturing process, the ventilation ports allow air to pass therethrough. As a result, air is not trapped in the form of bubbles between the heat sink and the underlying structure. | 2011-12-29 |
20110316145 | NANO/MICRO-STRUCTURE AND FABRICATION METHOD THEREOF - A nano/micro-structure and a fabrication method thereof are provided. The method combines electroless plating and metal-assist etching to fabricate nano/micro-structure on a silicon substrate. | 2011-12-29 |
20110316146 | Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure - A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation. | 2011-12-29 |
20110316147 | Embedded 3D Interposer Structure - A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump. | 2011-12-29 |
20110316148 | WIRING SUBSTRATE - A wiring substrate includes plural wiring layers and plural insulation layers being alternately stacked one on top of the other. The plural insulation layers are formed with insulation resin having the same composition. The plural insulation layers are formed with a filler having the same composition. The filler content of each of the plural insulation layers ranges from 30 vol % or more to 65 vol % or less. The thermal expansion coefficient of each of the plural insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less. | 2011-12-29 |
20110316149 | METHOD OF MOUNTING ELECTRONIC COMPONENT AND MOUNTING SUBSTRATE - In flip chip attach of electronic components, underfill is filled between the component and the substrate to alleviate, for example, thermal stress. In electronic component mounting using copper pillars conducted so far, filler contained in the underfill may cause separation in the process of heating and curing the resin. Disclosed is plating the surfaces of the copper pillars with solder. Mobilization of the filler charged in the underfill due to electric fields produced by local cells that are developed upon contact between dissimilar metals, is suppressed, and occurrence of crack at connection portions is obviated. Thus, connection reliability is increased. | 2011-12-29 |
20110316150 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a first board, a semiconductor chip having a first face and a second face at an opposite side to the first face, the semiconductor chip being mounted on the first board with the first face facing the first board, an insulating film provided on the second face of the semiconductor chip, and a second board stacked on the first board. A bump provided on a face of the second board facing the first board is connected to a pad provided on a face of the first board facing the second board and a gap is formed between the first board and the second board. The semiconductor chip and the insulating film are provided in the gap. | 2011-12-29 |
20110316151 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a board, an under fill resin layer provided on the board, and a semiconductor chip having a first face and a second face at an opposite side to the first face, the semiconductor chip being flip-chip mounted on the board via the under fill resin layer with the first face facing the board. The semiconductor chip is covered with the under fill resin layer over the first face and from the first face to an edge part of the second face. | 2011-12-29 |
20110316152 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGES AND A SEMICONDUCTOR PACKAGE - Semiconductor chips are placed in recesses of a support carrier with electrode surfaces facing upward in a state where the semiconductor chips are arranged separately from each other. A seal resin part is formed by encapsulating the semiconductor chips by an insulating resin on said support carrier. Rewiring patterns are formed on a top surface of the seal resin part. External connection terminals are formed on the rewiring patterns. Bottom parts of the recesses of the support carrier are removed from the seal resin part while maintaining reinforcing members of the support carrier to be remained. The semiconductor packages are individualized by cutting the seal resin part along an outside of each reinforcing member. | 2011-12-29 |
20110316153 | SEMICONDUCTOR DEVICE AND PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate | 2011-12-29 |
20110316154 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof. | 2011-12-29 |
20110316155 | SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a semiconductor packaging system includes: providing a substrate; mounting a semiconductor chip to the substrate; mounting a pillar ball having a ball height electrically connected to the substrate; mounting an interposer above the semiconductor chip and electrically connected to the pillar ball; and wherein: mounting the interposer or mounting the substrate includes connecting the pillar ball to a pillar base having a base height substantially less than the ball height of the pillar ball and the pillar base having vertical sides not covered by the pillar ball. | 2011-12-29 |
20110316156 | Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect - A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL. | 2011-12-29 |
20110316157 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface. | 2011-12-29 |
20110316158 | METHOD AND SYSTEM FOR THIN MULTI CHIP STACK PACKAGE WITH FILM ON WIRE AND COPPER WIRE - A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die. | 2011-12-29 |
20110316159 | CHIP STACK PACKAGE - A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities. | 2011-12-29 |
20110316160 | Semiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate - A semiconductor arrangement includes a silicon body having a top surface and a bottom surface, and a thick metal layer arranged on the top surface of the silicon body. The thick metal layer has a bonding surface facing away from the top surface of the silicon body. A bonding wire or a ribbon is bonded to the thick metal layer at the bonding surface of the thick metal layer. The thickness of the thick metal layer is at least | 2011-12-29 |
20110316161 | METHOD OF PRODUCING A DUAL DAMASCENE MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE - In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed in the hard mask film, and a grove is formed in the insulating film structure using this as a mask. According to the prior art, the via side wall is oxidized equally severely in the both processes. The trench side wall is oxidized severely in the via first process according to the prior art, whereas, according to the present invention, the oxidation thereof is suppressed to such an extent that an almost non-oxidized state can be created. | 2011-12-29 |
20110316162 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a material layer including grooves in a fillet region that are substantially parallel and adjacent an integrated circuit; and forming a resin between the substrate and the integrated circuit that contacts a trench trace exposed by the grooves. | 2011-12-29 |
20110316163 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device; forming package interconnects adjacent the integrated circuit device, the package interconnects having an internal interconnect side with a lock structure; applying an encapsulation over the integrated circuit device and the package interconnects, the lock structure conformally filled with the encapsulation; and forming a base cavity with sides formed by the encapsulation and an external interconnect side of each of an adjacent pair of package interconnects facing one another, the base cavity having a cross-sectional length at least two times a cross-sectional width. | 2011-12-29 |
20110316164 | CORRUGATED DIE EDGE FOR STACKED DIE SEMICONDUCTOR PACKAGE - A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die. | 2011-12-29 |
20110316165 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines. | 2011-12-29 |
20110316166 | INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer. | 2011-12-29 |
20110316167 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 2011-12-29 |
20110316168 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure. | 2011-12-29 |
20110316169 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING THE WIRING SUBSTRATE - A wiring substrate includes a substrate body including a first substrate surface and a second substrate surface, a trench being open toward the first substrate surface, the trench having an inner bottom surface and an inner side surface, a through-hole having a first end communicating with the inner bottom surface of the trench and a second end being open toward the second substrate surface, a first conductive layer having a first surface toward the trench and being filled inside at least a portion of the through-hole from the second end, a second conductive layer covering the first surface and at least a part of the inner bottom surface of the trench, and a third conductive layer covering the second conductive layer and being filled inside the trench. | 2011-12-29 |
20110316170 | Wiring Substrate, Semiconductor Device, and Method for Manufacturing Wiring Substrate - A wiring substrate includes a wiring pattern in an uppermost layer that includes pads. A solder resist layer covers the wiring pattern. A recess exposes part of the wiring pattern from the solder resist layer to form pads. The solder resist layer includes a portion formed in a region corresponding to the recess, a portion formed outward from the recess, and a portion formed inward from the recess. The upper surface of the solder resist layer at the portion corresponding to the recess is higher than the upper surface of the pads but lower than the upper surfaces of the other portions of the solder resist layer. | 2011-12-29 |
20110316171 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 2011-12-29 |
20110316172 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor package that includes: a wiring board; a first semiconductor chip mounted on the wiring board; a second semiconductor chip mounted on the first semiconductor chip, wherein a size of second semiconductor chip is larger than that of the first semiconductor chip when viewed from a thickness direction of the semiconductor package; an insulating resin provided between the wiring board and the second semiconductor chip and between the wiring board and the first semiconductor chip so as to cover the first semiconductor chip; a base disposed on the wiring board to face a surface of the second semiconductor chip, wherein the insulating resin is provided between the base and the second semiconductor chip so as to cover the base. | 2011-12-29 |
20110316173 | ELECTRONIC DEVICE COMPRISING A NANOTUBE-BASED INTERFACE CONNECTION LAYER, AND MANUFACTURING METHOD THEREOF - An electronic device including a first region belonging to a semiconductor device having a first surface; a second region having a second surface; and an adhesion layer, set between the first and second regions, including first fibrils each having respective first and second ends. The first fibrils extend between the first and second surfaces and are fixed in a chemico-physical way to the first and second surfaces at the respective first and second ends. | 2011-12-29 |
20110316174 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction. | 2011-12-29 |
20110316175 | CARBONATION APPARATUS AND METHOD FOR FORMING A CARBONATED BEVERAGE - An inline carbonation apparatus that includes a fluid tube having an inner diameter. At least one water orifice is linked to a water source and is attached to one end of the fluid tube. The water orifice includes a plurality of holes atomizing water that passes therethrough. A carbon dioxide orifice is linked to a carbon dioxide source and is attached to the fluid tube in a spaced relationship from the water orifice. The atomized water has a pressure less than the carbon dioxide such that carbon dioxide is absorbed into the water forming carbonated water having a specified volume of carbonation. | 2011-12-29 |
20110316176 | SIMPLE START DIAPHRAGM TYPE CARBURETOR - A simple start diaphragm type carburetor includes a carburetor body, a main adjutage, a throttle subassembly, a choke spindle, a linkage subassembly and a start fuel passage. The carburetor body is formed to be a main fuel supply channel which includes g a gasinlet cavity, a venturi and a mixing cavity. The main adjutage is mounted on the venturi. The throttle subassembly is mounted on the carburetor body for controlling the fuel to enter the mixing cavity and the throttle spindle is pivoted to the carburetor body. The start fuel passage disposed in the carburetor body has a fuel inlet connecting with a measuring room provided in the carburetor body and a fuel outlet connecting with the mixing cavity. The linkage subassembly includes a first linkage subassembly, a reset element and a second linkage subassembly which cooperates with the first eccentric element to form a linkage. When the first linkage subassembly opens the start fuel passage, the second linkage subassembly drives the main fuel supply channel to be open partially. Rotate the throttle subassembly and the choke spindle is reset by the reset element, thereby closing the start fuel passage. The present invention can increases the probability of the successful start of an engine and keep the engine be warm-up for a long time, furthermore, it can reduce the burden of the user. | 2011-12-29 |
20110316177 | POLYIMIDE PARTICLES DERIVED FROM SCRAP POLYIMIDE FILM AND METHODS RELATING THERETO - A method is disclosed for making polyimide powder. The method includes feeding polyimide film material into an extruder, where the extruder has at least one heating zone. The feed rate into the extruder is less than the maximum feed rate of the extruder. The material is then extruded for at least 0.5 seconds at a temperature greater than 300° C. to provide a powdered extrudate. | 2011-12-29 |
20110316178 | Method And Apparatus For Making Products By Sintering And/Or Melting - The invention relates to a method for making metallic and/or non-metallic products | 2011-12-29 |
20110316179 | PROCESSES FOR PRODUCING A POLYMER-BONDED FIBER AGGLOMERATE AND A FIBER-REINFORCED COMPOSITE MATERIAL - A polymer-bonded fiber agglomerate includes short fibers selected from carbon, ceramic materials, glasses, metals and organic polymers, and a polymeric bonding resin selected from synthetic resins and thermoplastics. The fiber agglomerates have an average length, measured in the fiber direction, of from 3 mm to 50 mm and an average thickness, measured perpendicularly to the fiber direction, of from 0.1 mm to 10 mm. At least 75% of all of the contained fibers have a length which is at least 90% and not more than 110% of the fiber agglomerate average length. A fiber-reinforced composite material having the fiber agglomerate and processes for the production thereof are also provided. | 2011-12-29 |
20110316180 | MOLD MONITORING - A monitor for maintaining a mold cycle count and other mold operation data and a corresponding system that generates a first remote record of the mold cycle data and a second remote record of the mold cycle data, the second remote record comprising a lesser, different and/or non-confidential version of the first remote record. The first remote record and the second remote record may then be coordinated among an OEM manufacturer, a moldmaker and a molder. | 2011-12-29 |