52nd week of 2008 patent applcation highlights part 31 |
Patent application number | Title | Published |
20080316788 | Semiconductor memory device and method for operating semiconductor memory device - A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section. The memory array section and the interface section are sealed in a package. The interface section has a plurality of interface modules corresponding to a plurality of memory types on a one-to-one basis. The method includes the steps of: selecting one of the plurality of interface modules in accordance with the memory type complying with specifications of the external memory controller being connected; and causing the selected interface module to access the memory array section for either a write or a read operation in response to either a write or a read request issued by the external memory controller. | 2008-12-25 |
20080316789 | Random Access Electrically Programmable E-Fuse Rom - A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at V | 2008-12-25 |
20080316790 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR MANUFACTURING DEVICE - The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head | 2008-12-25 |
20080316791 | OPERATING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY - The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory. | 2008-12-25 |
20080316792 | CIRCUIT FOR PROGRAMMING A MEMORY ELEMENT - An integrated circuit includes a memory element and a circuit. The circuit is configured to program the memory element by applying one or more pulses to the memory element until a sensed resistance of the memory element is within a range of a desired resistance. The one or more pulses have a parameter value that is modified for each subsequent pulse based on the parameter value for an immediately preceding pulse and on a difference between the sensed resistance of the memory element and the desired resistance. | 2008-12-25 |
20080316793 | INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE - An integrated circuit includes a first electrode, a second electrode, and resistivity changing material between the first electrode and the second electrode. The integrated circuit includes a contact contacting a bottom and a first sidewall portion of the first electrode. | 2008-12-25 |
20080316794 | INTEGRATED CIRCUIT HAVING MULTILAYER ELECTRODE - An integrated circuit includes a first electrode including at least two electrode material layers and a resistivity changing material including a first portion and a second portion. The first portion contacts the first electrode and has a same cross-sectional width as the first electrode. The second portion has a greater cross-sectional width than the first portion. The integrated circuit includes a second electrode coupled to the resistivity changing material. | 2008-12-25 |
20080316795 | Method of making nonvolatile memory device containing carbon or nitrogen doped diode - A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping the diode with at least one of nitrogen or carbon, and forming a second electrode over the at least one nonvolatile memory cell. | 2008-12-25 |
20080316796 | Method of making high forward current diodes for reverse write 3D cell - A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell including a diode and a metal oxide antifuse dielectric layer over the first electrode, and forming a second electrode over the at least one nonvolatile memory cell. In use, the diode acts as a read/write element of the nonvolatile memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias. | 2008-12-25 |
20080316797 | Memory Element Array - Disclosed is a memory element array comprising a plurality of memory elements arranged in an array, wherein the memory elements are switching elements each including a gap of nanometer order in which a switching phenomenon of resistance is caused by applying a predetermined voltage between electrodes, and the memory element array is provided with tunnel elements respectively connected to the switching elements in series, each of the tunnel elements preventing generation of a sneak path current flowing to another switching element at a time of applying the predetermined voltage. | 2008-12-25 |
20080316798 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array, and each of the resistance value of the current path between the memory cell and the write current source and the resistance value of the current path between the selected memory cell and the reference potential node is set to 500Ω or lower. A nonvolatile semiconductor memory device having improved reliability of data read/write is achieved. | 2008-12-25 |
20080316799 | Read-Preferred SRAM Cell Design - A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell. | 2008-12-25 |
20080316800 | Semiconductor memory device - When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells. | 2008-12-25 |
20080316801 | Magnetic Memory System Using Mram-Sensor - The invention relates to a Magnetic memory system ( | 2008-12-25 |
20080316802 | MEMORY DEVICE HAVING DRIFT COMPENSATED READ OPERATION AND ASSOCIATED METHOD - A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels. | 2008-12-25 |
20080316803 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device. | 2008-12-25 |
20080316804 | Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices - In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: | 2008-12-25 |
20080316805 | Electronic Circuit With a Memory Matrix - An electronic circuit comprises a memory matrix ( | 2008-12-25 |
20080316806 | Phase change memory device - A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage. | 2008-12-25 |
20080316807 | Semiconductor memory device having metal-insulator transition film resistor - A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof. | 2008-12-25 |
20080316808 | Nonvolatile memory device containing carbon or nitrogen doped diode - A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration. | 2008-12-25 |
20080316809 | High forward current diodes for reverse write 3D cell - A nonvolatile memory device includes at least one memory cell which comprises a diode and a metal oxide antifuse dielectric layer, and a first electrode and a second electrode electrically contacting the at least one memory cell. In use, the diode acts as a read/write element of the memory cell by switching from a first resistivity state to a second resistivity state different from the first resistivity state in response to an applied bias. | 2008-12-25 |
20080316810 | MEMORY UNIT - A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory. | 2008-12-25 |
20080316811 | METHOD FOR OPERATING NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A method for controlling non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 2008-12-25 |
20080316812 | PROGRAMMING A MEMORY WITH VARYING BITS PER CELL - Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability. | 2008-12-25 |
20080316813 | MULTI-LEVEL CELL SERIAL-PARALLEL SENSE SCHEME FOR NON-VOLATILE FLASH MEMORY - A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme. | 2008-12-25 |
20080316814 | PROGRAM-VERIFY SENSING FOR A MULTI-LEVEL CELL (MLC) FLASH MEMORY DEVICE - According to some embodiments, a method and apparatus for program verify sensing disclosed. During a program verify sensing operation, a tracking signal may be generated to match a sense amplifier signal. A data stream from a sequence generator may be held at a pass/hold logic until the tracking signal reaches a trip point. The data stream may be subsequently latched at a main latch with the sense amplifier signal. | 2008-12-25 |
20080316815 | METHODS OF PROGRAMMING MULTILEVEL CELL NONVOLATILE MEMORY - A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block. | 2008-12-25 |
20080316816 | SYSTEMS FOR PROGRAMMING MULTILEVEL CELL NONVOLATILE MEMORY - A memory system includes a first block in which data is stored with a low density and a second block in which data is stored with a high density. When data is received it is written to the first block, and in parallel some of the data is written to the second block, so that the second block is partially programmed. The second block is later fully programmed by copying additional data from the first block. | 2008-12-25 |
20080316817 | Method and system for programming non-volatile memory cells based on programming of proximate memory cells - A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are proximate the row to be programmed. In one example of the invention, after the row has been programmed, the proximate cells are verified by read, comparison, and, if necessary, reprogramming operations to compensate for charge added to proximate memory cells resulting from programming the row. In another example of the invention, a row of memory cells is programmed with charge levels that take into account the charge that will be added to the memory cells when proximate memory cells are subsequently programmed. | 2008-12-25 |
20080316818 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING - A non volatile memory device and method of operating including providing a verification voltage to a gate of a selected memory cell within multiple memory cells and providing a first pass voltage to a gate of a non-selected memory cell within the memory cells during a program verification operation; and providing a read voltage to the gate of the selected memory cell and providing a second pass voltage to the gate of the non-selected memory cell during a read operation. The second pass voltage is greater than the first pass voltage. | 2008-12-25 |
20080316819 | FLASH MEMORY DEVICE CAPABLE OF STORING MULTI-BIT DATA AND SINGLE-BIT DATA - There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included. | 2008-12-25 |
20080316820 | Method of programming memory device - Provided is a method of programming a memory device. The method includes performing a program voltage applying operation; and performing a verifying operation, wherein a plurality of verifying operations are consecutively performed after a program voltage applying operation. | 2008-12-25 |
20080316821 | NONVOLATILE STORAGE DEVICE AND BIAS CONTROL METHOD THEREOF - A nonvolatile storage device having a memory cell array composed of a plurality of memory cells. The plurality of memory cells include a bit line to which the drain terminals of the plurality of memory cells that have noncovalent connected gate terminals are commonly connected and a source line to which the source terminals of the plurality of memory cells that have commonly connected gate terminals are commonly connected and which extend perpendicularly to the bit line. The memory cell also includes a first source selector switch for connecting the source line to a source bias line. | 2008-12-25 |
20080316822 | MEMORY SYSTEM THAT DETECTS BIT ERRORS DUE TO READ DISTURBANCE AND METHODS THEREOF - Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory. | 2008-12-25 |
20080316823 | STORAGE DEVICE AND CIRCUIT ELEMENT SWITCHING METHOD THEREOF - The present invention discloses a storage device and a circuit element switching method thereof. The storage device includes: a plurality of memory modules, wherein each of the plurality of memory modules includes a plurality of chip enable terminals; a memory control unit that includes a plurality of bank selection terminals; and a switch module that is coupled between the plurality of memory modules and the memory control unit, and utilized for dispersedly coupling the plurality of bank selection terminals to the plurality of chip enable terminals of each of the plurality of memory modules. The circuit element switching method applied to the storage device includes: providing a memory control unit including a plurality of bank selection terminals; and dispersedly coupling the plurality of bank selection terminals to a plurality of chip enable terminals of each of the plurality of memory modules. | 2008-12-25 |
20080316824 | Non-volatile memory device and method of operating the same - Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell. | 2008-12-25 |
20080316825 | SEMICONDUCTOR MEMORY DEVICE - An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal. | 2008-12-25 |
20080316826 | Semiconductor device having transistor and capacitor of SOI structure and storing data in nonvolatile manner - In a semiconductor device, a first transistor of an SOI structure has a source region, a drain region, a body region positioned between the source region and the drain region, and a gate electrode positioned above the body region. A first capacitor of the SOI structure has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal. The semiconductor device stores data in a nonvolatile manner in accordance with carriers accumulated in a first node electrically connecting the gate electrode of the first transistor and the first terminal of the first capacitor. | 2008-12-25 |
20080316827 | NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 2008-12-25 |
20080316828 | Memory in logic cell - Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type. | 2008-12-25 |
20080316829 | SYSTEM FOR VERIFYING NON-VOLATILE STORAGE USING DIFFERENT VOLTAGES - When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage. | 2008-12-25 |
20080316830 | COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES - Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell. For example, a compensated operation voltage can be provided that is higher near the center of the memory array and lower near an edge of the memory array, thereby lessening the effect of distributed substrate resistance and providing increased operation speed uniformity throughout the memory array. | 2008-12-25 |
20080316831 | Nonvolatile semiconductor device, system including the same, and associated methods - A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the memory cell units includes a tunnel insulation layer on the semiconductor substrate. A first memory gate and a second memory gate are disposed on the tunnel insulation layer. An isolation gate is disposed between the first and second memory gates. A word line covers the first memory gate, the second memory gate and the isolation gate. A method of forming the nonvolatile memory device is also provided. | 2008-12-25 |
20080316832 | NON-VOLATILE STORAGE SYSTEM WITH INTELLIGENT CONTROL OF PROGRAM PULSE DURATION - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations. | 2008-12-25 |
20080316833 | INTELLIGENT CONTROL OF PROGRAM PULSE DURATION - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations. | 2008-12-25 |
20080316834 | BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE - A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit. | 2008-12-25 |
20080316835 | Concurrent Multiple-Dimension Word-Addressable Memory Architecture - An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines. | 2008-12-25 |
20080316836 | Ground biased bitline register file - In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry is used to bias a read bitline when the memory cell is not performing a read operation. | 2008-12-25 |
20080316837 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING POTENTIAL LEVEL OF POWER SUPPLY LINE AND/OR GROUND LINE - Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced. | 2008-12-25 |
20080316838 | Redundancy memory cell access circuit and semiconductor memory device including the same - A redundancy memory cell access circuit includes a first control unit, a second control unit, and an accessing unit. The first control unit compares an unprogrammed fuse signal with an address signal to generate a first redundancy enable signal from the comparison. The accessing unit allows access to a redundancy memory cell corresponding to the unprogrammed signal when the first redundancy enable signal from the first control unit or a second redundancy enable signal from the second control unit is activated. Thus, the redundancy memory cell access circuit is tested simultaneously with testing of the redundancy memory cell for minimized testing and programming times. | 2008-12-25 |
20080316839 | MEMORY CELL ARRAY AND METHOD OF CONTROLLING THE SAME - To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage. | 2008-12-25 |
20080316840 | Input/output line sense amplifier and semiconductor memory device using the same - An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit. | 2008-12-25 |
20080316841 | MEMORY DEVICE HAVING DATA PATHS WITH MULTIPLE SPEEDS - A memory device has multiple bi-directional data paths. One of the multiple bidirectional data paths is configured to transfer data at one speed. Another one of the multiple bidirectional data paths is configured to transfer data at another speed. | 2008-12-25 |
20080316842 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR BROADCASTING WRITE OPERATIONS - A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this end, the write operations may be broadcasted to a plurality of targets. At least one of the targets includes another one of the apertures that produces at least one additional write operation. | 2008-12-25 |
20080316843 | Semiconductor memory device capable of operating in a plurality of operating modes and method for controlling thereof - A semiconductor memory device capable of operating in a plurality operating modes and a method for controlling the device may be provided. The semiconductor memory device may include a selecting unit and a plurality of control circuits operating in a plurality of operating modes. The selecting unit may transmit a selecting signal to select one of the plurality of operating modes. The plurality of control circuits may control operations of the semiconductor memory device in the plurality of operating modes, and the plurality of control circuits may be either enabled or disabled in response to the selecting signal. The semiconductor memory device and the method of controlling the device may have a capability of providing optimized performance in response to a change of operational conditions by selecting one of a plurality of the operating modes. | 2008-12-25 |
20080316844 | SELECTION METHOD OF BIT LINE REDUNDANCY REPAIR AND APPARATUS PERFORMING THE SAME - A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, and selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code. The apparatus includes a redundancy repair enable circuit for generating a redundancy enable signal based on logical addresses of the memory blocks, a controlling fuse circuit for sending a code matching a defective type of the memory blocks, and a redundancy decoder circuit for receiving the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks. | 2008-12-25 |
20080316845 | MEMORY ROW ARCHITECTURE HAVING MEMORY ROW REDUNDANCY REPAIR FUNCTION - The present invention discloses a memory row architecture having memory row redundancy repair function. The memory row architecture includes a plurality of normal memory sections and a plurality of redundancy memory sections, wherein a number of the plurality of normal memory sections is more than two, a number of the plurality of redundancy memory sections is equal to the number of the plurality of normal memory sections, and a redundancy memory section is implemented in one side of each of the plurality of normal memory sections. In addition, the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an odd serial number make up a first memory row redundancy repair module, and the plurality of normal memory sections and the plurality of redundancy memory sections respectively having an even serial number make up a second memory row redundancy repair module. | 2008-12-25 |
20080316846 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF STORING DATA OF VARIOUS PATTERNS AND METHOD OF ELECTRICALLY TESTING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array. | 2008-12-25 |
20080316847 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device. | 2008-12-25 |
20080316848 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREFOR - This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies and storing therein logic data; bit lines and word lines connected to the memory cells; sense amplifiers connected to the bit lines; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory cells; and a refresh interval timer setting a refresh interval between one refresh operation and a next refresh operation to a first interval in a data read mode or a data write mode, and setting the refresh interval to a second interval longer than the first interval in a data retention mode, the data read mode being a mode in which the data stored in the selected memory cell is read to an outside of the device, the data write mode being a mode in which data from the outside is written to the selected memory cell. | 2008-12-25 |
20080316849 | MEMORY DRIVING METHOD AND SEMICONDUCTOR STORAGE DEVICE - This disclosure concerns a method of driving a memory including memory cells, bit lines, and word lines, each memory cell having a source, a drain, and a floating body, the method comprising performing a refresh operation for recovering deterioration of first logical data of the memory cells and deterioration of second logical data of the memory cells, wherein in the refresh operation, the number of the carriers injected into the floating body is larger than the number of the carriers discharged from the floating body when a potential at the floating body is larger than a critical value, and the number of the carriers injected into the floating body is smaller than the number of the carriers discharged from the floating body when the potential at the floating body is smaller than the critical value. | 2008-12-25 |
20080316850 | System for retaining state data of an integrated circuit - According to one embodiment, a system for retaining M bits of state data of an integrated circuit during power down includes M serially coupled scan flip flops divided into M/N groups, where the M scan flip flops are able to save/restore the M bits of state data. Each group contains a merged scan flip flop coupled to a series of scan flip flops. The merged scan flip flop in each of the groups is coupled to a respective read port of a memory unit, and a final scan flip flop in each of the groups is coupled to a respective write port of the memory unit. The system enables the memory unit to save the M bits of state data in N clock cycles. Each merged scan flip flop has a read select input that enables restoring of the state data into the M scan flip flops in N clock cycles. | 2008-12-25 |
20080316851 | Semiconductor memory device - Disclosed is a semiconductor memory device including a plurality of memory cells, each of which is connected to word lines of first and second ports and to bit lines of the first and second ports, and first and second inter-port switches for electrically connecting first bit lines of the first port and second bit lines of the second port when row addresses of the first and second ports match each other. | 2008-12-25 |
20080316852 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the semiconductor substrate, a first electrode provided on the first conduction layer to be given a first voltage, a second conduction layer provided on the semiconductor substrate with the insulator interposed therebetween, and a second electrode provided on the second conduction layer to be given a second voltage different from the first voltage. The first electrode or the second electrode is formed of a metal silicide. | 2008-12-25 |
20080316853 | Internal Vibrator Provided With A Liberation Device - A system for routing telephone calls from a calling party instrument to a called party instrument and involving at least one internet protocol network includes: (a) a first internet protocol interface apparatus effecting a first communicative coupling between the calling party instrument and the at least one internet protocol network; (b) a second internet protocol interface apparatus effecting routing telephone calls according to routing criteria to establish a second communicative coupling between the at least one internet protocol network and the called party instrument; and (c) a call routing system apparatus coupled with the second internet protocol interface apparatus and storing information relating to a geographical or geospatial relationship of calling party instruments and called party instruments. The second internet protocol interface apparatus and the call routing system apparatus cooperate to establish the routing criteria. | 2008-12-25 |
20080316854 | Microfluid mixer - A microfluid mixer is provided. The non-linear electrokineticsis is applied to the design of the microfluid mixer. The microfluid mixer comprises a first and a second microfluidic elements, a mixing reservoir, and a micro channel unit, wherein the micro channel unit has at least two control channels for respectively connecting the first and the second microfluidic elements and the mixing reservoir. When two microfluids are mixed in the mixing reservoir, the electro-osmosis fluid field of the microfluids in the control channel of the mixing reservoir is changed by applying AC signal, such that powerful chaotic mixing effect is therefore produced by the two microfluids in the mixing reservoir. | 2008-12-25 |
20080316855 | Composite Mixer - Devices and methods for mixing a clotting agent with other inputs such as blood, blood derived product, bone marrow, and/or bone marrow derived product to form a congealed mixture. | 2008-12-25 |
20080316856 | Method and System for Calculating and Reporting Slump in Delivery Vehicles - A system for managing a concrete delivery vehicle having a mixing drum | 2008-12-25 |
20080316857 | DEVICE FOR AUTOMATICALLY SHAKING AN INHALER - The invention is concerned with testing of inhalers used for medicament delivery. Such devices are often intended to be first shaken by a user to prepare them, and then fired by operation of some mechanical mechanism. In order to automate testing, the invention provides a shake device having a carriage | 2008-12-25 |
20080316858 | Oscillatory Flow Mixing Reactor - The present invention relates to an oscillatory flow mixing reactor (OPM) oscillatory flow which is designed so that a flow with angular momentum is superposed by means effecting circular acceleration on the mixture flowing in with oscillation, with the result that good mixing of the individual phases of the mixture is achieved with the use of low shear forces. A use of the reactor according to the invention is also disclosed. | 2008-12-25 |
20080316859 | Methods for Controlling Marine Seismic Equipment Orientation During Acquisition of Marine Seismic Data - Methods are described for actively steering a towed marine seismic component using one or more actively controllable control members; reducing the actively steering of the control members during duration of a time window of recording seismic reflections from a sub-surface geological feature of interest; and resuming the actively steering of the control members after the time window. The marine seismic component may be a streamer, a source, or both. Other methods allow measuring initial orientation of a streamer based on measuring static control surface angle of a control surface of an inline steerable bird. This abstract is provided to comply with the rules requiring an abstract, and allow a reader to ascertain the subject matter of the technical disclosure. It will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b). | 2008-12-25 |
20080316860 | Borehole Seismic Acquisition System - A borehole seismic acquisition system is described with a plurality of sensors arranged so as to identify within the data measured by the pressure sensors P- and S-wave related signals converted at the boundary of the borehole into pressure waves, the sensors being best arranged in groups or clusters sensitive to pressure gradients in one or more directions. | 2008-12-25 |
20080316861 | Block-switching in ultrasound imaging - Systems of generating and manipulating an ultrasound beam are disclosed. The system uses selective sets of ultrasound elements to generate an ultrasound beam, scanning the beam over a series of ultrasound elements in order to collected echo data covering an area, and generating an image from the resulting data. The scanning process includes shifting the set of ultrasound elements used to form the ultrasound beam by more than one ultrasound element (block-switching) between each step in the scanning process. This is accomplished without loss of image resolution by using area-forming techniques. The block-switching technique enables use of cross-correlation methods during image construction. | 2008-12-25 |
20080316862 | Point Source Localization Sonar System and Method - A matched-field based sonar system and method of use that supports real-time, three-dimensional acoustic source localization using a mobile, horizontal array. The system receives and processes acoustic array, non-acoustic array, and own-ship navigational data in the matched-field process (MFP). Driven by own-ship and array status, a global bathymetry database and an acoustic environmental model are used to generate replicas for the MFP. If a three-dimensional tracker is assigned, then the tracker will steer the search region to maintain contact on the target of interest. Displays are provided to the user including tracker displays (which provide tracker information), MFP ambiguity surface displays (which support contact localization), and non-acoustic and navigational displays. A control interface allows a user to control the search region in bearing, range, depth, and frequency; assign the three-dimensional tracker function; and control display processing. | 2008-12-25 |
20080316863 | DIRECTIONAL MICROPHONE OR MICROPHONES FOR POSITION DETERMINATION - Directional microphone or microphones for position determination. One or multiple directional microphones are implemented in various locations to perform acoustic wave capture of acoustic waves associated with object (e.g., a player, a gaming object, a game controller, etc.). The generator of such acoustic waves may be co-located with the object (e.g., integrated into the object if the object is a device such as a gaming object, a game controller, etc., or integrated into clothing worn by a player such as on a hat, a jacket, etc.). The acoustic waves described herein may be generated by any number of means/devices including audio output devices, speakers, pulse wave generators, audio oscillators, etc. Moreover, such acoustic waves may be ultrasonic. A game module and/or processing module processes directional vectors associated with positions of the directional microphones when detecting relative maximum amplitude of an acoustic wave emits by an acoustic wave generator. | 2008-12-25 |
20080316864 | SPRING BASED FINE ACOUSTIC WAVEGUIDE - A fine acoustic waveguide comprising an inner spring. The inner spring provides stability to the acoustic waveguide and increases the manufacturing yield. The disclosed methods further comprise the steps of bending the fine acoustic waveguide with the inner spring and placing a securing material over the bent fine acoustic waveguide, optionally by using mold injection, casting, or extrusion coating. | 2008-12-25 |
20080316865 | Ultrasonic Generator System - The system generates resonant ultrasonic vibrations, preferably in a torsional mode. A control circuit monitors, feedback signals therefrom, which are scanned to determine the frequency at which minima occur. The frequency of the ultrasonic signal is then adjusted to the frequency at which the minimum occurs. | 2008-12-25 |
20080316866 | Lightweight acoustic array - An acoustic transducer array and method of baffle construction is presented to provide an improved array for use in underwater installations. The array is presented wherein a significant majority of the acoustic energy receiving surface is formed by lightweight acoustic baffling material while still maintaining a fully functional, fully populated array. The acoustic baffle constructed is incompressible and suitable for deep water operation while demonstrating both improved acoustic performance and positive buoyancy when necessary. In addition, the invention eliminates the non-uniform element to element spacing that occurs between sub-panels in similar arrays. | 2008-12-25 |
20080316867 | Correction apparatus and clock device using the same - A clock device is provided for generating a real-time clock. The clock device includes a frequency generator, a measuring module, a setting module and a timing module. The frequency generator generates a frequency signal. The measuring module is coupled to the frequency generator for measuring the frequency signal and generating a measuring frequency value. The setting module is coupled to the measuring module for generating an error setting value corresponding to the measuring frequency value. The timing module is coupled to the frequency generator and the setting module for compensating the frequency signal according to the error setting value and generating the real-time clock. | 2008-12-25 |
20080316868 | MULTIPLE-COOKING TIMING SYSTEM - The invention comprises a timing system for use in kitchen applications. The timing system includes a potholder or oven mitt with a timing device integrally attached thereto. The timing device contains an audible or visual alarm that alerts the user to the passage of the desired time. The timing device may be removably attached to the potholder or oven mitt. | 2008-12-25 |
20080316869 | Time Piece Provided With a Date Dial - The inventive timepiece provided with a date dial comprises a date disc driven step by step once per 24 hours. The dial of the time piece is provided with unit figures distributed along a circular sector and crossed by a window which is embodied in the form of a circular arc and extends through the entire angular length of the circular sector. A display member connected to the date disc appears in the window and comprises an index of units, FIGS. | 2008-12-25 |
20080316870 | WIRELESS SYNCHRONOUS TIME SYSTEM - A wireless synchronous time system comprising a primary master event device and secondary slave devices. The primary event device receives a global positioning systems “GPS” time signal, processes the GPS time signal, receives a programmed instruction, and broadcasts or transmits the processed time signal and the programmed instruction to the secondary slave devices. The secondary slave devices receive the processed time signal and the programmed instruction, select an identified programmed instruction, display the time, and execute an event associated with the programmed instruction. The primary event device and the secondary devices further include a power interrupt module for retaining the time and the programmed instruction in case of a power loss. | 2008-12-25 |
20080316871 | Drive Device, Particularly for a Clockwork Mechanism - A drive device formed by etching a wafer. The drive device includes a drive element that can sequentially mesh with a driven element and an actuating element that can displace the drive element according to a hysteresis movement thereby driving the driven element. Placement of the drive element on an outer edge of the wafer enables an interfacing of the drive element with a driven element placed opposite therefrom. A clockwork mechanism including a drive device of the aforementioned type and an input gear that can be rotationally driven by the drive device is also provided. | 2008-12-25 |
20080316872 | OPTICAL DEVICE INTEGRATED HEAD - An optical device integrated head having high light utilizing efficiency by decreasing the propagation loss caused from an optical source to a recording medium, conducting by mounting according to compact active alignment method for efficiently guiding a light generated from a laser device to the top end of a head, in which a light source device mounted on a submount has a mirror portion having an inclinated surface to at least a portion of one edge thereof for reflecting an output light from the optical source device at the inclinated surface, a structural member including a lens structure for further allowing a light to pass through the submount, and an optical waveguide disposed passing through a slider for mounting the submount, and the optical source and the slider are positioned by using active alignment of light in a chip-on carrier structure having the optical source device mounted on the submount. | 2008-12-25 |
20080316873 | SYSTEMS AND METHODS FOR IMPROVING PERCEIVED START-UP TIME FOR A DVD PLAYER - Systems and method for initializing the software for an optical disc player are provided. The optical disc player may include an operating system, an application framework, and a disc loader comprising a disc tray. The method may also include, in response to receiving a tray open request, executing a board support package. The package supports a loading of the operating system and may establish a communication protocol with the loader. Finally, the package may execute a disc tray open command code. One embodiment of the method may conclude by loading the operating system. | 2008-12-25 |
20080316874 | Control Method For A Media Transportation Mechanism, And A Media Processing Device - A media transportation mechanism control method and a media processing device can accurately detect the last disc or other media stored in a media storage unit. A transportation arm | 2008-12-25 |
20080316875 | Optical Disc Apparatus for Accessing a Plurality of Optical Discs and Operating Method thereof - The present invention discloses an optical disc apparatus. The optical disc apparatus includes a rotation module for rotating a plurality of optical discs; a plurality of holding plates, which at least includes a first holding plate and a second holding plate, for loading the optical discs; a sled guide bar positioned between the first holding plate and second holding plate on a straight line; an optical pick-up unit for accessing the optical discs; and a sled motor, moveably positioned of sled on the sled guide bar, for loading the optical pick-up unit and driving the optical pick-up unit along the sled guide bar to access each of the optical discs loaded on the holding plates. | 2008-12-25 |
20080316876 | Optical disk - The invention provides an optical disk that enables high-speed reproduction of address signals. A wobble address system for optical disk supports various types of synchronization, such as phase synchronization, bit synchronization, word synchronization, etc., to be established easily with high detection reliability with the use of an self-orthogonal code. Thus, the invention provides a method for easily synchronizing an address signal, i.e., high-speed reproduction of the address signal. Further, by virtue of an efficient modulation system of the address signal and redundancy thereof, it becomes possible to detect address information with high reliability. This capability is particularly effective in optical recording/reproduction with a blue light source whose signal light quantity and reproduction quality are prone to reduce. Moreover, other additional data of the address data is preserved in the wobbles, which provides medium information to a rewritable optical disk without using embossed pits such that a high-reliability disk (with enhanced security) is realized with a low cost and easily. | 2008-12-25 |
20080316877 | Control Method for an Optical Drive with Different Bandwidths - The present invention discloses a method for controlling the position of a radiation beam on an optical carrier ( | 2008-12-25 |
20080316878 | METHOD FOR MEASURING THICKNESS AND MEASURING DEVICE USING THE SAME - A method for measuring thickness of a transparent layer and a measuring device using the same are provided. The transparent layer has a first face, a second face and a normal direction. The method includes the following steps. First, a light beam with a focal point is emitted to the transparent layer. Next, a focus error signal (FES) is generated according to a refracted beam of the light beam. Then, the focal point is moved along the normal direction and passes through the first face and the second face. The FES converts into a first focus error curve and a second focus error curve respectively when the focal point passes through the first and the second face. Afterwards, the thickness of the transparent layer is obtained according to the first focus error curve and the second focus error curve. | 2008-12-25 |
20080316879 | Recording Medium, Recording Apparatus and Method, Data Processing Apparatus and Method and Data Outputting Apparatus - Disclosed is an apparatus for reproducing main data under an optimum reproduction environment. The reproducing apparatus includes a readout unit ( | 2008-12-25 |
20080316880 | INFORMATION RECORDING MEDIUM, AND RECORDING METHOD AND REPRODUCING METHOD THEREOF - An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array. | 2008-12-25 |
20080316881 | Recording Apparatus and Recording Method, Reproducing Apparatus and Reproducing Method, and Program - The present invention relates a recording apparatus and a recording method, a reproducing apparatus and a reproducing method, and a program that make it possible to easily judge whether data was recorded in a recording medium by an apparatus of own model. An own model/another model information generating unit | 2008-12-25 |
20080316882 | Optical Drive and Method For Determining a Reading and/or Writing Position - The invention relates to an optical drive ( | 2008-12-25 |
20080316883 | RECORDING MEDIUM DETECTION DEVICE - A device enabling simple detection of a recording medium placed on a tray includes at least two electrodes arranged on the tray, an electric field sensor connected to the electrodes, and a control circuit connected to the electric field sensor. The electric field sensor detects capacitance in accordance with the distance between the electrodes relative to the recording medium placed on the tray. The control circuit determines the recording media type of the recording medium based on the capacitance detected by the electric field sensor. | 2008-12-25 |
20080316884 | MULTI-LAYERED INFORMATION RECORDING MEDIUM, REPRODUCTION APPARATUS, RECORDING APPARATUS, REPRODUCTION METHOD, AND RECORDING METHOD - A multi-layered information recording medium comprising a plurality of recording layers, a user data area for recording user data, provided in at least two of the plurality of recording layers, and a defect list storing area for storing a defect list. When at least one defective area is detected in the user data area, the defect list is used to manage the at least one defective area. | 2008-12-25 |
20080316885 | METHOD OF RECORDING ERASE PATTERN INFORMATION ON AN OPTICAL RECORDING MEDIUM, ERASING INFORMATION ON THE OPTICAL RECORDING MEIDUM BASED ON THE ERASE PATTERN INFORMATION, AND OPTICAL RECORDING MEDIUM THEREFOR - An optical recording medium is provided for allowing data to be recorded on, erased from, and reproduced from, and storing information about power levels of an erase pulse. The recorded erase pattern information may include information about power levels of first and last pulses of an erase pattern for erasing data. The first and last pulses of the erase pattern can be differently set depending on the differing kind of recording layer or layers of a disk or differing kinds of disks and recorded in a reproducible only area or rewritable area of the optical recording medium. Thus, by presetting the appropriate erase power levels, the time required for selecting an optimal erase power for the optical recording medium can be considerably reduced. | 2008-12-25 |
20080316886 | RECORDING MEDIUM FOR STORING VERSION INFORMATION FOR MAINTAINING RECORDING AND/OR REPRODUCING COMPATIBILITY, AND METHOD AND APPARATUS FOR MANAGING THE SAME - A method of recording read/write compatibility information on an optical disc and a recording medium employing the method. Extended part version information, latest part version having recording capability, and latest part version having reproducing capability are stored in n.xy form on 6 bytes of a reserved zone of a physical format information zone of the optical disc. A recording/reproducing apparatus to record extended part version information on a reserved zone of a physical format information zone of a recording medium. The recording/reproducing apparatus has a base part version and a comparing unit to determine recording/reproducing compatibility with a recording medium having a detailed extended part version stored in a reserved zone of a physical format information zone. | 2008-12-25 |
20080316887 | Game system and method employing reversible voice recorder - A handheld recording device and a method of play that can be played with either one or two recording devices. Each recording device has a microphone for converting sound into an electronic sound signal. The recording device also has a digital memory with a limited sound recording capacity. The digital memory records the sound signal when a record button is pressed. A backward play button is also located on the recording device. The backward play button causes any sound signal recorded in the digital memory to play backward and be broadcast through a speaker. A game is played using one or two of the recording devices. A first player records a message and plays it backwards. The other players can decipher the backward message by recording it in their own recording device and playing the backward message in reverse. | 2008-12-25 |