52nd week of 2008 patent applcation highlights part 15 |
Patent application number | Title | Published |
20080315186 | Organic Semiconductor Device and Organic Semiconductor Thin Film - An organic semiconductor device includes a channel forming region including an organic semiconductor thin film which is composed of an organic semiconductor material having an oxidation or reduction mechanism in units of two-π-electrons and a two- or three-dimensional conduction path. It is thus possible to provide an organic semiconductor device including an organic semiconductor thin film based on an organic semiconductor thin film composed of an organic semiconductor material which can be dissolved in an organic solvent at a low temperature (e.g., room temperature) and is suitable for use in a coating process. | 2008-12-25 |
20080315187 | ENHANCING PERFORMANCE CHARACTERISTICS OF ORGANIC SEMICONDUCTING FILMS BY IMPROVED SOLUTION PROCESSING - Improved processing methods for enhanced properties of conjugated polymer films are disclosed, as well as the enhanced conjugated polymer films produced thereby. Addition of low molecular weight alkyl-containing molecules to solutions used to form conjugated polymer films leads to improved photoconductivity and improvements in other electronic properties. The enhanced conjugated polymer films can be used in a variety of electronic devices, such as solar cells and photodiodes. | 2008-12-25 |
20080315188 | Apparatus and method for depositing thin film - In a thin film depositing apparatus, a first reaction gas, a second reaction gas, and a non-volatile gas are supplied to a reaction chamber in order to form a protective layer, in which an organic layer and an inorganic layer are alternately stacked, on a process substrate. The first reaction gas is supplied to the reaction chamber only while the inorganic layer is formed on the process substrate, and the second reaction gas and the non-volatile gas are supplied to the reaction chamber through while the inorganic and organic layers are formed on the process substrate. Thus, the discontinuous surfaces may be prevented from being formed between the organic layer and the inorganic layer, thereby preventing the peeling of the organic and inorganic layers and increasing light transmittance. | 2008-12-25 |
20080315189 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An organic light emitting diode (OLED) display device and a method of fabricating the same capable of minimizing the number of process operations and a decrease in aperture ratio. The OLED display device includes a compensation circuit to compensate for a threshold voltage of a driving transistor. A pixel circuit of the OLED display device can be stably driven, can minimize a threshold voltage of a driving transistor using a minimized structure, and can increase an aperture ratio of the display device. | 2008-12-25 |
20080315190 | Organic Thin Film Transistor and Method for Surface Modification of Gate Insulating Layer of Organic Thin Film Transistor - This invention provides an organic thin film transistor, which can realize the modification of the surface of a gate insulating layer not only the case where the gate insulating layer is formed of an oxide, but also the case where the gate insulating layer is formed of a material other than the oxide and consequently can significantly improve transistor characteristics, and a method for surface modification of a gate insulating layer in the organic thin film transistor. In an organic thin film transistor comprising a gate insulating layer, an organic semiconductor layer stacked on the gate insulating layer, and an electrode provided on the organic semiconductor layer, a polyparaxylylene layer formed of a continuous polyparaxylylene film is formed on the surface of the gate insulating layer, between the gate insulating layer and the organic semiconductor layer, so as to face and contact with the organic semiconductor layer. | 2008-12-25 |
20080315191 | Organic Thin Film Transistor Array and Method of Manufacturing the Same - An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like. | 2008-12-25 |
20080315192 | Integrated Circuit Comprising an Organic Semiconductor, and Method for the Production of an Integrated Circuit - An embodiment of the invention provides an integrated circuit having an organic field effect transistor (OFET) with a dielectric layer. The dielectric layer is prepared from a polymer formulation comprising: about 100 parts of at least one crosslinkable base polymer, from about 10 to about 20 parts of at least one di- or tribenzyl alcohol compound as an electrophilic crosslinking component, from about 0.2 to about 10 parts of at least one photo acid generator, and at least one solvent. Another embodiment provides a semiconductor fabrication method. The method comprises applying the polymer formulation to a surface of a substrate, drying the polymer formulation, crosslinking the polymer formulation after drying, and baking the polymer formulation after crosslinking. | 2008-12-25 |
20080315193 | Oxide-based thin film transistor, method of fabricating the same, zinc oxide etchant, and a method of forming the same - Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession. | 2008-12-25 |
20080315194 | Oxide semiconductors and thin film transistors comprising the same - Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Ta and Y atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Ta and Y atoms added thereto. | 2008-12-25 |
20080315195 | Method and Apparatus for Monitoring VIA's in a Semiconductor Fab - A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured. | 2008-12-25 |
20080315196 | TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER - The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed. | 2008-12-25 |
20080315197 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a substrate of single crystal silicon; a first device formed in a first region of a surface of the substrate; a first interlayer insulating film formed on the substrate; a polycrystalline silicon layer formed in a second region on the first interlayer insulating film; a second device formed in the polycrystalline silicon layer; a second interlayer insulating film formed on the first interlayer insulating film, the second interlayer insulating film covering the polycrystalline silicon layer; and a pad formed in a third region on the second interlayer insulating film. The second region includes at least part of a directly overlying zone of the first region. The third region includes at least part of a region which is the directly overlying zone of the first region and a directly overlying zone of the second region. | 2008-12-25 |
20080315198 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a manufacturing method thereof are provided. The sensor includes a substrate, a bottom electrode, an intrinsic layer and a first conductive layer formed over the substrate, a diffusion barrier film formed over the first conductive layer, and an upper transparent electrode formed over the diffusion barrier film. Therefore, a vertical integration of a transistor circuitry and a photodiode can be provided. Further, the leakage current is prevented and the photosensitivity is increased by performing the plasma treatment on the first conductive layer. Due to the vertically integrated transistor circuitry and photodiode, the fill factor can approach 100%, and higher sensitivity compared with the related art having the same pixel size can be provided. The sensitivity of each unit pixel is not reduced, even though more complex circuitry is realized on the image sensor. | 2008-12-25 |
20080315199 | THIN FILM TRANSISTOR MANUFACTURING METHOD, THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME - A thin film transistor manufacturing method includes the steps of: forming a gate electrode, gate insulating film and amorphous silicon film in succession on an insulating substrate; forming a channel protective film only in the region which will serve as a channel region of the amorphous silicon film; and forming an n-plus silicon film and metal layer on top of the channel protective film and amorphous silicon film in succession. The method further includes the step of patterning the amorphous silicon film and n-plus silicon film to selectively leave the region associated with source and drain electrodes, using the channel protective film as an etching stopper to selectively remove the region of the n-plus silicon film and metal layer associated with the channel region so as to form source and drain regions from the n-plus silicon film and also form source and drain electrodes from the metal layer. | 2008-12-25 |
20080315200 | Oxide semiconductors and thin film transistors comprising the same - Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Hf and Cr atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Hf and Cr atoms added thereto. | 2008-12-25 |
20080315201 | Apparatus for Producing Electronic Device Such as Display Device, Method of Producing Electronic Device Such as Display Device, and Electronic Device Such as Display Device - An object of the present invention is to reduce an adverse effect of an atmosphere in a heat treatment device used in production of an electronic device, imparted on characteristics of the produced electronic device. To attain the object, an inner surface of the heat treatment device is covered with an oxide passive-state film and bringing the surface roughness of the inner surface to 1 μm or less in terms of a central mean roughness Ra. According to this type of heat treatment device, in curing a heat curable resin, deterioration in the heat curable resin caused by decomposition or dissociation of the heat curable resin, can be reduced. | 2008-12-25 |
20080315202 | DISPLAY DEVICE - A resin material having a small relative dielectric constant is used as a layer insulation film | 2008-12-25 |
20080315203 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY DEVICE - Disclosed herein is a TFT substrate which exhibits good characteristic properties despite the omission of the barrier metal layer to be normally interposed between the source-drain electrodes and the semiconductor layer in the TFT. The TFT substrate permits sure and direct connection with the semiconductor layer of the TFT. The thin film transistor substrate has a substrate, a semiconductor layer and source-drain electrodes. The source-drain electrodes are composed of oxygen-containing layers and thin films of pure copper or a copper alloy. The oxygen-containing layer contains oxygen such that part or all of oxygen combines with silicon in the semiconductor layer. And, the thin films of pure copper or a copper alloy connect with the semiconductor layer of the thin film transistor through the oxygen-containing layers. | 2008-12-25 |
20080315204 | Thin Film Transistor, and Active Matrix Substrate and Display Device Provided with Such Thin Film Transistor - Improves the electric current driving capability of a thin film transistor without the yield being decreased due to a defective leak between a source electrode/drain electrode and a gate electrode or due to a decrease in an off-characteristic. | 2008-12-25 |
20080315205 | Display device and manufacturing method thereof - It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. | 2008-12-25 |
20080315206 | Highly Scalable Thin Film Transistor - Shrinking the dimensions of PMOS or NMOS thin film transistors is limited by dopant diffusion. In these devices an undoped or lightly doped channel region is interposed between heavily doped source and drain regions. When the device is built with very short gate length, source and drain dopants will diffuse into the channel, potentially shorting it and ruining the device. A suite of innovations is described which may be used in various combinations to minimize dopant diffusion during fabrication of a PMOS or NMOS polycrystalline thin film transistor, resulting in a highly scalable thin film transistor. This transistor is particularly suitable for use in a monolithic three dimensional array of stacked device levels. | 2008-12-25 |
20080315207 | METHOD OF FABRICATING POLYCRYSTALLINE SILICON, TFT FABRICATED USING THE SAME, METHOD OF FABRICATING THE TFT, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE TFT - A method of fabricating a polycrystalline silicon (poly-Si) layer includes providing a substrate, forming an amorphous silicon (a-Si) layer on the substrate, forming a thermal oxide layer to a thickness of about 10 to 50 Å on the a-Si layer, forming a metal catalyst layer on the thermal oxide layer, and annealing the substrate to crystallize the a-Si layer into the poly-Si layer using a metal catalyst of the metal catalyst layer. Thus, the a-Si layer can be crystallized into a poly-Si layer by a super grain silicon (SGS) crystallization method. Also, the thermal oxide layer may be formed during the dehydrogenation of the a-Si layer so that an additional process of forming a capping layer required for the SGS crystallization method can be omitted, thereby simplifying the fabrication process. | 2008-12-25 |
20080315208 | Semiconductor device and manufacturing method thereof - [Problem] A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. | 2008-12-25 |
20080315209 | Group III Nitride Semiconductor Device and Epitaxial Substrate - Affords a Group III nitride semiconductor device having a structure that can improve the breakdown voltage. A Schottky diode ( | 2008-12-25 |
20080315210 | High electron mobility transistor - A GaN-based semiconductor layer is stacked on a GaN-based single-crystal substrate. The GaN-based single-crystal substrate forms an electron transit layer, and the GaN-based semiconductor layer forms an electron supply layer. A principal growth plane of the GaN-based single-crystal substrate is an m-plane, and a principal growth plane of the GaN-based semiconductor layer formed on the GaN-based single-crystal substrate is also an m-plane. With such a layer structure, no piezoelectric field is generated since the m-plane is a nonpolar plane. This suppresses generation of a two-dimensional electron gas layer at the time when no gate voltage is applied and consequently enables achievement of a normally-off configuration. | 2008-12-25 |
20080315211 | SIC semiconductor device with BPSG insulation film and method for manufacturing the same - A SiC device includes: a substrate; a drift layer; a base region; a source region; a channel layer connecting the drift layer and the source region; a gate oxide film on the channel layer and the source region; a gate electrode on the gate oxide film; an interlayer insulation film with a contact hole having a barrier layer and a BPSG insulation film on the gate electrode; a source electrode having upper and lower wiring electrodes on the interlayer insulation film and in the contact hole for connecting the base region and the source region; and a drain electrode on the substrate. The barrier layer prevents a Ni component in the lower wiring electrode from being diffused into the BPSG insulation film. | 2008-12-25 |
20080315212 | METHOD FOR FABRICATING A P-TYPE SEMICONDUCTOR STRUCTURE - One embodiment of the present invention provides a method for fabricating a group III-V p-type nitride structure. The method comprises growing a first layer of p-type group III-V material with a first acceptor density in a first growing environment. The method further comprises growing a second layer of p-type group III-V material, which is thicker than the first layer and which has a second acceptor density, on top of the first layer in a second growing environment. In addition, the method comprises growing a third layer of p-type group III-V material, which is thinner than the second layer and which has a third acceptor density, on top of the second layer in a third growing environment. | 2008-12-25 |
20080315213 | Process for Producing an Electroluminescent P-N Junction Made of a Semiconductor Material by Molecular Bonding - A method for making an electroluminescent PN junction includes molecular bonding a face in a crystalline semiconducting material doped with a first type of a first element with a face in a crystalline semiconducting material doped with a second type opposite to the first type, of a second element, at a bonding interface. The semiconducting material has an indirect forbidden band. The crystalline lattices shown by the faces are shifted in rotation by a predetermined angle so as to at least cause formation of a network of screw type dislocations at the bonding interface. | 2008-12-25 |
20080315214 | Solderless Integrated Package Connector and Heat Sink for LED - Standard solderless connectors extend from a molded package body supporting at least one high power LED. The package includes a relatively large metal slug extending completely through the package. The LED is mounted over the top surface of the metal slug with an electrically insulating ceramic submount in-between the LED and metal slug. Electrodes on the submount are connected to the package connectors. Solderless clamping means, such as screw openings, are provided on the package for firmly clamping the package on a thermally conductive mounting board. The slug in the package thermally contacts the board to sink heat away from the LED. Fiducial structures (e,g., holes) in the package precisely position the package on corresponding fiducial structures on the board. Other packages are described that do not use a molded body. | 2008-12-25 |
20080315215 | Semiconductor Module - A semiconductor module (A | 2008-12-25 |
20080315216 | Terahertz Electromagnetic Wave Radiation Element and Its Manufacturing Method - The present invention improves the efficiency of conversion from a non-radiation two-dimensional electron plasmon wave into a radiation electromagnetic wave, and realizes a wide-band characteristic. A terahertz electromagnetic wave radiation element of the present invention comprises a semiinsulating semiconductor bulk layer, a two-dimensional electron layer formed directly above the semiconductor bulk layer by a semiconductor heterojunction structure, source and drain electrodes electrically connected to two opposed sides of the two-dimensional electron layer, a double gate electrode grating which is provided in the vicinity of and parallel to the upper surface of the two-dimensional electron layer and for which two different dc bias potentials can be alternately set, and a transparent metal mirror provided in contact with the lower surface of the semiconductor bulk layer, formed into a film shape, functioning as a reflecting mirror in the terahertz band, and being transparent in the light wave band. Two light waves are caused to enter from the lower surface of the transparent metal mirror, and two different dc bias potentials are alternately applied to the double gate electrode grating so as to periodically modulate the electron density of the two-dimensional electron layer in accordance with the configuration of the double gate electrode grating. | 2008-12-25 |
20080315217 | Semiconductor Light Source and Method of Producing Light of a Desired Color Point - This invention relates to a solid-state light source ( | 2008-12-25 |
20080315218 | Cubic illuminators - An exemplary illuminator includes a first electrode, a second electrode, and a light-emitting chip. The light-emitting chip includes light-emitting layers arranged three-dimensionally. The first and second electrodes are configured for providing different voltages to the light-emitting chip, and the light-emitting chip is capable of emitting light simultaneously along all dimensional axes. | 2008-12-25 |
20080315219 | LIGHT EMITTING DIODE LIGHT SOURCE DEVICE - A light emitting diode (LED) light source device includes a plurality of LED modules, a base and a clip. The base has a first base body, a second base body, and a third base body. The second base body and the third base body extend from two sides of the first base body and are corresponding to each other. The LED modules are provided at inside surfaces of the first base body, the second base body and the third base body. The clip holds the LED modules and fastens the second base body and the third base body to enable the LED modules to be tightly assembled at the base. | 2008-12-25 |
20080315220 | High Light Efficiency Solid-State Light Emitting Structure And Methods To Manufacturing The Same - In one embodiment of an epitaxial LED device, a buffer layer (e.g. dielectric layer) between the current spreading layer and the substitute substrate comprises a plurality of vias and has a refractive index that is below that of the current spreading layer. A reflective metal layer between the buffer layer and the substitute substrate is connected to the current spreading layer through the vias in the buffer layer. The buffer layer separates the current spreading layer from the reflective metal layer. In yet another embodiment, stress management is provided by causing or preserving stress, such as compressive stress, in the LED so that stress in the LED is reduced when it experiences thermal cycles. In one implementation of this embodiment, a layer is attached to the LED and reflective metal layer, and causes or preserves stress in the LED along one or more directions parallel to an interface between the LED epitaxial layers so that stress in the LED is reduced in said one or more directions when temperature of the structure is increased. | 2008-12-25 |
20080315221 | NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a nitride-based semiconductor device capable of reducing contact resistance between a nitrogen face of a nitride-based semiconductor substrate or the like and an electrode is provided. This method of fabricating a nitride-based semiconductor device comprises steps of etching the back surface of a first semiconductor layer consisting of either an n-type nitride-based semiconductor layer or a nitride-based semiconductor substrate having a wurtzite structure and thereafter forming an n-side electrode on the etched back surface of the first semiconductor layer. | 2008-12-25 |
20080315222 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor light emitting device and a method of manufacturing the same are provided. The semiconductor light emitting device comprises a substrate, a mask seed layer formed on the substrate and comprising a TI group element, a nitride layer formed on the mask seed layer and comprising a III group element, a first conductive semiconductor layer on the nitride layer, an active layer on the first conductive layer, and a second conducive semiconductor layer on the active layer. | 2008-12-25 |
20080315223 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a light emitting device comprising a first conductive type semiconductor layer, an active layer, a semiconductor layer comprising Al, a high-concentration semiconductor layer, a low-mole In | 2008-12-25 |
20080315224 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting device and a method of fabricating the same, The light emitting device comprises: a first conductive semiconductor layer; an active layer comprising an InGaN well layer and a GaN barrier layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The GaN barrier layer comprises an AlGaN layer. | 2008-12-25 |
20080315225 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided are a semiconductor light emitting device and a method of manufacturing the same. The semiconductor light emitting device comprises a p-type substrate, a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. The p-type semiconductor layer is formed on the p-type substrate. The active layer is formed on the p-type semiconductor layer. The n-type semiconductor layer is formed on the active layer. | 2008-12-25 |
20080315226 | LIGHT EMITTING DIODE, OPTOELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - A light emitting diode structure including a substrate, a strain-reducing seed layer, an epitaxial layer, a first electrode and a second electrode is provided. The strain-reducing seed layer having a plurality of clusters is disposed on the substrate, and the material of the clusters is selected from a group consisting of aluminum nitride, magnesium nitride and indium nitride. The epitaxial layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The first electrode is disposed on the exposed first type doped semiconductor layer and electrically connected thereto. The second electrode is disposed on the second type doped semiconductor layer and electrically connected thereto. | 2008-12-25 |
20080315227 | Light-Emitting Diode Arrangement - A light-emitting diode arrangement is disclosed, comprising at least one light-emitting diode (LED) chip with a radiation decoupling surface through which a large portion of the electromagnetic radiation generated in the LED chip exits in a main direction of emission; a housing laterally surrounding the LED chip; and a reflective optic disposed after the radiation decoupling surface in the main direction of emission. The LED arrangement is particularly well suited for use in devices such as camera-equipped cell phones, digital cameras or video cameras. | 2008-12-25 |
20080315228 | LOW PROFILE SIDE EMITTING LED WITH WINDOW LAYER AND PHOSPHOR LAYER - Low profile, side-emitting LEDs are described that generate white light, where all light is emitted within a relatively narrow angle generally parallel to the surface of the light-generating active layer. The LEDs enable the creation of very thin backlights for backlighting an LCD. In one embodiment, the LED emits blue light and is a flip chip with the n and p electrodes on the same side of the LED. Separately from the LED, a transparent wafer has deposited on it a red and green phosphor layer. The phosphor color temperature emission is tested, and the color temperatures vs. positions along the wafer are mapped. A reflector is formed over the transparent wafer. The transparent wafer is singulated, and the phosphor/window dice are matched with the blue LEDs to achieve a target white light color temperature. The phosphor/window is then affixed to the LED. | 2008-12-25 |
20080315229 | Light-Emitting Device Comprising Conductive Nanorods as Transparent Electrodes - Disclosed herein is an electrical light-emitting device including a transparent conductive nanorod type electrode, in which transparent conductive nanorods grown perpendicular to a light-emitting layer are used as the electrode. Hence, light is not absorbed by the electrode, and tunneling easily occurs due to nanocontact of the nanorods, thus increasing current injection efficiency, and also, total internal reflections decrease. Thereby, the light-emitting device according to this invention has light-emitting properties and luminous efficiency superior to conventional light-emitting devices, including metal electrodes or thin film type transparent electrodes. | 2008-12-25 |
20080315230 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC COMPONENT DEVICE - An electronic component package, includes a package substrate portion constructed by a silicon substrate in which a through hole is provided, an insulating layer formed on both surface sides of the silicon substrate and an inner surface of the through hole, and a through electrode filled in the through hole, and a frame portion provided upright on a peripheral portion of the package substrate portion to constitute a cavity on the silicon substrate, wherein an upper surface of the through electrode in the cavity is planarized such that a height of the through electrode is set equal to a height of the insulating layer. The frame portion is joined to the package substrate portion by the low-temperature joining utilizing the plasma process after the through electrode is planarized. | 2008-12-25 |
20080315231 | LIGHT SOURCE, OPTICAL PICKUP, AND ELECTRONIC APPARATUS - A light source of the present invention includes: a semiconductor light emitting device which has a light emitting face and emits light from part of the light emitting face; a container which has a light transmitting window for transmitting the light and accommodates the semiconductor light emitting device; and a gettering portion for performing gettering of a material containing at least one of carbon and silicon. The gettering portion is positioned, in the container, in a region other than the part of the light emitting face of the semiconductor light emitting device. | 2008-12-25 |
20080315232 | LIGHT-EMITTING SEMICONDUCTOR DEVICE - A light-generating semiconductor region is grown on a substrate of electroconductive silicon or like light-absorptive material. An anode is placed atop the light-generating semiconductor region, and a cathode under the substrate. The light-generating semiconductor region and the substrate are encapsulated in an epoxy envelope. In order to prevent the substrate from absorbing the light that has been radiated from the light-generating semiconductor region and reflected back from the envelope, the substrate has its side surfaces covered by a reflector layer. The reflector layer has its surfaces roughened, as a result of the roughening of the underlying substrate surfaces by dicing, for scattering the incident light. | 2008-12-25 |
20080315233 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Provided is a semiconductor light emitting device. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, a second conductive type super lattice layer, and a second conductive type semiconductor layer. The active layer is formed on the first conductive type semiconductor layer. The second conductive type super lattice layer comprises a second conductive type nitride layer and an undoped nitride layer on the active layer. The second conductive type semiconductor layer is formed on the second conductive type super lattice layer. | 2008-12-25 |
20080315234 | Optically Active Compositions and Combinations of Same with Indium Gallium Nitride Semiconductors - New combinations of semi-conductor devices in conjunction with optically active materials are set forth herein. In particular, light emitting semiconductors fashioned as diodes from indium gallium nitride construction are combined with high-performance optically active Langasite La3GasSi0i4 crystalline materials. When Langasite is properly doped, it will respond to the light output emissions of the diode by absorbing high energy photons therefrom and reemitting light of longer wavelengths. High-energy short wavelength light mixes with the longer wavelengths light to produce a broad spectrum which may be perceived by human observers as white light. Langasite, a relatively new material, enjoying great utility in frequency control and stabilization schemes has heretofore never been used in combination with optical emission systems. | 2008-12-25 |
20080315235 | Light emitting device - A light emitting device is provided that has a semiconductor light emitting element and a phosphor which converts a part of the luminescence spectrum emitted from the semiconductor light emitting element. The luminescence spectrum of the semiconductor light emitting element is located between a near ultraviolet region and a short-wavelength visible region, and the phosphor is made by adding a red luminescent activator to a base material of a blue luminescent phosphor. Thereby, improving the color shading generated by the dispersion of the spectra of the light emitting elements and obtaining the light emitting device having a high brightness and a good color rendering properties. With the light emitting device, it is possible to provide the light sources for the lighting apparatus of medical treatments, the flash plate of a copying machine, etc., in which a good color rendering property is required. | 2008-12-25 |
20080315236 | Optoelectronic semiconductor device and manufacturing method thereof - An embodiment of the invention discloses an optoelectronic semiconductor device comprising a semiconductor system capable of performing a conversion between light energy and electrical energy; an interfacial layer formed on at least two surfaces of the semiconductor system; an electrical conductor; and an electrical connector electrically connecting the semiconductor system to the electric conductor. | 2008-12-25 |
20080315237 | Gallium Nitride-Based Compound Semiconductor Light Emitting Device - This gallium nitride-based compound semiconductor light emitting device includes an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are composed of gallium nitride-based compound semiconductors and are deposited in that order on a substrate, and further includes a negative electrode and a positive electrode that are in contact with the n-type semiconductor layer and the p-type semiconductor layer, respectively, wherein the positive electrode has a translucent electrode composed of a three-layer structure including a contact metal layer that contacts at least the p-type semiconductor layer, a current diffusion layer provided on the contact metal layer and having conductivity greater than that of the contact metal layer, and a bonding pad layer provided on the current diffusion layer, and a mixed positive electrode-metal layer including a metal that forms the contact metal layer is present in a positive electrode side surface of the p-type semiconductor layer. | 2008-12-25 |
20080315238 | Porous Circuitry Material for Led Submounts - A submount comprising a ceramic substrate and a circuitry arranged thereon is provided. The circuitry comprises an electrically conducting porous material comprising at least one noble metal doped with at least one non-noble metal, the surface of at least portions of said electrically conducting porous material comprises oxides of said non-noble metals, and said ceramic substrate is bonded to said porous electrically conducting material via said oxides of said non-noble metals. | 2008-12-25 |
20080315239 | THIN DOUBLE-SIDED PACKAGE SUBSTRATE AND MANUFACTURE METHOD THEREOF - The present invention discloses a manufacture method for a thin double-sided package substrate, which includes steps: providing a carrier; respectively forming a first conductive layer and a second conductive layer on the upper and lower surfaces of the carrier; forming a through-hole penetrating the first conductive layer and the carrier but not penetrating the second conductive layer; setting a conductive element in the through-hole to electrically connect the first conductive layer with the second conductive layer; forming desired circuits on the first conductive layer and/or the second conductive layer; forming a first metal layer on the first conductive layer and/or the second conductive layer; and removing the carrier located in a predetermined region to form a chip receiving bay. The present invention also discloses a package substrate made by the abovementioned manufacture method, which can reduce the overall thickness of a chip package structure, increase the heat-dissipation effect of the chip and prevent the chip package structure from humidity penetration. | 2008-12-25 |
20080315240 | III-Nitride Semiconductor light Emitting Device - The present disclosure relates to an III-nitride semiconductor light emitting device, particularly, an electrode structure thereof. The III-nitride semiconductor light emitting device includes a substrate, a plurality of III-nitride semiconductor layers grown on the substrate, and composed of a first III-nitride semiconductor layer with first conductivity, a second III-nitride semiconductor layer with second conductivity different from the first conductivity, and an active layer positioned between the first III-nitride semiconductor layer and the second III-nitride semiconductor layer, for generating light by recombination of electrons and holes, and a hole passing through the substrate and the plurality of III-nitride semiconductor layers. | 2008-12-25 |
20080315241 | Surface Mountable Chip - A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer. | 2008-12-25 |
20080315242 | System, apparatus and method of selective laser repair for metal bumps of semiconductor device stack - Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be separated. The operation of a control unit and a driving unit may position a laser unit such that a laser beam may be irradiated at the damaged and/or defective metal bump. An X-ray inspection unit may obtain information about the damaged and/or defective metal bump. | 2008-12-25 |
20080315243 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A group III nitride semiconductor light-emitting device comprises an n-type gallium nitride-based semiconductor layer, a first p-type Al | 2008-12-25 |
20080315244 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - Provided are a light emitting diode (LED) and a method for manufacturing the same. The LED includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The active layer includes a well layer and a barrier layer that are alternately laminated at least twice. The barrier layer has a thickness at least twice larger than a thickness of the well layer. | 2008-12-25 |
20080315245 | Nitride-based semiconductor substrate and semiconductor device - A nitride-based semiconductor substrate has a diameter of 25 mm or more, a thickness of 250 micrometers or more, a n-type carrier concentration of 1.2×10 | 2008-12-25 |
20080315246 | TRANSISTOR SWITCH CIRCUIT AND SAMPLE-AND-HOLD CIRCUIT - A transistor switch circuit includes: a MOS transistor in which a channel is formed when a gate-source voltage is zero; and a voltage supply part which is connected to a gate of the MOS transistor to supply the gate with a voltage for turning off the MOS transistor. | 2008-12-25 |
20080315247 | BONDED-WAFER SUPERJUNCTION SEMICONDUCTOR DEVICE - A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack. | 2008-12-25 |
20080315248 | Semiconductor Device Having Igbt Cell and Diode Cell and Method for Designing the Same - A semiconductor device includes: a semiconductor substrate; an IGBT cell; and a diode cell. The substrate includes a first layer on a first surface, second and third layers adjacently arranged on a second surface of the substrate and a fourth layer between the first layer and the second and third layers. The first layer provides a drift layer of the IGBT cell and the diode cell. The second layer provides a collector layer of the IGBT cell. The third layer provides one electrode connection layer of the diode cell. A resistivity ρ | 2008-12-25 |
20080315249 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided. | 2008-12-25 |
20080315250 | INSULATED GATE SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A trench-type insulated-gate semiconductor device is disclosed that includes unit cells having a trench gate structure that are scattered uniformly throughout the active region of the device. The impurity concentration in the portion of a p-type base region, sandwiched between an n+-type emitter region and an n-type drift layer and in contact with a gate electrode formed in the trench via a gate insulator film, is the lowest in the portion thereof sandwiched between the bottom plane of n+-type emitter regions and the bottom plane of p-type base region and parallel to the major surface of a silicon substrate. The trench-type insulate-gate semiconductor device according to the invention minimizes the variation of the gate threshold voltage. | 2008-12-25 |
20080315251 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device and/or a method for fabricating a semiconductor device (e.g. fabricating an LIGBT) that may minimize occurrences of latch-up due to increases of hole current. A semiconductor device and/or a method of fabricating a semiconductor device that may prevent and/or eliminate latch-up due to operation of a parasitic thyrister without significantly deteriorating performances of significant parameters considered when fabricating a high voltage power control device. | 2008-12-25 |
20080315252 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor provides enhanced integration of transistor circuitry and photo diodes. The image sensor simultaneously improves resolution and sensitivity. An image sensor an a method for manufacturing prevents defects in a photo diode by adopting a vertical photo diode structure. An image sensor includes a substrate which may include at least one circuit element. A bottom electrode and a first conductive layer may be sequentially formed over the substrate. A strained intrinsic layer may be formed over the first conductive layer. A second conductive layer may be formed over the strained intrinsic layer. An upper electrode may be formed over the second conductive layer. | 2008-12-25 |
20080315253 | FRONT AND BACKSIDE PROCESSED THIN FILM ELECTRONIC DEVICES - This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits. | 2008-12-25 |
20080315254 | SEMICONDUCTOR DEVICE FABRICATION METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR LAYER FORMATION METHOD - A semiconductor device fabrication method and a semiconductor layer formation method for making a semiconductor layer having excellent morphology selectively epitaxial-grow over a semiconductor, and a semiconductor device. When a recessed source/drain pMOSFET is fabricated, a gate electrode is formed over a Si substrate in which STIs are formed with a gate insulating film therebetween (step S | 2008-12-25 |
20080315255 | Thermal Expansion Transition Buffer Layer for Gallium Nitride on Silicon - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate with a first thermal expansion coefficient (TEC), and forms a silicon-germanium (SiGe) film overlying the Si substrate. A buffer layer is deposited overlying the SiGe film. The buffer layer may be aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN). A GaN film is deposited overlying the buffer layer having a second TEC, greater than the first TEC. The SiGe film has a third TEC, with a value in between the first and second TECs. In one aspect, a graded SiGe film may be formed having a Ge content ratio in a range of about 0% to 50%, where the Ge content increases with the graded SiGe film thickness. | 2008-12-25 |
20080315256 | Nitride semiconductor device - A nitride semiconductor device according to the present invention includes: a nitride semiconductor laminated structure comprising a first layer made of a Group III nitride semiconductor, a second layer laminated on the first layer and made of an Al-containing Group III nitride semiconductor with a composition that differs from that of the first layer, the nitride semiconductor laminated structure comprising a stripe-like trench exposing a lamination boundary between the first layer and the second layer; a gate electrode formed to oppose the lamination boundary; and a source electrode and a drain electrode, having the gate electrode interposed therebetween, each connected electrically to the second layer. | 2008-12-25 |
20080315257 | SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING THE SAME - In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p | 2008-12-25 |
20080315258 | CELL BASED INTEGRATED CIRCUIT AND UNIT CELL ARCHITECTURE THEREFOR - A unit cell for an integrated circuit includes a first conductive type active region and a second conductive type active region which extend in a first direction. Each of the active regions has first and second ends. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A poly-silicon pattern extends in the first direction across the first conductive type active region and second conductive type active region. A first contact region is adjacent the first end of the first conductive type active region in the first direction. A second contact region is adjacent the second end of the second conductive type active region in the first direction. | 2008-12-25 |
20080315259 | Semiconductor memory device - A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction. | 2008-12-25 |
20080315260 | Diode Structure - An open-base semiconductor diode device has an emitter, base, and collector layers. The layers are configured and doped such that the device has an IV characteristic with: i. a punchthrough region beginning at a voltage V | 2008-12-25 |
20080315261 | Dual conversion gain gate and capacitor combination - A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination. | 2008-12-25 |
20080315262 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object of the present invention to provide a solid-state imaging device that can achieve a high sensitivity, finer pixels for increasing the number of pixels, a high-speed operation, and high image quality, and a method for manufacturing the same. There are provided a plurality of photoelectric conversion portions arranged in a matrix on a substrate, a vertical transfer channel arranged between vertical columns of the photoelectric conversion portions, a plurality of vertical transfer electrodes for transferring a charge of the photoelectric conversion portions to the vertical transfer channel, a light-shielding film that is laminated on the vertical transfer electrodes via a first insulating film and has a plurality of window portions, each defining a light-receiving portion of each of the photoelectric conversion portions, and a shunt wiring that is arranged in a region overlapping the vertical transfer channel and is insulated from the light-shielding film by a second insulating film. A driving pulse according to a drive phase of each of the vertical transfer electrodes is supplied from the shunt wiring. | 2008-12-25 |
20080315263 | IMAGER PIXEL STRUCTURE AND CIRCUIT - An imager pixel and imaging device and system including an imager pixel for discharging a floating diffusion region are described. The imager pixel includes a photoconversion regions floating diffusion region, and a reset diode. A reset diode is coupled to the floating diffusion region and, when activated, discharges accumulated and collected charge from the photoconversion and the floating diffusion regions. Following successive accumulation, transfer and collection processes, the reset diode again discharges residual accumulated and collected charge from the photoconversion and the floating diffusion regions. | 2008-12-25 |
20080315264 | STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor. | 2008-12-25 |
20080315265 | Semiconductor Radiation Detector Optimized for Detecting Visible Light - A semiconductor radiation detector comprises a bulk layer of semiconductor material, and on a first surface of the bulk layer in the following order: a modified internal gate layer of semiconductor of second conductivity type, a barrier layer of semiconductor of first conductivity type and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create pixels corresponding to pixel dopings. The device comprises a first conductivity type first contact. Said pixel voltage is defined as a potential difference between the pixel doping and the first contact. The bulk layer is of the first conductivity type. On a second surface of the bulk layer opposite to the first surface, there is nonconductive back side layer that would transport secondary charges outside the active area of the device or function as the radiation entry window. | 2008-12-25 |
20080315266 | JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION - A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate. | 2008-12-25 |
20080315267 | Device Performance Improvement Using FlowFill as Material for Isolation Structures - A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body. | 2008-12-25 |
20080315268 | Methods and Apparatus for Semiconductor Memory Devices Manufacturable Using Bulk CMOS Process Manufacturing - The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices can be formed in a well on a substrate where isolation trenches surround one or more devices to create storage regions (floating wells) that is capable of holding a charge. Depending on the charge in the storage region (floating well), it can represent information. The semiconductor devices of the present invention can be manufactured using the standard process of manufacturing (bulk cmos processing). | 2008-12-25 |
20080315269 | PHOTODETECTOR ARRAY USING ISOLATION DIFFUSIONS AS CROSSTALK INHIBITORS BETWEEN ADJACENT PHOTODIODES - A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate. | 2008-12-25 |
20080315270 | MULTILAYER ANTIREFLECTION COATINGS, STRUCTURES AND DEVICES INCLUDING THE SAME AND METHODS OF MAKING THE SAME - Multi-layer antireflection coatings, devices including multi-layer antireflection coatings and methods of forming the same are disclosed. A block copolymer is applied to a substrate and self-assembled into parallel lamellae above a substrate. The block copolymer may optionally be allowed to self-assemble into a multitude of domains oriented either substantially parallel or substantially perpendicular to an widerlying substrate | 2008-12-25 |
20080315271 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - Disclosed are an image sensor and a method for fabricating the same. The method may include forming a gate, a photo diode, and a floating diffusion region on a pixel region of a semiconductor substrate; forming an oxide film on the pixel region and on an edge region of the semiconductor substrate; forming a sacrificial oxide layer by etching the oxide film using a photoresist pattern as a mask; forming a metal layer on the photoresist pattern, the gate, and the floating diffusion region; forming a salicide layer on the gate and the floating diffusion region; etching a remaining non-salicided portion of the metal layer, the photoresist pattern, and at least a portion of the sacrificial oxide layer; and forming an interlayer insulating film on the semiconductor substrate and planarizing the interlayer insulating film. | 2008-12-25 |
20080315272 | IMAGE SENSOR WITH GAIN CONTROL - An image sensor having a plurality of pixels; each pixel includes one or more photosensitive elements that collect charge in response to incident light; one or more transfer mechanisms that respectively transfer the charge from the one or more photosensitive elements; a charge-to-voltage conversion region having a capacitance, and the charge-to-voltage region receives the charge from the one or more photosensitive elements; a first reset transistor connected to the charge-to-voltage conversion region; a second reset transistor connected to the first reset transistor, which in combination with the first reset transistor, selectively sets the capacitance of the charge-to-voltage conversion regions from a plurality of capacitances. | 2008-12-25 |
20080315273 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor for minimizing a dark level defect is disclosed. The image sensor includes an isolation layer formed on a substrate. A field region and an active region are defined on the substrate by the isolation layer. A photodiode is formed in the image sensor in such a structure that a first region is formed below a surface of the substrate in the active region and a second region is formed under the first region. A first conductive type impurity is implanted into the first region and a second conductive type impurity is implanted into the second region. A dark current suppressor is formed on side and bottom surfaces of the isolation layer adjacent to the first region, and the dark current suppressor is doped with the second conductive type impurity. The dark current suppressor suppresses the dark current to minimize the dark level defect caused by the dark current. | 2008-12-25 |
20080315274 | DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME - A trench capacitor and method of forming a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an electrically conductive polysilicon inner plate filling regions of the trench not filled by the liner; an electrically conductive doped outer plate in the substrate surrounding the sidewalls and the bottom of the trench; a doped silicon region in the substrate; a first electrically conductive metal silicide layer on a surface region of the doped silicon region exposed at the top surface of the substrate; a second electrically conductive metal silicide layer on a surface region of the inner plate exposed at the top surface of the substrate; and an insulating ring on the top surface of the substrate between the first and second metal silicide layers. | 2008-12-25 |
20080315275 | Capacitor pair structure for increasing the match thereof - A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers. | 2008-12-25 |
20080315276 | Capacitor pair structure for increasing the match thereof - A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers. | 2008-12-25 |
20080315277 | SEMICONDUCTOR DEVICE - A semiconductor device | 2008-12-25 |
20080315278 | Insulated Gate Field Effect Transistors - The invention relates to FETs with stripe cells ( | 2008-12-25 |
20080315279 | NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 2008-12-25 |
20080315280 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL UNIT AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a silicon substrate including a first region which has a buried insulating layer below a single-crystal silicon layer and a second region which does not have the buried insulating layer below the single-crystal silicon layer, at least one memory cell transistor which has a first gate electrode, the first gate electrode being provided on the single-crystal silicon layer in the first region, and at least one selective gate transistor which has a second gate electrode and is provided on the single-crystal silicon layer in the first region. The one selective gate transistor is provided in such a manner that a part of the second gate electrode is placed on the single-crystal silicon layer in the second region. | 2008-12-25 |
20080315281 | Flash Memory Device and Method of Manufacturing the Same - Disclosed are a flash memory device and a method of manufacturing the same. In the method of manufacturing the flash memory device, gate patterns of a cell area and a logic area are formed by sequentially depositing and patterning a first polysilicon layer, an ONO layer and a second polysilicon layer without separately performing a photolithography process for one of the gate patterns. A mask process for removing a dummy gate pattern in the logic area is performed to form transistors in the cell area and the logic area, so that the manufacturing process is simplified. | 2008-12-25 |
20080315282 | Semiconductor Devices Including Transistors Having Three Dimensional Channels - Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein. | 2008-12-25 |
20080315283 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a plurality of element regions and a plurality of element isolation regions in a first direction, a plurality of floating gate electrodes formed via a gate insulating film on the respective element regions, an intergate insulating film formed on the floating gate electrodes, a plurality of control gate electrodes formed on the intergate insulating film so as to extend over the adjacent floating gate electrodes, and an element isolation insulating film formed in the element isolation region and having an upper end located higher than the upper surface of the gate insulating film, the element isolation insulating film including a part formed between the control gate electrodes so that the central sidewall of the element isolation insulating film is located lower than the end of the sidewall of the element isolation insulating film. | 2008-12-25 |
20080315284 | Flash memory structure and method of making the same - A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer. | 2008-12-25 |
20080315285 | Non-volatile memory devices and methods of fabricating the same - Non-volatile memory devices and methods of fabricating the same are provided. The non-volatile memory devices may include a semiconductor substrate having a pair of sidewall channel regions extending from the semiconductor substrate and opposite to each other, and a floating gate electrode between the pair of sidewall channel regions and protruding from the semiconductor substrate. A control gate electrode may be formed on the semiconductor substrate and a portion of the floating gate electrode. | 2008-12-25 |