51st week of 2011 patent applcation highlights part 63 |
Patent application number | Title | Published |
20110314201 | METHOD AND DEVICE FOR IDENTIFYING UNIVERSAL SERIAL BUS (USB) INSERTION OR CHARGER INSERTION OF MOBILE TERMINAL - The present invention discloses a method to identify whether a USB or a charger is plugged into a mobile terminal and an identification device thereof. The identification device comprises a USB interface module connected with an external power supply device, an interface detection and control module, an electronic switch module, a charging switch module, an identification module and a baseband USB data transceiving module. With the method to identify whether a USB or a charger is plugged into a mobile terminal and an identification device thereof provided by the present invention, when an external power supply is plugged in, the identification device makes the terminal to preferentially enter a USB mode, while, according to the ultimately detected D−signal state, interrupt responses can be flexibly generated to accurately determine the presence of a USB or a charger. It can quickly and accurately identify the type of USB or charger plugged into the terminal. The technology plays a particular important role for a 3G mobile phone terminal. | 2011-12-22 |
20110314202 | MANAGING CACHE DATA AND METADATA - Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. When a reboot of the computer is initiated, only a subset of the plurality of hierarchy levels may be loaded to memory, thereby expediting the process of restoring the cache metadata and thus startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot. Thereafter, as requests to read data items on the storage medium are processed using cache metadata to identify addresses at which the data items are stored in cache, the identified addresses may be stored in memory. When the computer is later shut down, instead of having to transfer the entirety of the cache metadata from memory to storage, only the subset of the plurality of hierarchy levels and/or the identified addresses previously loaded to memory may be transferred (e.g., to the cache device), thereby expediting the shutdown of the computer. | 2011-12-22 |
20110314203 | RESOURCE ADJUSTMENT METHODS AND SYSTEMS FOR VIRTUAL MACHINES - Resource adjustment methods and systems for virtual machines (VMs) for use in at least one physical device are provided. First, a first VM having a first resource set and a second VM having a second resource set are respectively enabled to enter a suspended state. A first user space address and a second user space address are respectively obtained from a first VM memory page table corresponding to the first VM and a second VM page table corresponding to the second VM, and a first physical memory address corresponding to the first user space address in the physical device and a second physical memory address corresponding to the second user space address in the physical device are obtained from a Hypervisor. The first user space address is mapped to the second physical memory address by the Hypervisor. Then, the first VM is enabled to enter an execution state, and the second VM is stopped. | 2011-12-22 |
20110314204 | SEMICONDUCTOR STORAGE DEVICE, CONTROL METHOD THEREOF, AND INFORMATION PROCESSING APPARATUS - According to the embodiments, a first storing unit as a cache, second and third storing units included in a nonvolatile semiconductor memories, and a controller are included, in which the controller includes an organizing unit that increases a resource by organizing data in the nonvolatile semiconductor memories, and an organizing-state notifying unit that, when an organizing-state notification request is input from a host, outputs an organizing state by the organizing unit to the host as an organizing-state notification, thereby improving a command response speed and the writing efficiency. | 2011-12-22 |
20110314205 | STORAGE SYSTEM - A storage system includes a first storage device, and a second storage device retrieving stored data at higher speeds than the first storage device. The storage system further includes a feature calculation unit calculating feature data based on a data content of storage target data, a data management unit storing the storage target data and managing a storing position thereof based on the feature data calculated from the storage target data, and a duplication determination unit determining whether or not the same storage target data as the storage target data to be newly stored is already stored in the first storage device. In a case that the same storage target data as the storage target data to be newly stored is already stored in the first storage device, the data management unit stores the storage target data already stored in the first storage device into the second device. | 2011-12-22 |
20110314206 | APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE - An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations. | 2011-12-22 |
20110314207 | MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND COMPUTING SYSTEM INCLUDING THE SAME - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 2011-12-22 |
20110314208 | CONTENT-AWARE DIGITAL MEDIA STORAGE DEVICE AND METHODS OF USING THE SAME - A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated. | 2011-12-22 |
20110314209 | DIGITAL SIGNAL PROCESSING ARCHITECTURE SUPPORTING EFFICIENT CODING OF MEMORY ACCESS INFORMATION - A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value. | 2011-12-22 |
20110314210 | LEVERAGING CHIP VARIABILITY - Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc. | 2011-12-22 |
20110314211 | RECOVER STORE DATA MERGING - Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory. | 2011-12-22 |
20110314212 | MANAGING IN-LINE STORE THROUGHPUT REDUCTION - Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred. | 2011-12-22 |
20110314213 | PROCESSOR SYSTEM USING SYNCHRONOUS DYNAMIC MEMORY - A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips. | 2011-12-22 |
20110314214 | Memory Sharing System and Memory Sharing Method - A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right. | 2011-12-22 |
20110314215 | MULTI-PRIORITY ENCODER - A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. | 2011-12-22 |
20110314216 | Method and Device for Reducing the Remanence of Data Stored on a Recording Medium - In a method of reducing the remanence of data stored in the memory space of a recording medium, in which at least a portion of the data stored in the memory space is moved in blocks according to a cycle repeated over time, the cycle includes choosing a number N of data blocks to be moved, and, as long as the number D of blocks moved during the cycle is less than N: a data block B | 2011-12-22 |
20110314217 | ESTIMATING THE SIZE OF AN IN-MEMORY CACHE - This Sampling Object Cache System (“SOCS”) estimates the size of an in-memory heap-based object cache without the need to serialize every object within the cache. SOCS samples objects at a user-determined rate and then computes a “sample size average” for each type of class—whether a top class, type of top class or non top class. Using these sample size averages, a statistically accurate measure of the overall size of the cache is calculated by adding together the total size of the objects in the cache for each class type. | 2011-12-22 |
20110314218 | PARITY-BASED RAID SYSTEM CONFIGURED TO PROTECT AGAINST DATA CORRUPTION CAUSED BY THE OCCURRENCE OF WRITE HOLES - A RAID system is provided in which the RAID controller of the system causes a predetermined number, N, of IO commands to be queued in a memory element, where N is a positive integer. After the N IO commands have been queued, the RAID controller writes N locks associated with the N IO commands in parallel to a service memory device. The RAID controller then writes N stripes of data and parity bits associated with the N IO commands to the PDs of the system to perform striping and parity distribution. If a catastrophic event, such as a power failure, occurs, the RAID controller reads the locks from the service memory device and causes parity to be reconstructed for the stripes associated with the locks. These features improve write performance while preventing the occurrence of data corruption caused by write holes. | 2011-12-22 |
20110314219 | SYSTEMS ANDMETHOD FOR STORING PARITY GROUPS - A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency. | 2011-12-22 |
20110314220 | STORAGE CONTROL APPARATUS, STORAGE SYSTEM AND METHOD - A storage control apparatus includes a controller configured to control to convert an access to logical volume into an access to associated RAID group in response to an access to the corresponding virtual volume on the basis of access conversion information, monitor frequency of access to each of logical volumes, select a logical volume on the basis of the monitored frequency of access, move data stored in a RAID group corresponding to the selected logical volume to a different RAID group corresponding to a logical volume to be a data shift destination, and update the access conversion information to convert access to the RAID group corresponding to the selected logical volume into access to the different RAID group. | 2011-12-22 |
20110314221 | STORAGE APPARATUS, CONTROLLER AND STORAGE APPARATUS CONTROL METHOD - An apparatus including: a first storage for storing first data; second storages for storing the first data; a storage controller for storing the first data stored in the first storage into the second storage; a third storage for saving data including second data; a saving device for reading the data and saving the data in the third storage; a data set output device for outputting the data to a copy destination device; a restoration device for storing the data saved in the third storage into available ones of the second storages; and a suspending device for causing the data set output device to output all of the data stored in the second storage to the copy destination device and then suspending the output of the data by the data set output device to the copy destination device to place the data set output device in a suspend state. | 2011-12-22 |
20110314222 | Clustered Storage Network - A data storage network is provided. The network includes a client connected to the data storage network; a plurality nodes on the data storage network, wherein each data node has two or more RAID controllers, wherein a first RAID controller of a first node is configured to receive a data storage request from the client and to generate RAID parity data on a data set received from the client, and to store all of the generated RAID parity data on a single node of the plurality of nodes. | 2011-12-22 |
20110314223 | SYSTEM FOR PROTECTING AGAINST CACHE RESTRICTION VIOLATIONS IN A MEMORY - An apparatus comprising a plurality of tag circuits, a plurality of compare circuits and a processing circuit. The plurality of tag circuits may each be configured to store memory mapping data. The plurality of compare circuits may each be configured to generate a respective compare result in response to a match between the memory mapping data of a respective one of the tag circuits and a respective one of a plurality of tag fields. The processing circuit may be configured to receive each of the compare results from the plurality of compare circuits. The processing circuit may also be configured to count occurrences of the matches. If more than one match is identified within a predetermined time, the processing circuit may invalidate the memory mapping data and the tag field. If more than one match is identified within a predetermined time, the processing circuit may also re-fetch the memory mapping data. | 2011-12-22 |
20110314224 | Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus - An apparatus and method are provided for handling access operations issued to local cache structures within a data processing apparatus. The data processing apparatus comprises a plurality of processing units each having a local cache structure associated therewith. Shared access coordination circuitry is also provided for coordinating the handling of shared access operations issued to any of the local cache structures. For a shared access operation, the access control circuitry associated with the local cache structure to which that shared access operation is issued will perform a local access operation to that local cache structure, and in addition will issue a shared access signal to the shared access coordination circuitry. For a local access operation, the access control circuitry would normally perform a local access operation on the associated local cache structure, and not notify the shared access coordination circuitry. However, if an access operation extension value is set, then the access control circuitry treats such a local access operation as a shared access operation. Such an approach ensures correction operation even after an operating system and/or an application program are migrated from one processing unit to another. | 2011-12-22 |
20110314225 | COMPUTATIONAL RESOURCE ASSIGNMENT DEVICE, COMPUTATIONAL RESOURCE ASSIGNMENT METHOD AND COMPUTATIONAL RESOURCE ASSIGNMENT PROGRAM - In a multi-core processor system, cache memories are provided respectively for a plurality of processors. An assignment management unit manages assignment of tasks to the processors. A cache status calculation unit calculates a cache usage status such as a memory access count and a cache hit ratio, with respect to each task. A first processor handles a plurality of first tasks that belong to a first process. If computation amount of the first process exceeds a predetermined threshold value, the assignment management unit refers to the cache usage status to preferentially select, as a migration target task, one of the plurality of first tasks whose memory access count is smaller or whose cache hit ratio is higher. Then, the assignment management unit newly assigns the migration target task to a second processor handling another process different from the first processor. | 2011-12-22 |
20110314226 | SEMICONDUCTOR STORAGE DEVICE BASED CACHE MANAGER - In general, the present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to SSD based cache manager. In a typical embodiment, a cache balancer is coupled to a set of cache meta data units. A set of cache algorithms that utilizes the set of cache meta data units to determine optimal data caching operations. A cache adaptation manger is coupled to and sends volume information to the cache balancer. Typically, this information is computed using the set of cache algorithms. A monitoring manager is coupled to the cache adaptation. | 2011-12-22 |
20110314227 | Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer - Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes. | 2011-12-22 |
20110314228 | Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer - Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes. | 2011-12-22 |
20110314229 | Error Detection for Files - Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily. | 2011-12-22 |
20110314230 | ACTION FRAMEWORK IN SOFTWARE TRANSACTIONAL MEMORY - A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems. | 2011-12-22 |
20110314231 | BANDWIDTH ADAPTIVE MEMORY COMPRESSION - Data is retrieved from system memory in compressed mode if a determination is made that the memory bus is bandwidth limited and in uncompressed mode if the memory bus is not bandwidth limited. Determination of the existence of the bandwidth limited condition may be based on memory bus utilization or according to a depth of a queue of memory access requests. | 2011-12-22 |
20110314232 | ELECTRONIC DATA STORE - A method of, and apparatus for, predicting the performance of a data storage resource forming part of a networked electronic data store. The method includes representing the data storage resource as a plurality of separate virtual storage components, each virtual storage component representing a part of the data storage resource and having at least one operational state selectable from a pool of operational states. The method further includes obtaining resource profile data from the data storage resource, and modelling the performance of the data storage resource by assigning, from the pool, an operational state to each virtual storage component to fit the resource profile data. By providing such a method, the data storage resource can be represented as a collection of virtual storage components, each having a dynamically-assignable operational state. This enables the modelling of the performance of the data storage resource to be simplified significantly because each virtual storage component can only have a finite number of operational states, simplifying the modelling of access patterns on, and interactions between, the virtual storage components. | 2011-12-22 |
20110314233 | MULTI-CORE QUERY PROCESSING USING ASYNCHRONOUS BUFFERS - A system may include a buffer monitor configured to monitor buffer content of a buffer being used during processing of a query workflow in which write tasks of the query workflow write data to the buffer and read tasks of the query workflow read data from the buffer, the buffer having a buffer capacity. The system may include a threshold manager configured to compare the buffer content to a low threshold and to a high threshold that are defined relative to the buffer capacity, and a speed controller configured to control a number of the write tasks relative to a number of the read tasks that are currently executing the query workflow, to thereby maintain the buffer content between the low threshold and the high threshold. | 2011-12-22 |
20110314234 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE - An MCP type semiconductor memory device having a defective cell remedy function, which enables easy design and manufacture while minimizing chip area increase, is provided. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information. | 2011-12-22 |
20110314235 | DATA STORAGE DEVICE AND WRITE METHOD THEREOF - A data storage device that includes a storage media, and a controller to compress raw data to be stored in the storage media, wherein the controller can add header and/or footer information to the compressed data. The controller of the data storage device can further change stored, compressed data by retrieving all or only some of the compressed stored data, uncompressing it, adding or changing the now uncompressed data, and then re-compressing it before adding either or both of header and footer to the compressed data. The storage media can be solid state devices, and can be used with a controller in a computer or a server, that can be part of any one or a multitude of types of networks, including, for example, an internet. | 2011-12-22 |
20110314236 | Control apparatus, control method, and storage system - In a control apparatus, a write control unit controls operation of writing data to a non-volatile storage unit. The write control unit is configurable with given control data. A control data storage unit stores first control data for the write control unit. An input reception unit receives second control data for the write control unit. A configuration unit configures the write control unit with the first control data stored in the control data storage unit when the first control data has a newer version number than that of the second control data received by the input reception unit, and with the second control data when the second control data has a newer version number than that of the first control data. | 2011-12-22 |
20110314237 | VIRTUAL ORDERED WRITES TRANSFER LOG - A primary storage device maintaining recovery data in connection with ordering data writes includes the primary storage device receiving a plurality of data writes, the primary storage device associating data writes begun after a first time and before a second time with a first chunk of data, and the primary storage device associating data writes begun after the second time with a second chunk of data different from the first chunk of data. After completion of all writes associated with the first chunk of data, the primary storage device initiates transfer of writes associated with the first chunk of data to a secondary storage device. The primary storage device maintains a transfer log of data from the first chunk that is successfully transferred to the secondary storage device. | 2011-12-22 |
20110314238 | COMMON MEMORY PROGRAMMING - A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task. | 2011-12-22 |
20110314239 | COMPUTER SYSTEM AND SYSTEM CONTROL METHOD - Operation of an environment that supports both host-based replication and array-based replication is realized. According to the present invention, data in the first storage area is copied first to the second storage area using an array-based replication engine. In this case, the execution result of the replication is managed using a flag from which the copy timing can be known. In addition, data in the first storage area is copied to the third storage area using a host-based replication engine, and further, data in the third storage area is copied to the fourth storage area. Then, when data in the second storage area is restored to the first storage area, data in the fourth storage area is returned to the third storage area so that the third storage area has data of the same time as the second storage area (see FIG. | 2011-12-22 |
20110314240 | Virtualization system and area allocation control method - A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation. | 2011-12-22 |
20110314241 | INFORMATION PROCESSING APPARATUS INCLUDING STORAGE UNIT AND CONNECTION UNIT FOR CONNECTING EXTERNAL STORAGE DEVICE - A main controller of an image forming apparatus allows a user to select whether to perform backup of an internal storage device to an external storage device when detecting that the external storage device is connected to a USB I/F. If the user selects to perform backup, the main controller denies access to the external storage device from processing other than the backup processing at least during the backup processing, and if the user selects not to perform backup, the main controller permits access to the external storage device from processing other than the backup processing. | 2011-12-22 |
20110314242 | COMPUTER SYSTEM FOR HIERARCHICALLY MANAGING A JOURNAL AND METHOD THEREFOR - A computer system having a first storage system which includes a first logical volume and a second logical volume, wherein the second logical volume stores a first differential data item representing a differential between data that was stored in the first logical volume at a first time instant and data that was stored in the first logical volume at a second time instant being later than the first time instant, and a second storage system which includes a third logical volume. The first storage system transmits the first differential data item to the second storage system, the second storage system stores the first differential data item into the third logical volume, the first storage system deletes the first differential data item from the second logical volume, and the computer system retains management information set for associating the first logical volume with the third logical volume storing therein the first differential data item. | 2011-12-22 |
20110314243 | METHOD AND APPARATUS FOR RESTRICTING ACCESS TO WRITABLE PROPERTIES AT RUNTIME - A processing device executing an application receives a user command to update a specified writeable property of the application. The processing device determines whether the specified writeable property has metadata that distinguishes the specified writeable property as a user updateable property. In one embodiment, this is determined by using a reflection mechanism to examine metadata of the specified writeable property. In another embodiment, this is determined by examining a dynamic changeable properties list that was created and populated at runtime of the application. If the specified writeable property has the metadata that distinguishes the specified writeable property as a user updateable property, the processing device updates the specified writeable property in accordance with the user command. | 2011-12-22 |
20110314244 | COMPOSITION OF LOCKS IN SOFTWARE TRANSACTIONAL MEMORY - A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection. | 2011-12-22 |
20110314245 | SECURE MEDIA SYSTEM - In one embodiment a network attached storage device comprises at least one storage media, a detection module to detect a connection of a media source to the network attached storage device, a network interface to receive, in the network attached storage device, an activation key associated with the media source, an activation module to determine whether the activation key is stored in a computer-readable memory coupled to the network attached storage device, and in response to a determination that the activation key is not stored in a computer-readable memory coupled to the network attached storage device, to associate the activation key with a device identifier for the network attached storage device and to store the activation key and the device identifier in the computer-readable memory coupled to the network attached storage device, an imaging module to create an image of at least a portion of the media content on the media source in a computer-readable memory coupled to the network attached storage device, and a security module binding the image of the media content to the network attached storage device. | 2011-12-22 |
20110314246 | HIERARCHICAL ALLOCATION FOR FILE SYSTEM STORAGE DEVICE - Aspects of the subject matter described herein relate to storage allocation. In aspects, a hierarchical data structure is used to track allocation data for storage managed by a file system. The hierarchical data structure may have multiple levels with each level having data regarding a different granularity of storage. Portions of the hierarchical data structure may be locked independently of other portions of the hierarchical data structure. The hierarchical data structure may indicate that one or more portions of storage are for exclusive use by a directory. Extra space may be reserved in allocated space in anticipation of subsequent operations. Allocation requestors may obtain storage allocation from regions associated with different levels of the hierarchical data structure. | 2011-12-22 |
20110314247 | BROADCAST RECEIVING APPARATUS AND MEMORY MANAGING METHOD THEREOF - A broadcast receiving apparatus and memory managing method thereof are provided. The broadcast receiving apparatus includes a storage unit which includes a plurality of memory areas for each of a plurality of operating systems, a determination unit which periodically determines a retrievable memory area for each of the plurality of memory areas, and a controller which reallocates at least part of the retrievable memory area, if memory area reallocation is necessary. | 2011-12-22 |
20110314248 | STORING AND RETRIEVING BLOCKS OF DATA HAVING DIFFERENT DIMENSIONS IN/FROM BLOCK STORABE DEVICES - A method for storing and retrieving blocks of data having different dimensions is disclosed. The method can include receiving a first data segment to be stored in a block storage device where the first data segment has an address. The method can also include determining if the first data segment conforms to a standard dimension and sorting the first data segment according to the destination address if it does not have a standard dimension. The method can further include placing a non-standard data segment into a unfilled block allocation and placing a second non-standard data segment into the unfilled block allocation when the second data segment has the destination identifier. Other embodiments are also disclosed. | 2011-12-22 |
20110314249 | METHOD OF SELECTION OF AN AVAILABLE MEMORY SIZE OF A CIRCUIT INCLUDING AT LEAST PROCESSOR AND A MEMORY AND CORRESPONDING PROGRAM AND SMART CARD - The invention relates to a method for selecting an available memory size of a circuit including at least a CPU and a total memory, the method including a stage for the selection of an available memory size that is smaller than or equal to that of the total memory. | 2011-12-22 |
20110314250 | STORAGE SYSTEM AND OPERATION METHOD OF STORAGE SYSTEM - The present invention is able to improve the processing performance of a storage system by respectively virtualizing the external volumes and enabling the shared use of such external volumes by a plurality of available virtualization storage devices. By virtualizing and incorporating the external volume of an external storage device, a first virtualization storage device is able to provide the volume to a host as though it is an internal volume. When the load of the first virtualization storage device increases, a second virtualization storage device | 2011-12-22 |
20110314251 | MEMORY SAFETY OF FLOATING-POINT COMPUTATIONS - Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any floating-point computations exist in the code, and if so, if the floating-point computations are memory safe. The analysis can include identifying floating-point instructions and conditional statements in the code. The code can be symbolically executed, and behavior of the floating-point instructions and the conditional statements can be monitored to determine if a floating point calculation is ever involved in computation of any memory address during the execution of the code. | 2011-12-22 |
20110314252 | REDUCED HARDWARE MULTIPLIER - The invention is directed to a multiplication apparatus or arrangement comprising: an address unit being adapted to receive address words from an external system, which address words have a first part comprising a first number X and a second part comprising a second number Y; a memory area comprising M×M memory cells arranged to be addressed by said address words, wherein a cell addressed by a particular address word is provided with the product P of the first and second number X and Y; and an output unit arranged to provide products P from the memory area to an external system. The invention is characterized in that the cells in the memory area addressed by address words wherein Y2011-12-22 | |
20110314253 | SYSTEM, DATA STRUCTURE, AND METHOD FOR TRANSPOSING MULTI-DIMENSIONAL DATA TO SWITCH BETWEEN VERTICAL AND HORIZONTAL FILTERS - A system, processor, and method for filtering multi-dimensional data, for example, image data. A processor may receive an instruction to execute a horizontal filter by combining multi-dimensional data values horizontally aligned in a single row of a first data structure. A second data structure may include a plurality of individually addressable internal memory units. A load unit may load the horizontally aligned values in a transposed orientation for storage as vertically aligned values in a single column in the second data structure in the individually addressable memory units. Each transposed value in the single column may be separately stored in a different respective one of the individually addressable memory units. The processor may independently manipulate and combine each transposed value designated for combination by the horizontal filter by individually accessing the separate memory units. | 2011-12-22 |
20110314254 | METHOD FOR VECTOR PROCESSING - The present application relates to a method for processing data in a vector processor. The present application relates also to a vector processor for performing said method and a cellular communication device comprising said vector processor. The method for processing data in a vector processor comprises executing segmented operations on a segment of a vector for generating results, collecting the results of the segmented operations, and delivering the results in a result vector in such a way that subsequent operations remain processing in vector mode. | 2011-12-22 |
20110314255 | MESSAGE BROADCAST WITH ROUTER BYPASSING - A processor and method for broadcasting data among a plurality of processing cores is disclosed. The processor includes a plurality of processing cores connected by point-to-point connections. A first of the processing cores includes a router that includes at least an allocation unit and an output port. The allocation unit is configured to determine that respective input buffers on at least two others of the processing cores are available to receive given data. The output port is usable by the router to send the given data across one of the point-to-point connections. The router is configured to send the given data contingent on determining that the respective input buffers are available. Furthermore, the processor is configured to deliver the data to the at least two other processing cores in response to the first processing core sending the data once across the point-to-point connection. | 2011-12-22 |
20110314256 | Data Parallel Programming Model - Described herein are techniques for enabling a programmer to express a call for a data parallel call-site function in a way that is accessible and usable to the typical programmer. With some of the described techniques, an executable program is generated based upon expressions of those data parallel tasks. During execution of the executable program, data is exchanged between non-data parallel (non-DP) capable hardware and DP capable hardware for the invocation of data parallel functions. | 2011-12-22 |
20110314257 | DISTRIBUTED MICRO INSTRUCTIONS SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING - A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank. | 2011-12-22 |
20110314258 | METHOD AND APPARATUS FOR OPERATING A PROGRAMMABLE LOGIC CONTROLLER (PLC) WITH DECENTRALIZED, AUTONOMOUS SEQUENCE CONTROL - A method for operating a programmable logic controller (PLC), and a programmable logic controller (PLC) for a processing plant with a central data processing unit and a sequence control that reads in, processes input data from inputs, and outputs the processed output data to outputs. The data processing unit performs only superordinate administrative functions for the administration of downstream input and output modules and is embodied as an ADMIN data processing unit. The sequence control is embodied as a partial application autonomously executing in the input and output modules. | 2011-12-22 |
20110314259 | OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM - A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location. | 2011-12-22 |
20110314260 | HIGH-WORD FACILITY FOR EXTENDING THE NUMBER OF GENERAL PURPOSE REGISTERS AVAILABLE TO INSTRUCTIONS - A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed. | 2011-12-22 |
20110314261 | Prefetch of Attributes in Evaluating Access Control Requests - In an embodiment, a method is provided for prefetching attributes used in access control evaluation. In this method, an access control policy that comprises rules is retrieved. These rules further comprise parameters. At least one of the rules is categorized into a class from multiple classes based on at least one of the parameters. Here, the class is a grouping based on at least one of these parameters. An attribute associated with the at least one of these parameters is identified and this attribute is mapped to the class. | 2011-12-22 |
20110314262 | PREFETCH REQUEST CIRCUIT - A prefetch request circuit is provided in a processor device. The processor device has hierarchized storage areas and can prefetch data of address to be used between appropriate storage areas among the storage areas, when executing respective instruction flows obtained by multi-flow expansion for one instruction at a time of decoding of the instruction. The prefetch request circuit includes a latch unit to hold, when a state in which the respective instruction flows to access the storage area are executed with a maximum specifiable data transfer volume is specified, the state during a time period of the multi-flow expansion; and a prefetch request signal output unit to output a prefetch request signal to request the prefetch every time when the instruction flow is executed, based on an output signal of the latch unit and a signal indicating an execution timing of the respective instruction flows. | 2011-12-22 |
20110314263 | INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND - An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result in the memory location of the second operand, and subsequently stores the temporary copy in a first register. | 2011-12-22 |
20110314264 | Key allocation when tracing data processing systems - A trace unit is provided which is configured to generate items of trace data indicative of processing activities, of a data processing unit. The trace unit comprises a trace indexing unit configured to associate an index value with at least a subset of the items of trace data generated by the trace unit. The trace indexing unit is configured to generate each index value as one of a predetermined sequence of index values, wherein an n+1 | 2011-12-22 |
20110314265 | PROCESSORS OPERABLE TO ALLOW FLEXIBLE INSTRUCTION ALIGNMENT - Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned. | 2011-12-22 |
20110314266 | ON-DEMAND DATABASE SERVER STARTUP AND SHUTDOWN - A database startup service is launched at the boot time of a computer that is configured to receive requests to start the execution of a database server. A business application plug-in is then started in a minimal functionality mode of operation. The plug-in determines whether an action has been performed that requires access to a database. If access to the database is needed, the plug-in transmits a request to the database startup service to start the database service. Once the database server has been started, the plug-in transitions to a full functionality mode of operation where all of the functionality provided by the plug-in is enabled. The plug-in might also determine that access to the database is no longer needed. In response thereto, the plug-in may transmit a request to the database startup service to terminate the execution of the database server. | 2011-12-22 |
20110314267 | ELECTRONIC DEVICE AND COMPUTER PROGRAM PRODUCT - According to one embodiment, an electronic device includes a display module, a power button, at least one function button, a hardware controller, and a pre-OS boot processor. The display module displays display data processed by an application on an operating system (OS) or display data based on received broadcast waves. The power button is operated to power on or off the electronic device. The function button is provided separately from a hardware keyboard having a plurality of keys to control a function defined on the OS. The hardware controller is activated in response to power-on operation made on the power button and provide the OS with basic input/output mechanism with respect to hardware including the function button. The pre-OS boot processor performs a process before boot-up of the OS if a predetermined operation is made on the function button within a predetermined time since the power-on operation is made. | 2011-12-22 |
20110314268 | SD SWITCH BOX IN A CELLULAR HANDSET - A cellular handset, including a cellular base band modem, including a UART interface, and an SD host interface, a NAND flash memory, a NAND controller coupled with the NAND flash memory, a host device including a host controller, wherein the electronic host device supports an SD connection, and a convergence controller coupled with the cellular base band modem, the host device and the NAND controller, including a UART port for transferring data to and from the cellular base band modem via the UART interface, an SD port for transferring data to and from the cellular base band modem via the SD host interface, an SD port for transferring data to and from the NAND flash memory via the NAND controller, an SD port for transferring data to and from the host device via the host controller, a first mailbox into which the base band modem writes messages and from which the host device reads messages, and a second mailbox into which the host device writes messages and from which the cellular base band modem reads messages. A method is also described and claimed. | 2011-12-22 |
20110314269 | Website Detection - A website fingerprint is generated that characterizes network traffic associated with a website as a website traffic fingerprint that includes size description(s), order description(s), and timing description(s) of packet traffic for the website. A website monitor generates website trace(s) of packet statistics. A correlation processor correlates a sequence of packet statistics from the website trace(s) with the size description, the order description, and timing description found in the website traffic fingerprint(s). | 2011-12-22 |
20110314270 | ENCRYPTED NETWORK TRAFFIC INTERCEPTION AND INSPECTION - A method of operating a computing device that allows inspecting data that the device attempts to transmit over a network in an encrypted form for presence of malware, viruses or confidential information. The method includes intercepting a request from an application to an encryption component of an operating system to encrypt the data and acquiring encrypted data generated by the encryption component in response to the request. SSL or TLS protocol may be used for encryption. The request may be intercepted using API hooking. The data in an unencrypted form and an identifier of the encrypted data may be provided to a data inspection facility for establishing a correspondence between the unencrypted and encrypted data, using the identifier. The data inspection facility performs inspection of the unencrypted data to determine whether to allow transmission of the encrypted data over the network. | 2011-12-22 |
20110314271 | Secure Processing Systems and Methods - This disclosure relates to systems and methods for enabling the use of secret digital or electronic information without exposing the sensitive information to unsecured applications. In certain embodiments, the methods may include invoking, by a client application executing in an open processing domain, a secure abstraction layer configured to interface with secret data protected by a secure processing domain. Secure operations may be securely performed on the secret data by the secure abstraction layer in the secure processing domain based on an invocation from a client application running in the open processing domain. | 2011-12-22 |
20110314272 | SECURE TRANSFER OF BUSINESS DATA TO A HOSTED SYSTEM - A system and method for uploading data from a customer system to a hosted system is disclosed. A stub is integrated with a firewall between the customer system and the hosted system. The stub includes an inbound layer on the customer system side of the firewall and an outbound layer on the hosted system side of the firewall, and the inbound layer includes a write-only directory. A demon is connected between the inbound layer and the outbound layer of the stub. The demon is configured to recognize newly received data in the write-only directory of the inbound layer, encrypt the newly received data to generate encrypted data, and move the encrypted data to the outbound layer for access by the hosted system. | 2011-12-22 |
20110314273 | DATA GRADING TRANSMISSION METHOD - A data grading transmission method includes steps of enabling a transmitting terminal to grade data according to a preset data security rule and to mark the data with labels; designating transmission routes of the data according to levels of the graded data; and enabling the data to be transmitted from the transmitting terminal to the receiving terminal through the designated transmission routes, and cascading the data having the same label according to the labels of the data. Thereby, grading data according to privacy and designating transmission routes of data reduce network establishment cost and effectively regulate data transmission rate through the data grading transmission method. | 2011-12-22 |
20110314274 | METHOD AND APPARATUS FOR SECURITY ENCAPSULATING IP DATAGRAMS - A method and corresponding apparatus are provided to security encapsulate an original IP datagram received from a network. It is first determined whether an IP payload of the original IP datagram is a TCP segment, UDP datagram or packet of another type of network protocol. Based on this determination, a portion of the IP payload is encrypted resulting in an encrypted payload. A security encapsulated IP packet is then formed with source IP address, destination IP address, and IP protocol field from the original IP datagram, and the encrypted payload. The security encapsulated IP packet is then provided to the network. | 2011-12-22 |
20110314275 | MANAGING ENCRYPTION KEYS - Methods, apparatus, and articles of manufacture to manage encryption keys are disclosed. An example method to manage encryption keys includes obtaining data including a private key, determining that the data cannot be read according to a first format by attempting to read the data in the first format, in response to determining that the data cannot be read according to the first format, accessing the private key by reading the data according to a second format different from the first format, and converting the data from the second format to a third format. | 2011-12-22 |
20110314276 | Communication verification system - A communication system verifying the source of a file. The system uses a first link between a sending computer and an authorizing computer which contains a request for a PIN associated with the intended receiving computer. This PIN is returned to the first computer via a second link which permits the sending computer to properly communicate in an encrypted manner with the receiving computer. An alert or notice is sent to the receiving computer by the authorizing computer to further verify the authenticity of the file being sent to the receiving computer from the sending computer. | 2011-12-22 |
20110314277 | ELECTRONIC AUTHORIZATION SYSTEM AND METHOD - An electronic authorization system comprising a data source system configured to transmit transaction data. A secure data system is coupled to the data source system over an open network, the secure data system is configured to receive the transaction data from the data source system, generate a unique encrypted identifier for the transaction data and to transmit the unique encrypted identifier to the data source system. The data source system is configured to receive the unique encrypted identifier and replace payment card data associated with the transaction data in a database with the unique encrypted identifier. | 2011-12-22 |
20110314278 | ON-THE-FLY DATA MASKING - Described are methods, systems, and apparatus, including computer program products for securing data of a production server. The invention, in one implementation, includes reading a data value on the production server, obfuscating the data value in the memory of the server to create a masked value, transmitting the masked value to a non-production server, and storing the masked value on the non-production server. | 2011-12-22 |
20110314279 | Single-Use Authentication Methods for Accessing Encrypted Data - Single-use authentication methods for accessing encrypted data stored on a protected volume of a computer are described, wherein access to the encrypted data involves decrypting a key protector stored on the computer that holds a volume-specific cryptographic key needed to decrypt the protected volume. Such single-use authentication methods rely on the provision of a key protector that can only be used once and/or that requires a new access credential for each use. In certain embodiments, a challenge-response process is also used as part of the authentication method to tie the issuance of a key protector and/or access credential to particular pieces of information that can uniquely identify a user. | 2011-12-22 |
20110314280 | HEALTH CARE SYSTEM - A measurement device ( | 2011-12-22 |
20110314281 | METHOD AND SYSTEM FOR SECURING COMMUNICATION - A method for securing communication among members of a group. The method includes a first member obtaining a first secret. An n-bit generator executing on the first member generates a first message digest using the first secret. The first member extracts a first encryption solution and a second encryption solution, at least in part, from the first message digest, encrypts a first communication using the first encryption solution to obtain a first encrypted communication, and sends, to a second member of the group, the first encrypted communication. The first member further receives, from the second member, a second encrypted communication, and decrypts the second encrypted communication using the second encryption solution to obtain a second communication. | 2011-12-22 |
20110314282 | CONTENT TRANSMISSION APPARATUS, CONTENT RECEPTION APPARATUS AND CONTENT TRANSMISSION METHOD - A content transmission apparatus including: an authenticator configured (i) to perform authentication, (ii) to share an authentication key, (iii) to request transmission range acknowledgement and authentication information, (iv) to receive a response, and (v) to share an exchange key; an encryptor to encrypt based on the exchange key; and a timer measuring a time interval between transmission of said request for transmission range acknowledgement and reception of a response; wherein, said authenticator measures said time interval using said timer, and if a time measurement value exceeds a predetermined value, said authenticator does not share said exchange key; and wherein, said response of said request for transmission range acknowledgement includes a data generated based on said authentication information and said authentication key, and if said data is incorrect, said authenticator does not share said exchange key. | 2011-12-22 |
20110314283 | E-MAIL CERTIFICATION SERVICE - A method is provided to handle an electronic mail message such that the receiver of the e-mail message can verify the integrity of the message. A request is provided from a sender's side to a service. The request includes information regarding the e-mail message. The service processes at least a portion of the request to generate a result. For example, the service may encrypt the portion of the request, according to a public/private key encryption scheme, to generate a digital signature as the result. The service provides the result to the sender's side. At the sender's side, the result is incorporated into the e-mail message and the result-incorporated message is transmitted via an e-mail system. At the receiver's side, the result-incorporated e-mail message is processed to assess the integrity of the received e-mail message. | 2011-12-22 |
20110314284 | METHOD FOR SECURING TRANSMISSION DATA AND SECURITY SYSTEM FOR IMPLEMENTING THE SAME - A method for securing transmission data is to be implemented by a security system including first and second security modules. The first security module provides a first public key to the second security module. The second security module encrypts a second public key and second verification data associated therewith using the first public key, and provides the encrypted second public key and the encrypted second verification data to the first security module. The first security module decrypts the encrypted second public key using a first private key, encrypts first verification data associated therewith using the second public key, and provides the encrypted first verification data to the second security module. The first and second security modules verify each other using the encrypted second and first verification data, respectively. The security system allows data transmission through the first and second security modules when verification is successfully completed. | 2011-12-22 |
20110314285 | REGISTRATION METHOD OF BIOLOGIC INFORMATION, APPLICATION METHOD OF USING TEMPLATE AND AUTHENTICATION METHOD IN BIOMETRIC AUTHENTICATION - When a registration station appends an anonymous ID (AID), a linking validity of the anonymous ID and actual user ID (UID) is assured for an application businessperson in the case of applying to use a biometric authentication. Specifically, a biometric authentication service system includes a biometric authentication server, an application server, a registration station server and a client server, for holding a hash value alone of personal information (P) in the registration station server, supplying again the personal information on applying to use a template (T) for the application server, collating the hash with the previously held hash, and verifying that the user applying to use the template is identical with the user registered the biologic information in the registration station server, in addition, secret information (S) different for every user is added to the personal information to generate unique data and identify the user correctly. | 2011-12-22 |
20110314286 | ACCESS AUTHENTICATION METHOD APPLYING TO IBSS NETWORK - An access authentication method applying to IBSS network involves the following steps of: 1) performing authentication role configuration for network entities; 2) authenticating an authentication entity and a request entity that have been performed the authentication role configuration via an authentication protocol; and 3) after finishing the authentication, the authentication entity and the request entity perform the key negotiation, wherein, the message integrity check field and protocol synchronization lock-in field are added in a key negotiation message. The access authentication method applying to IBSS network provided by the invention has the advantages of the better safeness and the higher execution efficiency. | 2011-12-22 |
20110314287 | Method and apparatus for binding subscriber authentication and device authentication in communication systems - An authentication method is provided between a device (e.g., a client device or access terminal) and a network entity. A removable storage device may be coupled to the device and stores a subscriber-specific key that may be used for subscriber authentication. A secure storage device may be coupled to the device and stores a device-specific key used for device authentication. Subscriber authentication may be performed between the device and a network entity. Device authentication may also be performed of the device with the network entity. A security key may then be generated that binds the subscriber authentication and the device authentication. The security key may be used to secure communications between the device and a serving network. | 2011-12-22 |
20110314288 | CIRCUIT, SYSTEM, DEVICE AND METHOD OF AUTHENTICATING A COMMUNICATION SESSION AND ENCRYPTING DATA THEREOF - Disclosed is a circuit, system, device and method for authentication and/or encryption, which is based on the characteristics and/or management of One Time Programming (OTP) Non Volatile Memory (NVM) that may prevent the ability to alter, modify, mimic or otherwise use an identification string/code for attaining false authentication and/or falsely decrypting encrypted data. | 2011-12-22 |
20110314289 | REMOTE VERIFICATION OF ATTRIBUTES IN A COMMUNICATION NETWORK - It is provided an apparatus, comprising property checking means configured to check whether a claimant property information received from a claimant device corresponds to a predefined claimant attribute; obtaining means configured to obtain a result, which is positive only if the claimant property information corresponds to the predefined claimant attribute as checked by the property checking means; key generation means configured to generate a first claimant intermediate key from a predefined claimant permanent key stored in the apparatus; supplying means configured to supply, to the claimant device, the first claimant intermediate key using a secured protocol, wherein at least one of the key generation means and the supplying means is configured to generate and to supply, respectively, the first claimant intermediate key only if the result is positive. | 2011-12-22 |
20110314290 | DIGIPASS FOR WEB-FUNCTIONAL DESCRIPTION - The DigiPass for the Web provides security for internet communication greater than that achieved by the use of a static password without requiring the user to install any software or to possess or use dedicated hardware of any kind. The user merely access an appropriate website which downloads an applet to the user's browser. This is a conventional function which is handled by the browser and does not require any expertise on the part of the user. The browser relies on a password known only to the user for authenticating the user to the browser/applet. The browser/applet interacts with the server to create an authentication key which is then stored on the user's computer. The user can invoke the authentication key dependent on the user's presentation to the browser/applet of the password. Since the password is not used outside the user-browser/applet interaction it is not subject to attacks by hackers. The authentication key is also protected from attacks by encryption although the user need not memorize any information other than the password. | 2011-12-22 |
20110314291 | Digital signature program, digital signature apparatus, and digital signature method - When input data (f | 2011-12-22 |
20110314292 | POWER ANALYSIS ATTACK COUNTERMEASURE FOR THE ECDSA - Execution of the Elliptic Curve Digital Signature Algorithm (ECDSA) requires determination of a signature, which determination involves arithmetic operations. Some of the arithmetic operations employ a long term cryptographic key. It is the execution of these arithmetic operations that can make the execution of the ECDSA vulnerable to a power analysis attack. In particular, an attacker using a power analysis attack may determine the long term cryptographic key. By modifying the sequence of operations involved in the determination of the signature and the inputs to those operations, power analysis attacks may no longer be applied to determine the long term cryptographic key. | 2011-12-22 |
20110314293 | Method of Handling a Server Delegation and Related Communication Device - A method of handling a server delegation for a first server in a service system supporting a device management (DM) protocol is disclosed. The method comprises receiving a delegation message with a first signature from a second server via a delegation session, wherein the second server has a control of a plurality of management objects of a client; generating a delegation request message comprising the delegation message and the first signature; and sending the delegation request message with a second signature to the client in the service system, to obtain the control of the part of the plurality of management objects of the client. | 2011-12-22 |
20110314294 | PASSWORD CHECKING - A method is disclosed for password checking. After input is received, a proposed password included in the input is parsed into symbols. At least one of the symbols includes two or more characters. A probably metric is determined based on a sequence of symbols. The probability metric is used to determine whether or not the password is secure. | 2011-12-22 |
20110314295 | Storage Device and Method for Communicating a Password between First and Second Storage Devices Using a Double-Encryption Scheme - A first storage device provides a host device with access to a private memory area by communicating a password between the first storage device and a second storage device via the host device using a double-encryption scheme. In one embodiment, a host device receives a twice-encrypted password from a first storage device, sends the twice-encrypted password to a second storage device, receives a once-encrypted password from the second storage device, decrypts the once-encrypted password to obtain the password, and sends the password to the first storage device. In another embodiment, a first storage device sends a twice-encrypted password to a host device, receives the password from the host device after the twice-encrypted password is decrypted by a second storage device and the host device, and provides the host device with access to the private memory area only if the password matches one that is stored in the first storage device. | 2011-12-22 |
20110314296 | Host Device and Method for Communicating a Password between First and Second Storage Devices Using a Double-Encryption Scheme - A first storage device provides a host device with access to a private memory area by communicating a password between the first storage device and a second storage device via the host device using a double-encryption scheme. In one embodiment, a host device receives a twice-encrypted password from a first storage device, sends the twice-encrypted password to a second storage device, receives a once-encrypted password from the second storage device, decrypts the once-encrypted password to obtain the password, and sends the password to the first storage device. In another embodiment, a first storage device sends a twice-encrypted password to a host device, receives the password from the host device after the twice-encrypted password is decrypted by a second storage device and the host device, and provides the host device with access to the private memory area only if the password matches one that is stored in the first storage device. | 2011-12-22 |
20110314297 | EVENT LOG AUTHENTICATION USING SECURE COMPONENTS - Some embodiments provide a system that facilitates use of a computing device. During operation, the system obtains an event description of an event on the computing device. Next, the system computes a message authentication code (MAC) for the event description using a secure component associated with the computing device. Finally, the system uses the MAC to maintain the integrity of an event log containing the event description. | 2011-12-22 |
20110314298 | SYSTEM AND METHOD FOR N-ARY LOCALITY IN A SECURITY CO-PROCESSOR - Enhancing locality in a security co-processor module of a computing system may be achieved by including one or more additional attributes such as geographic location, trusted time, a hardware vendor string, and one or more environmental factors into an access control space for machine mode measurement of a computing system. | 2011-12-22 |
20110314299 | ELECTRONIC APPARATUS, DISPLAY DRIVING APPARATUS, AND DIGITAL CONTENT DISPLAY METHOD THEREOF - A digital content display method adaptable to an electronic apparatus is provided. The electronic apparatus includes a display interface and a display driving apparatus. The digital content display method includes following steps. An encrypted digital content is received by the display driving apparatus. The encrypted digital content is decrypted by the display driving apparatus according to an algorithm. The display interface of the electronic apparatus is driven by the display driving apparatus according to the decrypted digital content so that the display interface displays the digital content. Additionally, an electronic apparatus and a display driving apparatus thereof are also provided. | 2011-12-22 |
20110314300 | Segmented Mapping - Described are methods and apparatus, including computer program products for masking data. The inventions involves receiving a mapping scheme with a number of segments and a different cryptographic algorithm for each segment and then receiving a target value to be masked. The target value is then split into a number of segments based on the number of segments of the mapping scheme and the cryptographic algorithm is applied for each segment in the mapping scheme to each segment of the target value to generate an encrypted segment for each segment in the target value. Then, the encrypted segments are concatenated to create a masked value. | 2011-12-22 |