| 51st week of 2011 patent applcation highlights part 42 |
| Patent application number | Title | Published |
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| 20110312090 | CARDIOMYOCYTE MEDIUM WITH DIALYZED SERUM - Methods and composition for maintenance of cardiomyocytes are provided. For example, in certain aspects methods including culturing the cardiomyocytes in a medium essentially free of serum or containing dialyzed serum to maintain long-term purity. In further aspects, methods for modulation of cardiomyocytes may be provided. | 2011-12-22 |
| 20110312091 | PLURIPOTENT STEM CELLS, METHOD FOR PREPARATION THEREOF AND USES THEREOF - Human pluripotent stem cells which are isolated from cut human umbilical cord or placenta and characteristic of cell surface marker CD151 | 2011-12-22 |
| 20110312092 | DUAL-TERMINAL AMIDE HYDROGELLING AGENT - Disclosed is a benzamide derivative represented by formula (1). In the formula, k1 represents an integer from 0-4, m1 represents an integer from 1-100, and n1 represents an integer from 1-6. In addition, R | 2011-12-22 |
| 20110312093 | COMPOSITIONS AND METHODS FOR PREVENTION AND TREATMENT OF AMYLOID-BETA PEPTIDE-RELATED DISORDERS - The present invention provides methods and compositions for modulating levels of amyloid-β peptide (Aβ) exhibited by cells or tissues. The invention also provides pharmaceutical compositions and methods of screening for compounds that modulate Aβ levels. The invention also provides modulation of Aβ levels via selective modulation (e.g., inhibition) of ATP-dependent γ-secretase activity. The invention also provides methods of preventing, treating or ameliorating the symptoms of a disorder, including but not limited to an Aβ-related disorder, by administering a modulator of γ-secretase, including, but not limited to, a selective inhibitor of ATP-dependent γ-secretase activity or an agent that decreases the formation of active (or optimally active) γ-secretase. The invention also provides the use of inhibitors of ATP-dependent γ-secretase activity to prevent, treat or ameliorate the symptoms of Alzheimer's disease. | 2011-12-22 |
| 20110312094 | USE OF DOUBLE STRANDED RNA TO INCREASE THE EFFICIENCY OF TARGETED GENE ALTERATION IN PLANT PROTOPLASTS - Method for targeted gene alteration in protoplasts of plant cells comprising the steps of transiently transfecting the protoplasts with a dsRNA that preferably targets plant MMR mRNA; and a mutagenic nucleobase. The transfection may be simultaneously or subsequently and the gene can be any gene functional in the mismatch repair system. | 2011-12-22 |
| 20110312095 | METHOD AND CONSTRUCTS FOR INCREASING RECOMBINANT PROTEIN PRODUCTION IN PLANTS DEHYDRATION STRESS - The present invention provides methods and constructs for increasing recombinant protein production in plants during dehydration stress. The invention includes nucleic acids, inducible expression systems, and methods for using same for increasing recombinant protein production in plants and plant protection. | 2011-12-22 |
| 20110312096 | CHEMICAL INDICATOR COMPOSITIONS, INDICATORS AND METHODS - Chemical indicator compositions comprising a bismuth compound; elemental sulfur; and a compound with relatively high water solubility which makes the composition alkaline when exposed to water vapor at an elevated temperature; a chemical indicator comprising a substrate and the composition coated on at least a portion of a major surface of the substrate; and methods of making and using the chemical indicator are disclosed. | 2011-12-22 |
| 20110312097 | GEL FOR RADIATION DOSIMETER AND RADIATION DOSIMETER WHICH USES THE SAME - Gel for radiation dosimeter including a gel part (A) and a gel part (B) that become cloudy when exposed to a fixed dose or more, wherein said gel part (A) exposed to more than a specified dose above the fixed dose maintains a cloudy state regardless of the decrease in external temperature; and said gel part (B) exposed to less than the specified dose above the fixed dose changes gradually from a cloudy state into a transparent state according to the decrease in external temperature. | 2011-12-22 |
| 20110312098 | SYSTEM AND METHOD OF ASSESSING NANOTUBE PURITY - The present invention is directed to methods for assessing the purity of carbon nanotube (CNT) compositions, specifically, a method for assessing the presence of contaminants in a CNT composition using polyaryl ethynyl (PAE) conjugate polymer as an indicator material. Additionally, compositions and kits comprising a polyaryl ethynyl (PAE) conjugate polymer are also provided. | 2011-12-22 |
| 20110312099 | USE OF PSYCHROPHILIC ANAEROBIC DIGESTION IN SEQUENCING BATCH REACTOR FOR DEGRADATION OF PRIONS - The present invention relates to the use or process of use of a sequencing batch reactor for eliminating prion in specified risk materials and for measuring the efficacy of a sequencing batch reactor to degrade prion proteins in specified risk materials. | 2011-12-22 |
| 20110312100 | ASSAY METHOD FOR DETECTING PRIMARY AMINES - The invention provides an assay method for the detection of a primary amine analyte in an aqueous body fluid, which method comprises contacting a sample of said body fluid at a pH below 9.5 with a thiol and an unsaturated cis-dialdehyde and testing for the presence of a pyrrole reaction product. | 2011-12-22 |
| 20110312101 | REFRIGERANT COMPOSITION CONTAINING HYDROFLUOROPROPENE WITH LOW-GLOBAL WARMING POTENTIAL - The present invention provides a stabilized refrigerant composition containing a hydrofluoropropene with low global warming potential (GWP) that can remain stable even in the presence of air (oxygen) for a long period of time. More specifically, the present invention provides a refrigerant composition containing a hydrofluoropropene and a stabilizer. The stabilizer is at least one member selected from the group consisting of alkylcatechols, alkoxyphenols, benzoquinones, phenothiazines, and phthalates. | 2011-12-22 |
| 20110312102 | LIGHT TRANSMISSIVE TEMPERATURE CONTROL APPARATUS AND BIO-DIAGNOSIS APPARATUS INCLUDING THE SAME - A light transmissive temperature control apparatus, a bio-diagnosis apparatus including the transmissive temperature control apparatus, and a method of diagnosing biochemical reaction using the bio-diagnosing apparatus are provided. The light transmissive temperature control apparatus includes at least one tube which is formed of a light transmissive material and configured to contain a sample; and a temperature control unit which accommodates at least a part of the at least one tube which is transparent, guides light to be irradiated onto the at least one tube, and controls a temperature of the at least one tube. | 2011-12-22 |
| 20110312103 | SAMPLE DETECTION SENSOR AND SAMPLE DETECTION METHOD - The present invention uses a detecting plate having a transparent substrate on which a single-crystal Si thin film layer, a transparent thin film layer, and a sample capturing layer for capturing a sample are provided. The present invention comprises a light directing mechanism for directing light through said transparent substrate of the detecting plate, and a light detection mechanism for detecting reflected light of the incident light from the detecting plate. The present invention is configured so that a change in absorbance occurs at the sample capturing layer or in the vicinity thereof, when said sample is captured on said sample capturing layer. The wavelengths of said incident light are determined in a range of wavelengths within which said change in absorbance occurs. In this way, the sample is detected by means of measuring a significant change in intensity of the reflected light which is generated when the sample is captured on the sample capturing layer. | 2011-12-22 |
| 20110312104 | IMMUNOASSAY METHOD - Provided is an immunoassay method that can reduce the effort of establishing an immunoassay system due to not needing two or more antibodies, and that is applicable to not only high molecular weight antigens but also to low molecular weight antigens such as hapten. The method is for releasing, from a surface of a base plate, immunoglobulin G antibody bound to the surface via protein A. The method includes the following steps (A) and (B): (A) a step of preparing the base plate having the surface to which immunoglobulin G antibody produced by a producer cell line of deposit No. FERM BP-10459 is bound via protein A; and (B) a step of providing a solution (from pH 6 to pH 8.9; preferably, from pH 7.4 to pH 8.9) containing human serum albumin onto the surface so as to release the immunoglobulin G antibody from the protein A. | 2011-12-22 |
| 20110312105 | DETECTION SYSTEM AND METHOD FOR HIGH SENSITIVITY FLUORESCENT ASSAYS - This invention relates to a detection system for measuring a fluorescent signal in a fluorescent assay. The system comprises a probe having a small sensing surface bound with a fluorescent label, and a light source and a detector both mounted at the proximal side of the sensing surface of the substrate. The invention also relates to a method for detecting an analyte in a liquid sample using a probe tip having a small surface area (≦5 mm) and a high molecular weight polymer (≧1 MD) having multiple binding molecules and multiple fluorescent labels. The binding reaction is accelerated by flowing the reaction solutions laterally and moving the probe tip up and down in the reaction vessels. The invention furthers relates to a fluorescent labeling composition comprising a cross-linked Ficoll molecule having a plurality of binding molecules and a plurality of fluorescent labels. | 2011-12-22 |
| 20110312106 | METHOD FOR PREPARING A LIGHT-EMITTING DEVICE USING GAS CLUSTER ION BEAM PROCESSING - A method of manufacturing semiconductor-based light-emitting devices, such as light-emitting diodes (LEDs), is described. The method comprises irradiating an interface region with a gas cluster ion beam (GCIB) to improve the interface region between a light-emitting device stack and the substrate, within the light-emitting device stack, and/or between the light-emitting device stack and a metal contact layer in an end-type contact. | 2011-12-22 |
| 20110312107 | METHOD AND DEVICE FOR MEASURING TEMPERATURE DURING DEPOSITION OF SEMICONDUCTOR - Provided is a method and a device for measuring a temperature which can recognize the temperature of a semiconductor layer directly with high precision when the semiconductor layer is formed by deposition. The quantity of laser light transmitted a semiconductor layer is monitored by a photodetector by using laser light having a wavelength As at which the transmittance of light changes abruptly when the temperature of the semiconductor layer reaches Ts during or after deposition. When heat being given to the semiconductor layer is changed, the quantity of laser light monitored by the photodetector changes abruptly when the temperature of the semiconductor layer reaches Ts at a time A, B or C. Consequently, the fact that the temperature of the semiconductor layer reached Ts at a time A, B or C can be recognized exactly, and an error in temperature information observed by a device for measuring temperature variations can be calibrated, for example. | 2011-12-22 |
| 20110312108 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized. | 2011-12-22 |
| 20110312109 | LIGHT EMITTING DIODE PACKAGE HAVING ANODIZED INSULATION LAYER AND FABRICATION METHOD THEREFOR - An LED package having an anodized insulation layer which increases heat radiation effect to prolong the lifetime LEDs and maintains high luminance and high output, and a method therefor. The LED package includes an Al substrate having a reflecting region and a light source mounted on the substrate and connected to patterned electrodes. The package also includes an anodized insulation layer formed between the patterned electrodes and the substrate and a lens covering over the light source of the substrate. The Al substrate provides superior heat radiation effect of the LED, thereby significantly increasing the lifetime and light emission efficiency of the LED. | 2011-12-22 |
| 20110312110 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a light emitting element having a first surface and a second surface, the first surface having a first electrode provided thereon, the second surface being located on the opposite side from the first surface and having a second electrode provided thereon; a first conductive member connected to the first surface; a second conductive member connected to the second surface; a first external electrode connected to the first conductive member; a second external electrode connected to the second conductive member; and an enclosure sealing the light emitting element, the first conductive member, and the second conductive member between the first external electrode and the second external electrode, and being configured to transmit light emitted from the light emitting element. | 2011-12-22 |
| 20110312111 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof. | 2011-12-22 |
| 20110312112 | LIGHT EMITTING DIODE - A light emitting diode having a substrate, an electron injection layer, an active layer, a hole injection layer, a first pad electrically connected to the hole injection layer, and a second pad electrically connected to the electron injection layer. The hole injection layer includes an activated region and a patterned non-activated region. The first pad is disposed upon the non-activated region and the first pad and the non-activated region are overlapping in the vertical direction. | 2011-12-22 |
| 20110312113 | LIGHT-EMITTING DIODE STRUCTURE WITH ELECTRODE PADS OF SIMILAR SURFACE ROUGHNESS AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode (LED) structure and a method for manufacturing the LED structure are disclosed for promoting the recognition rate of LED chips, wherein a roughness degree of the surface under a first electrode pad of a first conductivity type is made similar to that of the surface under a second electrode pad of a second conductivity type, so that the luster shown from the first electrode pad can be similar to that from the second electrode pad, thus resolving the poor recognition problem of wire-bonding machines caused by different lusters from the first and second electrode pads. | 2011-12-22 |
| 20110312114 | METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE - It is an object to prevent disordered orientation of liquid crystal molecules which is due to division of substrates even when a liquid crystal dripping method is used, and to provide a method for manufacturing a liquid crystal display device in which liquid crystal is not adversely affected even when a sealant not cured and liquid crystal are in contact. In a method for manufacturing a liquid crystal display device using a liquid crystal dripping method, a scribe groove is provided for at least one of a pair of substrates with a diamond cutter or the like before the pair of substrates are attached under reduced pressure. After the scribing, the pair of substrates are attached under reduced pressure, heat treatment for curing the sealant and aligning the liquid crystal molecules is performed, and the substrates are divided by applying impact using a breaking apparatus. | 2011-12-22 |
| 20110312115 | LASER MACHINING METHOD AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR LIGHT-EMITTING ELEMENT - Provided is a laser machining method in which, when modified regions are formed plural number of times by changing the depth in the thickness direction of a substrate, displacement of the formed modified regions from a planned cutting line is inhibited. Specifically provided is a laser machining method for cutting a substrate ( | 2011-12-22 |
| 20110312116 | ELECTRONIC DISPLAYS USING OPTICALLY PUMPED LUMINESCENT SEMICONDUCTOR NANOCRYSTALS - A multicolor electronic display is based on an array of luminescent semiconductor nanocrystals. Nanocrystals which emit tight of different colors are grouped into pixels. The nanocrystals are optically pumped to produce a multicolor display. Different sized nanocrystals are used to produce the different colors. A variety of pixel addressing systems can be used. | 2011-12-22 |
| 20110312117 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The method can include forming an active layer including indium (In) on a heated substrate. The method can include forming a multiple-layer film made of a nitride semiconductor on the active layer in a state of the substrate being heated to substantially the same temperature as a temperature of the forming of the active layer. In addition, the method can include cooling the substrate to room temperature after the forming of the multiple-layer film. | 2011-12-22 |
| 20110312118 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A micromachine includes a microstructure and a semiconductor element formed over one insulating substrate. The micromachine includes including a movable layer containing polycrystalline silicon and a space below or above the layer. Such polycrystalline silicon is formed on an insulating surface, so that it is used as a microstructure and used for forming a semiconductor element. Accordingly, a semiconductor device may include a microstructure and a semiconductor provided over one insulating substrate. | 2011-12-22 |
| 20110312119 | ETCHING OF SOLAR CELL MATERIALS - A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid and hydrogen peroxide may be employed to etch the copper layer selective to the tin layer. A particular example of the aforementioned etchant is a Co-Bra Etch® etchant modified to comprise about 1% by volume of sulfuric acid, about 4% by volume of phosphoric acid, and about 2% by volume of stabilized hydrogen peroxide. In one embodiment, an aluminum layer in the solar cell is etched without substantially etching the tin layer. For example, an etchant comprising potassium hydroxide may be employed to etch the aluminum layer without substantially etching the tin layer. | 2011-12-22 |
| 20110312120 | ABSORBER REPAIR IN SUBSTRATE FABRICATED PHOTOVOLTAICS - The invention relates generally to methods of repairing defects in thin films. Void defects in thin films are repaired using methods that take advantage of substrate manufacturing protocols rather than conventional superstrate manufacturing protocols. Methods described herein are simple, robust and compatible with existing processes and equipment used in the manufacture of superstrate devices. | 2011-12-22 |
| 20110312121 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A method for manufacturing a photoelectric conversion device including a first-conductivity-type crystalline semiconductor region, an intrinsic crystalline semiconductor region, and a second-conductivity-type semiconductor region that are stacked over an electrode is provided for a new anti-reflection structure. An interface between the electrode and the first-conductivity-type crystalline semiconductor region is flat. The intrinsic crystalline semiconductor region includes a crystalline semiconductor region, and a plurality of whiskers that are provided over the crystalline semiconductor region and include a crystalline semiconductor. The first-conductivity-type crystalline semiconductor region and the intrinsic crystalline semiconductor region are formed by a low pressure chemical vapor deposition method at a temperature higher than 550° C. and lower than 650° C. The second-conductivity-type semiconductor region is formed by a low pressure chemical vapor deposition method at a temperature lower than or equal to 550° C. or higher than or equal to 650° C. | 2011-12-22 |
| 20110312122 | METAL SPECIES SURFACE TREATMENT OF THIN FILM PHOTOVOLTAIC CELL AND MANUFACTURING METHOD - A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate including a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer overlying the copper layer to form a multi-layered structure. The method subjects at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species and form a copper indium disulfide material. The copper indium disulfide material includes a thickness of substantially copper sulfide material. The thickness of the copper sulfide material is removed to expose a surface region having a copper poor surface characterized by a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a metal cation species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic. A window layer is formed overlying the copper indium disulfide material. | 2011-12-22 |
| 20110312123 | Method for forming conductive electrode pattern and method for manufacturing solar cell with the same - Disclosed herein is a conductive electrode pattern used as an electrode of a solar cell. The conductive electrode pattern includes a lower metal layer and an upper metal layer vertically disposed on a substrate, wherein any one of the lower metal layer and the upper metal layer includes silver (Ag) and the other one of the lower metal layer and the upper metal layer includes a metal of transition metals, different from that of the lower metal layer. | 2011-12-22 |
| 20110312124 | METHOD OF FABRICATING THIN FILM SOLAR CELL - Disclosed is a method of fabricating a thin film solar cell. A separation process (‘P4’ process) of insulating a thin film solar cell from the outside is integrally performed with a transparent electrode patterning process (‘P3’ process) and a metallic electrode patterning process (‘P3’ process). This may reduce the fabrication costs and enhance spatial efficiency as the ‘P4’ process and equipment for the ‘P4’ process are not required. | 2011-12-22 |
| 20110312125 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method includes the steps of: (1) coating a solution containing an organic semiconductor material on a water-repellent surface of a water-repellent stamp substrate; (2) drying the thus coated organic semiconductor material-containing solution on the water-repellent surface to crystallize the organic semiconductor material in contact with the water-repellent surface, thereby forming a semiconductor layer; (3) thermally treating the semiconductor layer formed on the stamp substrate; and (4) pressing the stamp substrate at a side, in which the thermally treated organic semiconductor layer is formed, against a surface of a substrate to be transferred so that the organic semiconductor layer is transferred to the surface of the substrate to be transferred. | 2011-12-22 |
| 20110312126 | METHOD FABRICATING A PHASE-CHANGE SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a phase-change semiconductor memory device includes a plasma treatment of an electrode connected to a phase-change material pattern after a conductive layer used to form the electrode has been planarized in the presence of an oxidizing agent. The plasma is formed from a plasma gas having a molecular weight of 17 or less. | 2011-12-22 |
| 20110312127 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor and having improved electric characteristics. The semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The method includes the steps of forming a first insulating film including gallium oxide over and in contact with the oxide semiconductor film; forming a second insulating film over and in contact with the first insulating film; forming a resist mask over the second insulating film; forming a contact hole by performing dry etching on the first insulating film and the second insulating film; removing the resist mask by ashing using oxygen plasma; and forming a wiring electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode through the contact hole. | 2011-12-22 |
| 20110312128 | STACK PACKAGE HAVING REDUCED ELECTRICAL CONNECTION LENGTH SUITABLE FOR HIGH SPEED OPERATIONS AND METHOD OF MANUFACTURING THE SAME - A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads. | 2011-12-22 |
| 20110312129 | INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES - A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate. | 2011-12-22 |
| 20110312130 | STACKED PACKAGE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire. | 2011-12-22 |
| 20110312131 | Forming A Semiconductor Package Including A Thermal Interface Material - In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed. | 2011-12-22 |
| 20110312132 | METHOD FOR POSITIONING CHIPS DURING THE PRODUCTION OF A RECONSTITUTED WAFER - A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips. | 2011-12-22 |
| 20110312133 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached. | 2011-12-22 |
| 20110312134 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - The reliability of a semiconductor device is enhanced. A first lead frame, a first semiconductor chip, a second lead frame, and a second semiconductor chip are stacked over an assembly jig in this order with solder in between and solder reflow processing is carried out to fabricate their assembly. Thereafter, this assembly is sandwiched between first and second molding dies to form an encapsulation resin portion. The upper surface of the second die is provided with steps. At a molding step, the second lead frame is clamped between the first and second dies at a position higher than the first lead frame; and a third lead frame is clamped between the first and second dies at a higher position. The assembly jig is provided with steps at the same positions as those of the steps in the upper surface of the second die in positions corresponding to those of the same. | 2011-12-22 |
| 20110312135 | Method of forming a polycrystalline silicon layer and method of manufacturing thin film transistor - A method of crystallizing a silicon layer and a method of manufacturing a TFT, the method of crystallizing a silicon layer including forming a catalyst metal layer on a substrate; forming a catalyst metal capping pattern on the catalyst metal layer; forming a second amorphous silicon layer on the catalyst metal capping pattern; and heat-treating the second amorphous silicon layer to form a polycrystalline silicon layer. | 2011-12-22 |
| 20110312136 | STRUCTURE AND METHOD FOR COMPACT LONG-CHANNEL FETs - A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided. | 2011-12-22 |
| 20110312137 | Vertical Power MOSFET and IGBT Fabrication Process with Two Fewer Photomasks - A process for fabrication of a power semiconductor device is disclosed in which a single photomask is used to define each of p-conductivity well regions and n-conductivity type source regions. In the process a single photomask is deposited on a layer of polysilicon on a wafer, the polysilicon layer is removed from first regions of the power semiconductor device where the p-conductivity well regions and the n-conductivity type source regions are to be formed, and both p-conductivity type and n-conductivity type dopants are introduced into the wafer through the first regions. | 2011-12-22 |
| 20110312138 | Methods of Manufacturing Power Semiconductor Devices with Trenched Shielded Split Gate Transistor - Methods of manufacturing power semiconductor devices include forming trenches in a substrate, depositing a shield oxide layer that conforms to the trenches, depositing a gate polysilicon layer into the trenches, etching the gate polysilicon layer so that the gate polysilicon layer is recessed in the trench, etching the shield oxide layer so that the shield oxide layer is recessed in the trench and lower than the gate polysilicon layer, depositing a layer of gate oxide across the top of the substrate, sidewalls of the trenches and troughs inside the trenches leaving a recess, depositing shield polysilicon in the recess, etching the shield polysilicon layer so that the shield polysilicon layer is recessed in the trench and higher than the gate polysilicon layer, forming a well region, and forming a source region. The well region can be formed with a −p-well implant. The source region can be performed with an n+ source implant. | 2011-12-22 |
| 20110312139 | SEMICONDUCTOR DEVICE WITH A GATE HAVING A BULBOUS AREA AND A FLATTENED AREA UNDERNEATH THE BULBOUS AREA AND METHOD FOR MANUFACTURING THE SAME | 2011-12-22 |
| 20110312140 | MULTIPLE-GATE TRANSISTORS AND PROCESSES OF MAKING SAME - A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane. | 2011-12-22 |
| 20110312141 | SEMICONDUCTOR DEVICE FABRICATION METHOD INCLUDING HARD MASK AND SACRIFICIAL SPACER ELEMENTS - Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region. | 2011-12-22 |
| 20110312142 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region. | 2011-12-22 |
| 20110312143 | STRAIN-COMPENSATED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor. | 2011-12-22 |
| 20110312144 | NOVEL METHOD TO ENHANCE CHANNEL STRESS IN CMOS PROCESSES - The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current. | 2011-12-22 |
| 20110312145 | SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 2011-12-22 |
| 20110312146 | BIPOLAR DEVICE HAVING BURIED CONTACTS - This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector. | 2011-12-22 |
| 20110312147 | TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR - Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance C | 2011-12-22 |
| 20110312148 | CHEMICAL VAPOR DEPOSITION OF RUTHENIUM FILMS CONTAINING OXYGEN OR CARBON - Methods for depositing ruthenium-containing films are provided herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing film to an oxygen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the oxygen-containing gas exposed ruthenium-containing film may be annealed in a hydrogen-containing gas to remove at least some oxygen from the ruthenium-containing film. In some embodiments, the deposition, exposure, and annealing may be repeated to deposit the ruthenium-containing film to a desired thickness. | 2011-12-22 |
| 20110312149 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer. | 2011-12-22 |
| 20110312150 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides. | 2011-12-22 |
| 20110312151 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 2011-12-22 |
| 20110312152 | Methods of Fabricating Integrated Circuit Devices Using Selective Etching Techniques that Account for Etching Distance Variations - Methods of fabricating integrated circuit devices include forming an integrated circuit capacitor on a substrate. This integrated circuit capacitor includes a lower capacitor electrode, a capacitor dielectric region on the lower capacitor electrode and an upper capacitor electrode on the capacitor dielectric region. The upper capacitor electrode has a smaller surface area relative to the lower capacitor electrode. An interlayer insulating layer is formed on the integrated circuit capacitor. This interlayer insulating layer is polished to have a planarized surface thereon that is spaced from an upper surface of the upper capacitor electrode by a first distance and spaced from an upper surface of the lower capacitor electrode by a second distance greater than the first distance. A step is performed to selectively etch first and second via holes of unequal size in the interlayer insulating layer to expose the upper surface of the lower capacitor electrode and the upper surface of the upper capacitor electrode, respectively. This etching step is performed using an etching process that concurrently etches portions of the interlayer insulating layer associated with the first via hole at a faster rate than portions of the interlayer insulating layer associated with the second via hole, which is larger than the first via hole. | 2011-12-22 |
| 20110312153 | METHOD OF MAKING A FLOATING GATE NON-VOLATILE MOS SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED CAPACITIVE COUPLING AND DEVICE THUS OBTAINED - A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined. simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed. | 2011-12-22 |
| 20110312154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive pattern is formed over the isolation insulating film, and an insulating film is formed over the isolation insulating film, the conductive pattern and the side face of the conductive pattern, and the side face of the conductive pattern comprises a notch. | 2011-12-22 |
| 20110312155 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×10 | 2011-12-22 |
| 20110312156 | CONTROLLED TEMPERATURE IMPLANTATION - In order to reduce and render uniform the surface roughness and variations in thickness of a layer after detachment (post-fracture) of a donor substrate, the mean temperature of the donor substrate during implantation thereof is controlled so as to be in the range 20° C. to 150° C. with a maximum temperature variation of less than 30° C. | 2011-12-22 |
| 20110312157 | WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits. | 2011-12-22 |
| 20110312158 | METHOD AND APPARATUS FOR DIVIDING THIN FILM DEVICE INTO SEPARATE CELLS - A method and apparatus for dividing a thin film device having a first layer which is a lower electrode layer, a second layer which is an active layer and a third layer which is an upper electrode layer, the layers each being continuous over the device, into separate cells which are electrically interconnected in series. The dividing of the cells and the electrical connection between adjacent cells are carried out in a single pass of a process head across the device, the process head performing the following steps in the single pass:
| 2011-12-22 |
| 20110312159 | Methods of Fabricating Nitride Semiconductor Structures with Interlayer Structures - A semiconductor structure includes a first layer of a nitride semiconductor material, a substantially unstrained nitride interlayer on the first layer of nitride semiconductor material, and a second layer of a nitride semiconductor material on the nitride interlayer. The nitride interlayer has a first lattice constant and may include aluminum and gallium and may be conductively doped with an n-type dopant. The first layer and the second layer together have a thickness of at least about 0.5 μm. The nitride semiconductor material may have a second lattice constant, such that the first layer may be more tensile strained on one side of the nitride interlayer than the second layer may be on the other side of the nitride interlayer. | 2011-12-22 |
| 20110312160 | Liquid precursor for deposition of copper selenide and method of preparing the same - Liquid precursors containing copper and selenium suitable for deposition on a substrate to form thin films suitable for semiconductor applications are disclosed. Methods of preparing such liquid precursors and methods of depositing a precursor on a substrate are also disclosed. | 2011-12-22 |
| 20110312161 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A film of an epitaxial layer that allows the reduction in both the height of a bunching step and crystal defects caused by a failure in migration of reactive species on a terrace is formed on a SiC semiconductor substrate having an off angle of 5 degrees or less. A film of a first-layer epitaxial layer is formed on and in contact with a surface of the SiC semiconductor substrate having an off angle of 5 degrees or less. Subsequently, the temperature in a reactor is lowered. A second-layer epitaxial layer is caused to epitaxially grow on and in contact with a surface of the first-layer epitaxial layer. In the above-described manner, the epitaxial layer is structured with two layers, and the growth temperature for the second epitaxial layer is set lower than the growth temperature for the first epitaxial layer. | 2011-12-22 |
| 20110312162 | CHEMICAL VAPOUR DEPOSITION SYSTEM AND PROCESS - A chemical vapour deposition system, including: a process tube for receiving at least one sample, the process tube being constructed of silicon carbide, impregnated with silicon, and coated with silicon carbide; a pumping system to evacuate the process tube to high vacuum; one or more gas inlets for introducing one or more process gases into the evacuated process tube; and a heater to heat the process tube and thereby heat the one or more process gases and the at least one sample within the process tube to cause a material to be deposited onto the at least one sample within the process tube by chemical vapour deposition. | 2011-12-22 |
| 20110312163 | Large Area Nanoenabled Macroelectronic Substrates and Uses Therefor - A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described. | 2011-12-22 |
| 20110312164 | FORMING AN ELECTRODE HAVING REDUCED CORROSION AND WATER DECOMPOSITION ON SURFACE USING A CUSTOM OXIDE LAYER - The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision. | 2011-12-22 |
| 20110312165 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A layer including a semiconductor film is formed over a glass substrate and is heated. A thermal expansion coefficient of the glass substrate is greater than 6×10 | 2011-12-22 |
| 20110312166 | Methods of Manufacturing Power Semiconductor Devices with Shield and Gate Contacts - Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first conductive layer away inside an active trench, forming a second oxide layer and second conductive layer. The second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench. The methods further include forming a third oxide layer over the second conductive layer, etching a first opening through the third oxide layer exposing the second conductive layer outside the active trench, etching a second opening through the second oxide layer outside the active trench in the first region exposing the first conductive layer but not the second conductive layer, and filling the first and second openings with conductive material. | 2011-12-22 |
| 20110312167 | PLASMA PROCESSING APPARATUS, AND DEPOSITION METHOD AN ETCHING METHOD USING THE PLASMA PROCESSING APPARATUS - A plasma processing apparatus, comprising:
| 2011-12-22 |
| 20110312168 | FORMATION OF SHALLOW JUNCTIONS BY DIFFUSION FROM A DIELECTRIC DOPED BY CLUSTER OR MOLECULAR ION BEAMS - A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10 | 2011-12-22 |
| 20110312169 | ANTI-FUSE MEMORY CELL - An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor. | 2011-12-22 |
| 20110312170 | SEMICONDUCTOR DEVICE AND FABRICATION MEHTOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode. Accordingly, the semiconductor element itself can have air-tightness, it is not necessary to cover the gate electrode surface with a damp-proof protective film, gate capacitance of the semiconductor element is reduced, and high frequency characteristics and gain of the semiconductor element improve. | 2011-12-22 |
| 20110312171 | Methods Of Forming Integrated Circuitry Comprising Charge Storage Transistors - Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region. | 2011-12-22 |
| 20110312172 | Methods of Forming Patterns and Methods of Manufacturing Semiconductor Devices Using the Same - In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate. | 2011-12-22 |
| 20110312173 | Method of Fabricating a Semiconductor Device - The invention relates to semiconductor devices and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer, the second conductive layer, the dielectric layer, and the first conductive layer are patterned so that the first conductive layer partially remains to prevent the tunnel insulating layer from being exposed. Sidewalls of the gate electrode layer are etched. A first passivation layer is formed on the entire surface including the sidewalls of the gate electrode layer. At this time, a thickness of the first passivation layer formed on the sidewalls of the gate electrode layer is thicker than that of the first passivation layer formed in other areas. A cleaning process is performed to thereby remove byproducts occurring in the etch process. A gate pattern is formed by etching the first passivation layer, the first conductive layer, and the tunnel insulating layer. | 2011-12-22 |
| 20110312174 | Methods Of Manufacturing Three-Dimensional Semiconductor Devices - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 2011-12-22 |
| 20110312175 | METHODS FOR FORMING ANTIFUSES WITH CURVED BREAKDOWN REGIONS - Methods are disclosed for forming an antifuse that includes first and second conductive regions having spaced-apart curved portions, with a first dielectric region therebetween, forming in combination with the curved portions a curved breakdown region adapted to switch from a substantially non-conductive initial state to a substantially conductive final state in response to a predetermined programming voltage. A sense voltage less than the programming voltage is used to determine the state of the antifuse as either OFF (high impedance) or ON (low impedance). A shallow trench isolation (STI) region is desirably provided adjacent the breakdown region to inhibit heat loss from the breakdown region during programming. Lower programming voltages and currents are observed compared to antifuses using substantially planar dielectric regions. In a further embodiment, a resistive region is inserted in one lead of the antifuse with either planar or curved breakdown regions to improve post-programming sense reliability. | 2011-12-22 |
| 20110312176 | FORMING AN ELECTRODE HAVING REDUCED CORROSION AND WATER DECOMPOSITION ON SURFACE USING AN ORGANIC PROTECTIVE LAYER - Accordingly, the present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A substrate which has a conductive layer disposed thereon is provided and the conductive layer has an oxide layer with an exposed surface. The exposed surface of the oxide layer contacts a solution of an organic surface active compound in an organic solvent to form a protective layer of the organic surface active compound over the oxide layer. The protective layer has a thickness of from about 0.5 nm to about 5 nm and ranges therebetween depending on a chemical structure of the surface active compound. | 2011-12-22 |
| 20110312177 | PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME - The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate, said inorganic antireflective coating is vapor deposited and comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La; forming at least one interconnect pattern within the at least one patternable low-k material; and curing the at least one patternable low-k material. The inventive method can be used to form dual-damascene interconnect structures as well as single-damascene interconnect structures. | 2011-12-22 |
| 20110312178 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY ELEMENT AND SPUTTERING APPARATUS - The present invention provides a method for manufacturing a semiconductor memory element including a chalcogenide material layer and an electrode layer, each having an improved adhesion, and a sputtering apparatus thereof. One embodiment of the present invention is the method for manufacturing a semiconductor memory element including: a first step of forming the chalcogenide material layer ( | 2011-12-22 |
| 20110312179 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - The present invention provides a substrate processing method and a substrate processing apparatus, which are capable of forming a high-k dielectric film with few trapping levels due to oxygen deficiencies and hot carriers by a sputtering method in one and the same vacuum vessel. The substrate processing method according to a first embodiment of the present invention includes: a first step of heating a to-be-processed substrate ( | 2011-12-22 |
| 20110312180 | POST CMP PLANARIZATION BY CLUSTER ION BEAM ETCH - The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies. | 2011-12-22 |
| 20110312181 | METHOD FOR CHEMICAL MECHANICAL PLANARIZATION OF A COPPER-CONTAINING SUBSTRATE - A method using an associated composition for chemical mechanical planarization of a copper-containing substrate affords high copper removal rates and low dishing values during CMP processing of the copper-containing substrate, including an abrasive, at least three surfactants, preferably non-ionic and preferably three distinct surfactants, preferably in the range of 100 ppm to 2000 ppm per surfactant and an oxidizing agent. | 2011-12-22 |
| 20110312182 | METHOD AND APPARATUS FOR CHEMICAL-MECHANICAL PLANARIZATION - A method and apparatus for performing chemical-mechanical planarization (CMP) is disclosed, which in one embodiment includes a CMP tool for polishing a semiconductor wafer. The CMP tool includes a slurry mixture that has slurry beads. The slurry beads are formed of a polymer material. The slurry beads are used to remove summits and non-uniformities on the semiconductor wafer. In some embodiments the CMP tool includes a counter-face that replaces the polishing pad of a conventional CMP tool. In some embodiments the counter-face is made of polycarbonate. In another embodiment a slurry mixture for use with a CMP tool is disclosed. The slurry mixture includes slurry beads, where each of the slurry beads has a diameter of between 0.1 and 1000 microns, or in some embodiments a diameter of between 10 and 50 microns. | 2011-12-22 |
| 20110312183 | Method of Fine Patterning Semiconductor Device - For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography. | 2011-12-22 |
| 20110312184 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a pattern of a semiconductor device is disclosed. The method for forming the semiconductor device pattern can simplify a fabrication process using Spacer Patterning Technology (SPT), and at the same time can form a microscopic contact hole. The method for forming the semiconductor device pattern includes forming a hard mask layer and a photoresist film pattern over an underlying layer to be etched; forming one or more first spacers over sidewalls of the photoresist film pattern; removing the photoresist film pattern; forming a sacrificial film pattern by burying a sacrificial film in a region between the first spacers; after removing the first spacer, and forming one or more second spacers over sidewalls of the sacrificial film pattern; after removing the sacrificial film pattern, etching the hard mask layer using the second spacer as an etch mask, and forming a hard mask pattern; and forming a contact hole pattern by etching the underlying layer using the hard mask layer pattern as a mask. | 2011-12-22 |
| 20110312185 | PATTERN FORMATION METHOD AND PATTERN FORMATION DEVICE - According to one embodiment, a pattern formation method includes: forming a first pattern in a first region on a substrate to be treated; coating a plurality of types of block copolymers which are different in composition ratio on a second region which is different from the first region; and forming in the second region, by a heat treatment, a second pattern including a plurality of types of structures based on the coated plurality of types of block copolymers. | 2011-12-22 |
| 20110312186 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop | 2011-12-22 |
| 20110312187 | MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE AND CLEANING METHOD OF MANUFACTURING APPARATUS FOR SEMICONDUCTOR - A manufacturing apparatus for a semiconductor device, including: a reaction chamber configured to perform film formation on a wafer; a process gas supplying mechanism provided in an upper part of the reaction chamber and configured to introduce process gas to an interior of the reaction chamber; a gas discharging mechanism provided in a lower part of the reaction chamber and configured to discharge gas from the reaction chamber; a supporting member configured to hold the wafer; a cleaning gas supplying mechanism provided in an outer periphery of the supporting member and configured to emit cleaning gas in an outer periphery direction below an upper end of the supporting member; a heater configured to heat the wafer; and a rotary driving mechanism configured to rotate the wafer. | 2011-12-22 |
| 20110312188 | PROCESSING APPARATUS AND FILM FORMING METHOD - A processing apparatus for processing objects, includes: a processing container structure having a bottom opening and including a processing container having a processing space for housing the objects, the container having a nozzle housing area on one side of the processing space and a slit-like exhaust port on the opposite side of the processing space from the nozzle housing area; a lid for closing the bottom opening of the processing container structure; a support structure for supporting the objects and which can be inserted into and withdrawn from the processing container structure; a gas introduction means including a gas nozzle housed in the nozzle housing area; an exhaust means including a plurality of exhaust systems for exhausting the atmosphere in the processing container structure; a heating means for heating the objects; and a control means for controlling the gas introduction means, the exhaust means and the heating means. | 2011-12-22 |
| 20110312189 | SUBSTRATE TREATING APPARATUS AND SUBSTRATE TREATING METHOD - A substrate treating apparatus is provided. The substrate treating apparatus includes a loading/unloading unit, a process unit in which a substrate treating process is performed, a loadlock unit disposed between the loading/unloading unit and the process unit, and a carrying member transferring a substrate between the process unit and the loadlock unit. Herein, the carrying member is provided in the process unit and the loadlock unit, and the loading/unloading unit, the loadlock unit, and the process unit are sequentially disposed. | 2011-12-22 |
