51st week of 2012 patent applcation highlights part 30 |
Patent application number | Title | Published |
20120320595 | LIGHT SOURCE HAVING LED ARRAYS FOR DIRECT OPERATION IN ALTERNATING CURRENT NETWORK AND PRODUCTION METHOD THEREFOR - To allow a direct connection of a light source to a 230V/50 Hz or 120V/60 Hz AC network and to ensure safe operation and easy adaptation to user requirements when mounting, the light source includes a series connection which is connected to a bridge rectifier (GL) and includes at least two LED arrays strands, which have several interconnected individual LEDs, and a pre-resistor, which are arranged on a plate-like, electrically contacting carrier that dissipates heat, has protection against contact and carries the at least two array-LED-strands. For direct operation in an AC voltage supply, the sum of the flow voltages of the LED arrays (U | 2012-12-20 |
20120320596 | POSITIONING APPARATUS AND SYSTEM FOR DIRECTING A BEAM - The present invention relates to an apparatus for positioning at least one optical element ( | 2012-12-20 |
20120320597 | LIGHT ASSEMBLY - A light assembly includes a fixing unit and a lighting unit located within a lamp cover. The fixing unit includes a substrate board with a recessed shape, and an elastic steel ring is engaged with the hook flange of the substrate board in order to increase the tightness between the substrate board and the lamp cover so as to prevent water vapor and salt mist from entering into the light assembly, and thereby the corrosion of light source and circuit can be avoided. The light emitting diode is used as a light source instead of the conventional halogen lamp. | 2012-12-20 |
20120320598 | LIGHT EMITTING APPARATUS AND LIGHT EMITTING UNIT - A fluorescent lamp type light emitting apparatus is provided. The light emitting apparatus comprises a cover, a light emitting module, radiation pads, and cap parts. The cover comprises a first cover and a transmissive second cover coupled to the first cover. The light emitting module comprises a plurality of light emitting diodes in the cover. The radiation pads are disposed on the light emitting module. The cap parts comprise electrode terminals at both ends of the cover. | 2012-12-20 |
20120320599 | LIGHT SOURCE DEVICE - A light source device having: a light source; first and second light guides extending in a first predetermined direction to guide light in the first predetermined direction and irradiate a document with the light; and a confinement portion that confines light emitted by the light source and is connected to one end of the first light guide and one end of the second light guide, in which the light confined in the confinement portion is reflected off both first and second reflection surfaces provided in the confinement portion, and thereby travels through the first and second light guides in the first predetermined direction. | 2012-12-20 |
20120320600 | WHITE FILM AND SURFACE LIGHT SOURCE USING SAME - A white film has reflective properties, concealing properties and film-forming stability and can be made into a thin film, a white film, which contains voids therein and satisfies the following formulae (i) to (iii) is provided: | 2012-12-20 |
20120320601 | MOUNTING SUBSTRATE AND MANUFACTURING METHOD THEREOF, LIGHT-EMITTING MODULE AND ILLUMINATION DEVICE - An object of the present invention is to provide a mounting substrate, a manufacturing method, a light-emitting module and an illumination device that can sufficiently improve the luminous efficiency of an LED lamp. A mounting substrate according to the present invention includes a substrate and a reflective film that is formed on a front surface of the substrate and has a front surface on which LED chips are to be mounted, and the reflective film is made of metal oxide microparticles and a glass fit, and reflects light from the LED chips. | 2012-12-20 |
20120320602 | ENGAGEABLE LED OPTICS AND LIGHTING FIXTURES INCORPORATING THEM - Total internal reflection (TIR) optics have an engagement member that mates with a complementary feature on the LED holder. The engagement member does not interfere with light propagation through or emission from the optical component, and does not enlarge the footprint area occupied by the optical component. | 2012-12-20 |
20120320603 | LAMP ASSEMBLY - A lamp assembly includes a shell wall defining a receiving space that retains a light source therein, and a reflecting unit. The shell wall has a central wall unit and a pair of connecting wall segments. The central wall unit has a base wall segment and a pair of connecting wall segments extending respectively from longitudinal ends of the base wall segment. The extending wall segments extend respectively from side ends of the base wall segment, interconnect the connecting wall segments and cooperate with the connecting wall segments to define an opening in spatial communication with the receiving space. A distance between the distal ends of the connecting wall segments is larger than that between the distal ends of the extending wall segments. The reflecting unit includes convex first reflecting members protruding inwardly from the extending wall segments, and prismatic second reflecting members protruding inwardly from the central wall unit. | 2012-12-20 |
20120320604 | LOW-PROFILE E-READER LIGHT - A device for illuminating a surface of a member is provided that includes a light transmissive element having a substantially planar surface adapted to be situated over and separated from the member surface. The device also includes a light source adapted to emit light rays that directly illuminate the member surface and light rays directed between the element surface and the member surface at an angle causing a substantial portion of the light rays to be reflected by the element surface onto the member surface to illuminate the member surface. The light rays reflected from the member surface pass through the element such that the illuminated member surface can be observed. An apparatus for illuminating a surface is provided that includes an arrangement reflecting light toward the member that is positioned over the member and separated from the member by a gap, and an arrangement emitting light into the gap. | 2012-12-20 |
20120320605 | LAMPSHADE FRAME ASSEMBLY - An improved lampshade frame assembly comprising: a frame device, including an upper frame, a lower frame and a link rod seat coupled to the upper frame or the lower frame; a hood device, including a hood, a connecting strip with appropriate elasticity and separately formed at upper and lower positions of an internal side of the hood, and an external side of the connecting strip being fixed to the hood, and a pair of embedding grooves formed on an internal side of the connecting strip for coupling the upper frame and the lower frame respectively to achieve the effects of reducing the material and weight of a lamp and the packaging volume of the lampshade frame, saving the transportation cost, providing a secured assembly of the hood and frame, improving the quality, and enhancing the add-on value of the lamp. | 2012-12-20 |
20120320606 | ENVELOPE-CONFIGURED LAMP SHADE - A lamp shade envelops and holds a lamp assembly that includes a light bulb having an enclosure portion and a connector portion connected to a lamp socket. The lamp shade includes two sheets joined at opposite side margins to form an envelope with separable top and bottom side margins. Each sheet is characterized by a rigidity property exhibiting an elastic restorative force that urges together the separable top and the bottom side margins in the absence of a lamp assembly positioned between the sheets. Spatially aligned openings in the sheets form a two-sided lamp shade aperture from which sections of the enclosure portion protrude when the lamp assembly is positioned within an interior space between the joined sheets. The sheets bend around the enclosure portion to expand the envelope to a convex shape, and the elastic restorative force holds the enclosure portion in place within the interior space. | 2012-12-20 |
20120320607 | WAVELENGTH CONVERSION MEMBER, LIGHT EMITTING DEVICE AND IMAGE DISPLAY DEVICE, AND METHOD FOR MANUFACTURING WAVELENGTH CONVERSION MEMBER - Disclosed is a wavelength conversion member that is provided with: a light transmissive member including a light input plane into which excitation light is inputted, and a light output plane from which wavelength converted light is outputted; and a semiconductor fine particle phosphor, which is dispersed in the light transmissive member, and which absorbs the excitation light, converts the wavelength, and emits light. The dispersion concentration of the semiconductor fine particle phosphor in the direction parallel to the light traveling direction, i.e., the direction connecting the light input plane and the light output plane, is lower than the dispersion concentration of the semiconductor fine particle phosphor in the direction orthogonal to the light traveling direction. | 2012-12-20 |
20120320608 | Luminaire With Enhanced thermal Dissipation Characteristics - A luminaire with enhanced thermal dissipation characteristics is disclosed. The luminaire may comprise a housing having a first external housing segment and a second external housing segment, the first and second external housing segments being spaced apart to provide an annular opening between the segments. A light source may be positioned at least partially within the first external housing segment, and a heat exchanger may be positioned at least partially within the second external housing segment. The luminaire described herein provides a light source with enhanced thermal dissipation features in an aesthetically pleasing package. | 2012-12-20 |
20120320609 | Socket Device - A lighting fixture capable of efficiently radiating heat of a lamp device may be configured to be attached to a socket device. In some examples, by attaching the lamp device to the socket device, a cap portion of the lamp device is brought into contact with a fixture body, and pressed against and brought into close contact with the fixture body by an elastic body. Heat generated by lighting of LEDs of the lamp device is conducted from the cap portion to the fixture body and efficiently radiated. | 2012-12-20 |
20120320610 | Socket Device - A lighting fixture capable of efficiently radiating heat of a lamp device may be configured to be attached to a socket device. In some examples, by attaching the lamp device to the socket device, a cap portion of the lamp device is brought into contact with a fixture body, and pressed against and brought into close contact with the fixture body by an elastic body. Heat generated by lighting of LEDs of the lamp device is conducted from the cap portion to the fixture body and efficiently radiated. | 2012-12-20 |
20120320611 | Socket Device - A lighting fixture capable of efficiently radiating heat of a lamp device may be configured to be attached to a socket device. In some examples, by attaching the lamp device to the socket device, a cap portion of the lamp device is brought into contact with a fixture body, and pressed against and brought into close contact with the fixture body by an elastic body. Heat generated by lighting of LEDs of the lamp device is conducted from the cap portion to the fixture body and efficiently radiated. | 2012-12-20 |
20120320612 | MOTORCYCLE REAR PORTION STRUCTURE - A rear portion structure ( | 2012-12-20 |
20120320613 | Apparatus and method for a vehicle safety system for driving vehicles at night - A safety system for drivers while driving vehicles at night in un-illuminated areas has side lights that are positioned one on each side of a vehicle, near front of the vehicle. The side lights illuminate areas on left and right sides of the vehicle near the front-end of the vehicle and operating in conjunction with head lights enable drivers to maintain visual reference to the surroundings to avoid the risk of disorientation while driving at night in un-illuminated areas. The side lights in conjunction with head lights also enable drivers to be able to see curved roads ahead. The position of the side lights in the vehicle is integrated with the head lights of the vehicle and the operational control is integrated with the operational control of head lights of the vehicle. The side lights illuminate a distance from the vehicle that is substantially equal to one to three single-road-widths. | 2012-12-20 |
20120320614 | WHEEL LIGHTS - A wheel light assembly may be mounted on wheel studs of a wheel hub, between the wheel hub and the rim of the wheel. The wheel light assembly may include a mounting plate having wheel stud holes in a pattern matching the pattern of the wheel studs onto which the light assembly is to be mounted. The wheel light assembly may further include one or more light bars extending from the mounting plate. The light bars may include one or more lights connected to a power source. The power source may be solar power and/or a battery. The wheel light assembly may include a remote power switch for turning the power to the light bars on and off from inside the vehicle. The vehicle may be an automobile, motorcycle, bicycle or any similar wheeled vehicle. | 2012-12-20 |
20120320615 | ILLUMINATED COMPONENT - The component has a planar decorative element ( | 2012-12-20 |
20120320616 | LIGHTING MODULE FOR AN EMERGENCY SERVICE VEHICLE - The invention relates to a lighting module ( | 2012-12-20 |
20120320617 | VEHICLE HEADLIGHT - The disclosed subject matter includes a projector headlight using a plurality of optical units for a low beam with a high visible/visual quality. Each of the optical units can include a plurality of LED devices and a projector lens. The projector lens can include a light-emitting surface including a reflex function and a reflex surface including a light incoming surface that is located on the opposite side of the light-emitting surface. The LED devices can be located adjacent the light incoming surface, and the optical units can be located so that angles between optical axes of adjacent optical units can be identical. Thus, the projector headlight can form various favorable light distribution patterns by changing curvature factors of the light-emitting surface and the reflex surface of the projector lens in each of the optical units and by changing the angles between the optical axes of the adjacent optical units. | 2012-12-20 |
20120320618 | LIGHTED EXTERIOR MIRROR ASSEMBLY FOR VEHICLE - A lighted exterior mirror assembly includes a housing that houses a reflectance element that is movably positionable by the driver of a vehicle to adjust its rearward field of view when the lighted exterior rearview mirror assembly is attached at a side of the vehicle. A ground illumination lamp is disposed at a portion of the lighted exterior mirror assembly and separate from the reflectance element. The ground illumination lamp is a substantially moisture-impervious unit having an enclosure and a lens that is permanently joined with the enclosure. The ground illumination lamp includes a light source disposed within the enclosure behind the lens and, when the lighted exterior mirror assembly is attached at the side of the vehicle and when the light source is electrically powered, the light source emits light that passes through the lens and illuminates a ground area adjacent the side of the vehicle. | 2012-12-20 |
20120320619 | THERMAL-EXPANSION COMPENSATOR AND HEADLAMP - The invention relates to a thermal-expansion compensator for holding a light module in a housing of a headlamp for a motor vehicle, comprising a compensation pin extending along a pin axis with a stop element, wherein the compensation pin can be connected to the housing by means of a connecting means, a compensation element with a compensation body extending along a compensation axis and at least two stop receptacles that are each formed for holding the stop element of the compensation pin, and a holder that is arranged rigidly on the light module. | 2012-12-20 |
20120320620 | SYSTEM FOR DISPLAYING IMAGES ON THE BACK OF A HITCH - An illuminated, image adjustable hitch cover allows a user to provide various images inside the hitch cover without the need to purchase an entire new hitch cover. The hitch cover can include an image, which can be an image printed by the user, such as a picture or text, that is inserted between two panes of clear material, such as clear plastic. The hitch cover may be illuminated along with the user's lights and may brighten or come on when the user pressed their brakes, providing not only a desired aesthetic result, but also a safety function. | 2012-12-20 |
20120320621 | LUMINOUS VEHICLE GLAZING AND MANUFACTURE THEREOF - A luminous vehicle glazing, containing: a first sheet containing a mineral or an organic glass having a first main face, a second main face, and an injection edge; a peripheral light source with an emitting face, which faces the injection edge; a guided-light extracting element; a peripheral functional element, bonded to the first sheet, which is fluid-tight, including a cavity for placing the peripheral light source; a covering element, which covers the cavity and the peripheral light source, which is fluid-tight, and which is selected from i) a cap combined with an interfacial element, for interfacial fluid-tightness or ii) a fluid-tight sealing mastic covering the peripheral light source and sealing the peripheral functional element. In addition, a method of manufacturing the luminous vehicle glazing. | 2012-12-20 |
20120320622 | DEVICE FOR DISPLAYING AND ILLUMINATING AN IMAGE - Some embodiments may include a device for displaying and illuminating images. The device may include a housing including an interior portion. An opening in the housing may provide access to the interior portion. A viewing aperture may be formed in the housing. The device may include a light guide having a light source. The light guide may be removably received within the housing via the opening. The device may include a graphic medium with an image printed thereon. The graphic medium may be removeably received within the housing via the opening and guided via a guide surface disposed on a portion of the light guide. The graphic medium may be guided via the guide surface and positioned with respect to the light guide such that at least a portion of the image is viewable through the aperture and at least partially illuminated via light originating from the light source. | 2012-12-20 |
20120320623 | ILLUMINATING DEVICE AND DISPLAY DEVICE - An illuminating device includes a light guide plate; a light source that is located opposite at least two adjacent end faces of four end faces of the light guide plate; and a chassis that has an opening through which light emanating from a light emission surface of the light guide plate passes. At least one optical sheet that includes a corner portion with an interior angle of greater than 90 degrees in a position corresponding to a corner portion of the light guide plate that is sandwiched between the two end faces opposite the light source is disposed between the light emission surface of the light guide plate and the chassis. | 2012-12-20 |
20120320624 | ILLUMINATING DEVICE AND DISPLAY DEVICE - An illuminating device includes a substantially rectangular light guide plate that includes at least one end face as a light incident surface, a frame that is arranged to surround the light guide plate, and a light source that is located between the light guide plate and the frame so as to face the light incident surface of the light guide plate. The light guide plate and the frame are integrally molded by two-color molding, and at least a part of the end faces of the light guide plate except for the light incident surface is spaced from the frame. Thus, the illuminating device can be made thinner and lighter without reducing the strength and the brightness. | 2012-12-20 |
20120320625 | EDGE LIGHT TYPE PLANAR LIGHT SOURCE DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE - Provided is an edge light type planar light source device capable of preventing luminance unevenness. An edge light type planar light source device ( | 2012-12-20 |
20120320626 | EDGE-LIT LIGHT FIXTURE INCORPORATING A DOWNLIGHT AND HAVING A UNIFORM EXTERNAL APPEARANCE - A light fixture and method for producing downward-propagating illumination are disclosed. The fixture includes an edge-lit lightguide illuminated from its perimeter. The lightguide has a light extractor, such as a dot pattern on its bottom surface, which extracts a portion of the light from inside the lightguide and directs it to a diffuser. The diffuser randomizes the direction of the extracted light and forms diffuse light. The fixture also includes a downlight, arranged above the lightguide and producing a downlight beam downward. The downlight beam transmits from the top face through the bottom face of the lightguide and emerges from the bottom face of the lightguide as a directional beam. The downlight beam has a downlight beam footprint. The light extractor has a light extractor area that excludes the downlight beam footprint, and the diffuser has a diffuser area that also excludes the downlight beam footprint. The fixture can produce both diffuse light and a directional beam, while maintaining a generally uniform external appearance. | 2012-12-20 |
20120320627 | FLAT PANEL LIGHTING DEVICE AND DRIVING CIRCUITRY - The present application is directed to a lighting fixture having a light emitting diode (LED) panel. The light fixture is configured to include a pair of LED configurations that are driven alternately by driving circuitry. The light fixture can include driving circuitry that is configured to be housed within a frame of the LED panel. | 2012-12-20 |
20120320628 | SIDE-LIGHT TYPE LIGHT GUIDE PLATE ASSEMBLY AND BACKLIGHT MODULE - The present invention discloses a side-light type light guide plate assembly and a backlight module, which has a light guide plate and at least one reflector sheet. The light guide plate has a lower surface, a light output surface opposite to the lower surface, and at least one light input side surface connected between the lower surface and the light output surface. The reflector sheet is correspondingly disposed on at least one side surface of the light guide plate except for the light input side surface, while a medium layer is defined between the reflector sheet and the light guide plate. The refraction index of the medium layer is smaller than or equal to 1.12. By providing the air layer and the reflector sheet, light beam emitting out of a side of the light guide plate and going back to the light guide plate can meet conditions of total reflection, so as to prevent from generating a light leakage phenomenon at edges of the light guide plate. | 2012-12-20 |
20120320629 | BACKLIGHT ASSEMBLY AND DISPLAY APPARATUS HAVING THE SAME - A backlight assembly includes a light guiding plate, a light source and a bottom receiving plate. The light source is disposed at a first side of the light guiding plate. The bottom receiving plate includes a bottom surface and a side wall to form a receiving space in which at least a portion of the light guiding plate is placed. The bottom surface is smaller than a lower surface of the light guiding plate and has a plurality of openings formed through the bottom surface. The side wall extends from the bottom surface. | 2012-12-20 |
20120320630 | ILLUMINATION APPARATUS AND DISPLAY DEVICE - Provided is an illumination apparatus which prevents variations in the distance between the light-receiving surface of a light guide plate and a light source. Also provided is a display device which incorporates the illumination apparatus. The light guide plate, which constitutes a backlight unit, receives light through a light-receiving surface with the light-receiving surface oriented toward the light being emitted. In the backlight unit, pillars extend to intersect the direction of emission from an LED and are thus brought into contact with a device-carrying board and the light guide plate, which are superposed one on the other, thereby securing the device-carrying board and the light guide plate. | 2012-12-20 |
20120320631 | COVER AND LIGHT GUIDE PLATE FOR ELECTRONIC DEVICE - A cover includes a molded cover body and a light guide board molded so as to be integral with the cover body. The cover body defines a mounting hole for mounting a keypad or keyboard. | 2012-12-20 |
20120320632 | POWER SWITCH CONTROLLERS AND METHODS USED THEREIN FOR IMPROVING CONVERSION EFFECIENCY OF POWER CONVERTERS - Power switch controllers and methods used therein are disclosed. An exemplifying power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of an inductive device, to generate a trigger signal. The logic controller prevents a power switch connected to the inductive device from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted. | 2012-12-20 |
20120320633 | VARIABLE FREQUENCY PWM SYNCHRONOUS RECTIFIER POWER SUPPLY - The present invention discloses a variable frequency PWM synchronous rectifier power supply comprising: a transformer, a PWM control circuit and a synchronous rectification switch circuit. The transformer has a primary side and a secondary side, and an isolation circuit is provided for separating the primary side and the secondary side, and the primary side uses a transmit/receive switch circuit to drive the transformer, and the secondary side uses a filter circuit to output different voltages to an external load. The PWM control circuit is situated on the secondary side and coupled to the isolation circuit and filter circuit, for generating a control signal to the isolation circuit to drive the transmit/receive switch circuit. The synchronous rectification switch circuit is situated on the secondary side and coupled to the PWM control circuit for receiving a timing delay control signal provided by the PWM control circuit. | 2012-12-20 |
20120320634 | METHOD AND APPARATUS FOR A CONTROL CIRCUIT WITH MULTIPLE OPERATING MODES - An example controller for use in a power converter includes an oscillator that is to be coupled to a switch of the power converter to determine a switching cycle period of the switch. The controller also includes means for controlling a duty cycle of the switch to regulate an output of the power converter and for maintaining a substantially constant rate of change of the duty cycle with respect to changes in a magnitude of a feedback signal as the controller transitions between duty cycle control modes such that a control loop gain of the power converter is substantially constant during the transition. | 2012-12-20 |
20120320635 | MAXIMIZE EFFICIENCY METHOD FOR RESONANT CONVERTER WITH SELF-ADJUSTING SWITCHING POINTS - A maximize efficiency method for resonant converter with self-adjusting switching points is disclosed. The method is operated by a resonant converter, which comprises a transformer and a field effect transistor (FET). When the transistor is turned on, energy is stored in the transformer. When the transistor is turned off, a resonant signal is generated at a drain of the transistor. At this time, a suitable trigger time has to be found to turn on the transistor, so as to reduce switching power loss. The method measures the slope of the resonant signal at the trigger time. This is used as a reference to adjust the next cycle's trigger time. If the slope is negative at the time of trigger, a delta time is added to the trigger time in the next cycle, If the slope is positive, a delta time is subtracted from the trigger time for the next cycle. | 2012-12-20 |
20120320636 | SWITCHING POWER SUPPLY APPARATUS - A control circuit performs at least one of detecting whether the resonance current detected by the current detection unit is beyond a first detection level over a predetermined time period, and detecting, when detecting that the resonance current is beyond the first detection level over the predetermined time period, that the resonance current falls below a second detection level, and detecting whether the resonance current detected by the current detection unit is below a first detection level over a predetermined time period, and detecting, when detecting that the resonance current is below the first detection level over the predetermined time period, that the resonance current exceeds a second detection level, and inverts, when detecting that the resonance current falls below or exceeds the second detection level, the levels of the drive control signal at which the first switching element and the second switching element are turned on or off. | 2012-12-20 |
20120320637 | SWITCHING POWER SOURCE APPARATUS - A switching power source apparatus has a pulse generator of a first pulse. A first resonant series circuit receives the first pulse signal and passes a current having a 90-degree phase delay with respect to the first pulse signal. The current of the first resonant series circuit turns on/off a switching element Q | 2012-12-20 |
20120320638 | RESONANT CIRCUIT AND RESONANT DC/DC CONVERTER - The present disclosure relates to a resonant circuit ( | 2012-12-20 |
20120320639 | METHOD AND APPARATUS TO SELECT A PARAMETER/MODE BASED ON A MEASUREMENT DURING AN INITIALIZATION PERIOD - A power supply includes an energy transfer element coupled between an input and an output. A switch is coupled to an input of the energy transfer element. A threshold detection circuit includes in an integrated circuit coupled to measure a signal from a resistive external circuit coupled between fourth and first external terminals of the integrated circuit during an initialization period after the fourth external terminal has been charged to a supply threshold value. A regulator circuit is coupled between second and fourth external terminals of the integrated circuit. The regulator circuit is coupled to charge the fourth external terminal to the supply threshold value during the initialization period. A selection circuit is coupled to the threshold detection circuit to select a parameter/mode of the integrated circuit in response to the measured signal. | 2012-12-20 |
20120320640 | METHOD AND APPARATUS FOR PROGRAMMING A POWER CONVERTER CONTROLLER WITH AN EXTERNAL PROGRAMMING TERMINAL HAVING MULTIPLE FUNCTIONS - A power converter controller is disclosed. An example controller includes a control circuit coupled to receive a feedback signal representative of an output of the power converter. The control circuit coupled to control a switching of a power switch of the power converter in response to the feedback signal to control a transfer of energy from an input of the power converter to the output of the power converter. An internal programming interface circuit is coupled to the control circuit. A coupling switcher is coupled to the internal programming interface circuit. An external programming terminal is selectively coupled to the internal programming interface circuit through the coupling switcher. An external programming circuit coupled to the external programming terminal is coupled to the internal programming interface circuit through the coupling switcher during a startup programming condition and during a fault condition of the power converter. The external programming circuit that is coupled to the external programming terminal is decoupled from the internal programming interface circuit by the coupling switcher during a normal operating condition of the power converter. | 2012-12-20 |
20120320641 | POWER CONVERTER BUS CONTROL - Processes, machines, and articles of manufacture that may management power conversion as provided. This may include circuit topology or management that serves to improve power conversion efficiency from a DC waveform to an AC waveform. This circuit topology or management may include considering and managing the voltage across a DC-link capacitive bus and the phase angle output of an AC waveform in order to influence or improve power conversion characteristics or efficiency. | 2012-12-20 |
20120320642 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes a substrate; and a compound semiconductor multilayer structure which is formed above the substrate and which contains compound semiconductors containing Group III elements, wherein the compound semiconductor multilayer structure has a thickness of 10 μm or less and a percentage of aluminum atoms is 50% or more of the number of atoms of the Group III elements. | 2012-12-20 |
20120320643 | SNUBBER CIRCUIT AND INVERTER WITH THE SAME - An inverter may include an inversion unit for converting a direct current bus voltage into an alternating current voltage, a first snubber unit, and a second snubber unit. The inversion unit may include a first external switch, a first internal switch, a second internal switch, and a second external switch which are connected in series in order between a direct current bus positive voltage terminal and a direct current bus negative voltage terminal. The first snubber unit may be connected between the direct current bus negative voltage terminal and the first internal switch for suppressing voltage stress of the first internal switch. The second snubber unit may be connected between the direct current bus positive voltage terminal and the second internal switch for suppressing voltage stress of the second internal switch. | 2012-12-20 |
20120320644 | DEVICE AND METHOD FOR DC TO AC CONVERSION - The present invention provides a DC to AC converter including a device enabling separation of electric current into a positive portion of the circuit and a negative portion of the circuit, each portion of the circuit including an electronic switch, wherein one portion of the circuit is adapted to produce a wave form in a positive half cycle, the second portion of the circuit is adapted to produce a wave form in a negative half cycle, the voltage of the output current is fed to a polarity switch as feedback to change the polarity, and wherein the carrier duty cycle is adapted to change from 0 to 100 percent in each polarity. | 2012-12-20 |
20120320645 | Power Converter - A power converter which has a power module allowing supply and cutoff of main current, and a driver module controlling supply and cutoff of the main current allowed by the power module includes: a high potential side semiconductor device which allows supply and cutoff of the main current on the high potential side of the power module; a low potential side semiconductor device which allows supply and cutoff of the main current on the low potential side of the power module, and is connected with the high potential side semiconductor device in series; plural power module side wirings connected with respective electrodes contained in the high potential side semiconductor device and the low potential side semiconductor device, and disposed adjacent to each other substantially on the same plane as the power module in the order of applied potentials with a connection end between the plural power module side wirings and the driver module located along the end of the power module; plural driver module side wirings provided on the driver module as wirings connected with the plural corresponding power module side wirings, and disposed adjacent to each other substantially on the same plane as the driver module in the order corresponding to the positions of the plural power module side wirings in positions along the end of the driver module; a power source transformer as a circuit which converts a signal voltage for controlling the supply and cutoff of the main current by the driver module into voltage applied to a control electrode of the high potential side semiconductor device and a control electrode of the low potential side semiconductor device, plural terminals of the power source transformer in correspondence with the plural driver module side wirings being provided in the order of the positions of the plural corresponding driver module side wirings; and conductors disposed in the vicinity of the plane on which the plural power module side wirings are provided and in the vicinity of the plane on which the plural driver module side wirings are provided, and electrically connected in such positions as to surround magnetic flux generated by current looping at least through the power source transformer, the driver module side wirings, and the power module side wirings. | 2012-12-20 |
20120320646 | DIMMER SYSTEM AND CONTROL SYSTEM AND METHOD THEREOF - A control system includes a detection circuit, a control circuit, and a dummy load system. The detection circuit is operable to detect a voltage level change of a direct-current voltage and output an activating signal when detecting the voltage level change of the DC voltage. The control circuit is operable to receive the activating signal. The dummy load system is electrically connected to the control circuit, and the control circuit controls the dummy load system by generating a turn-on signal in response to receiving the activating signal. A dimmer system and a control method thereof are further disclosed in herein. | 2012-12-20 |
20120320647 | SWITCHING BRANCH FOR THREE-LEVEL RECTIFIER, AND THREE-PHASE THREE-LEVEL RECTIFIER - An exemplary switching branch for a three-level rectifier includes a first diode and a first semiconductor switch connected in series between a positive direct voltage pole and a neutral direct voltage pole, a second diode and a second semiconductor switch connected in series between a negative direct voltage pole and the neutral direct voltage pole as well as a thyristor and a third diode connected in series between a connection point between the first diode and the first semiconductor switch and a connection point between the second diode and the second semiconductor switch in such a manner that a connection point between the thyristor and the third diode is connected to an alternating voltage pole of the switching branch. | 2012-12-20 |
20120320648 | CYCLO-CONVERTER AND METHODS OF OPERATION - A three phase full resonant cyclo-converter suitable for converting a three phase AC supply to a DC output. In one embodiment the cyclo-converter consists of two half bridge cyclo-converters driving a resonant circuit. The main switching sequence of the cyclo-converter may consist of a switching sequence in which the phases of a three phase supply are switched in a repeating sequence from the largest to the smallest absolute voltage value of the supply phases. | 2012-12-20 |
20120320649 | DISCHARGE CONTROL APPARATUS FOR POWER CONVERTING SYSTEM WITH CAPACITOR - A discharge controller carries out discharge control by determining a voltage to be applied to a conduction control terminal of each of switching elements such that a current in a non-saturation region of one of the switching elements is lower than a current in a non-saturation region of the other thereof, and applying the voltage to the conduction control terminal of each switching element with an opening-closing member opening an electrical path to turn on the switching elements, resulting in short-circuit of both electrodes of a capacitor so that a discharge current is outputted from the capacitor based on the discharge control. A manipulator manipulates, based on a value of the discharge current, how to apply the voltage to the conduction control terminal of the one of the switching elements, thus controlling an amount of heat to be generated in the one of the switching elements. | 2012-12-20 |
20120320650 | METHOD FOR CONTROLLING A CONVERTER - A method controls a three-phase converter with a voltage intermediate circuit by pulse-width modulation for supplying a polyphase system, in particular a three-phase machine. The converter is operated with at least two different modulation methods which are selected from among the group of modulation methods which includes single-phase switching, two-phase switching and three-phase switching, and for chageovers to be made between the at least two different modulation methods depending on the operating state of the polyphase system. | 2012-12-20 |
20120320651 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a semiconductor substrate; a memory cell array provided above the semiconductor substrate and including a plurality of memory cells that are stacked; a plurality of bit lines connected electrically to the plurality of memory cells; and a plurality of sense amplifiers connected to the bit lines via bit line connection lines. The bit line connection lines have every adjacent N lines (where N is an integer of 2 or more) as one group. The sense amplifiers are arranged in a number smaller than N in a first direction that the bit line connection lines extend. An M number of the sense amplifiers are arranged in a width of a P number of groups in a second direction intersecting the first direction. The M number being larger than the P number | 2012-12-20 |
20120320652 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit. | 2012-12-20 |
20120320653 | SEMICONDUCTOR SYSTEM - A device that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 2012-12-20 |
20120320654 | SEMICONDUCTOR SYSTEM - A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit. | 2012-12-20 |
20120320655 | SEMICONDUCTOR DEVICES - A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions. | 2012-12-20 |
20120320656 | Programmable Resistive Memory Unit with Data and Reference Cells - A method and system of a programmable resistive memory having a plurality of programmable resistive memory units is disclosed. At least one of the programmable resistive memory units has at least one data cell and at least one reference cell. The data cell can have one programmable resistive element coupled to at least one diode as a program selector and also coupled to a bitline (BL). The reference cell can have a reference resistive element coupled to at least one reference diode as reference program selector and also coupled to a reference bitline (BLR). In one embodiment, the reference resistive element can have substantially the same material, structure, or shape of the programmable resistive element. In one embodiment, the reference diode can have the same material, structure, or shape of the diode serving as the program selector diode. | 2012-12-20 |
20120320657 | Programmable Resistive Memory Unit with Multiple Cells to Improve Yield and Reliability - A method and system for a programmable resistive memory to improve yield and reliability has a plurality of programmable resistive units. Each programmable resistive unit can have at least one programmable resistive cell. Each programmable resistive cell can have a programmable resistive element with a first end coupled to a first supply voltage line and a second end coupled to at least one diode serving as program selector. Each diode can have at least first and second terminals with first and second types of dopants, with the second terminal being coupled to a second supply voltage line. The first and second terminals of the diode can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. | 2012-12-20 |
20120320658 | NONVOLATILE STATIC RANDOM ACCESS MEMORY CELL AND MEMORY CIRCUIT - A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line. | 2012-12-20 |
20120320659 | RESISTANCE-CHANGE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a first current to flow through the bit line and causing a second current smaller than the first current to flow through the bit line, thereby controlling a resistance decreasing operation in which the memory element is made to transit from a high resistance state to a low resistance state by using the second current. | 2012-12-20 |
20120320660 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 2012-12-20 |
20120320661 | METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT AND NONVOLATILE STORAGE DEVICE - A method includes applying a first polarity writing voltage pulse to a metal oxide layer to change its resistance state from high to low into a write state, applying a second polarity erasing voltage pulse different from the first polarity to the metal oxide layer to change its resistance state from low to high into an erase state, and applying an initial voltage pulse having the second polarity to the metal oxide layer before first application of the writing voltage pulse, to change an initial resistance value of the metal oxide layer. R | 2012-12-20 |
20120320662 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage. | 2012-12-20 |
20120320663 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A memory device with low power consumption is provided. A memory device includes a first logic element generating an output potential by inverting a polarity of a potential of a signal including data in accordance with a first clock signal; second and third logic elements holding the output potential generated by the first logic element; a switching element including a transistor; and a capacitor storing the data by being supplied with the output potential of the first logic element which is held by the second and third logic elements via the switching element. The second logic element generates an output potential by inverting a polarity of an output potential of the third logic element in accordance with a second clock signal different from the first clock signal, and the third logic element generates an output potential by inverting a polarity of the output potential of the second logic element. | 2012-12-20 |
20120320664 | SEMICONDUCTOR DEVICE - There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell. | 2012-12-20 |
20120320665 | SEMICONDUCTOR MEMORY - A semiconductor memory includes a first memory cell including: a first resistance change element and a first select transistor. The semiconductor memory includes a second memory cell including: a second select transistor and a second resistance change element. The semiconductor memory includes a third memory cell including: a third select transistor and a third resistance change element, the third memory cell acting as a reference cell. The semiconductor memory includes a fourth memory cell including: a fourth resistance change element and a fourth select transistor, the fourth memory cell acting as a reference cell. | 2012-12-20 |
20120320666 | Magnetoresistive Element and Magnetic Memory - There is provided a magnetoresistive element whose magnetization direction is stable in a direction perpendicular to the film surface and whose magnetoresistance ratio is controlled, as well as magnetic memory using such a magnetoresistive element. By having the material of a ferromagnetic layer forming the magnetoresistive element comprise a ferromagnetic material containing at least one type of | 2012-12-20 |
20120320667 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory according to the present invention is provided with: a magnetic recording layer including a magnetization free region having a reversible magnetization, wherein a write current is flown through the magnetic recording layer in an in-plane direction; a magnetization fixed layer having a fixed magnetization; a non-magnetic layer provided between the magnetization free region and the magnetization fixed layer; and a heat sink structure provided to be opposed to the magnetic recording layer and having a function of receiving and radiating heat generated in the magnetic recording layer. The magnetic random access memory thus-structured radiates heat generated in the magnetic recording layer by using the heat sink structure, suppressing the temperature increase caused by the write current flown in the in-plane direction. | 2012-12-20 |
20120320668 | PHASE QUBIT CELL HAVING ENHANCED COHERENCE - Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias. | 2012-12-20 |
20120320669 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode. | 2012-12-20 |
20120320670 | FAST VERIFY FOR PHASE CHANGE MEMORY WITH SWITCH - A phase change memory with switch (PCMS) compensates for threshold voltage drift by utilizing a lower demarcation voltage for a verify operation after programming than for a read operation occurring at least a predetermined period of time after the programming operation. | 2012-12-20 |
20120320671 | MEMORY DEVICE WITH REDUCED SENSE TIME READOUT - A method for data storage includes providing at least first and second readout configurations for reading storage values from analog memory cells, such that the first readout configuration reads the storage values with a first sense time and the second readout configuration reads the storage values with a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout configurations is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout configuration. | 2012-12-20 |
20120320672 | MEMORY DEVICE READOUT USING MULTIPLE SENSE TIMES - A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations. | 2012-12-20 |
20120320673 | DATA STORAGE SYSTEM HAVING MULTI-LEVEL MEMORY DEVICE AND OPERATING METHOD THEREOF - A method for a data storage system is disclosed. The method includes providing a memory cell array, and providing N blocks in a first region of the memory cell array, N being an integer greater than 1. Each cell of each block of the N blocks is configured to store no more than N−1 bits of data. The method further includes providing a block in the second region of the memory cell array. Each cell of the block in the second region is configured to store N bits of data. The method additionally includes configuring the data storage system so that when data is programmed to the memory cell array, N pages of the data are initially stored in N respective blocks of the first region of the memory cell array, and then the N pages of the data are stored in the block of the second region. | 2012-12-20 |
20120320674 | MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION - An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch. | 2012-12-20 |
20120320675 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 2012-12-20 |
20120320676 | SEMICONDUCTOR SYSTEM, NONVOLATILE MEMORY APPARATUS, AND AN ASSOCIATED READ METHOD - A semiconductor system includes a host configured to output a command, a control signal, an address signal, and data; and a nonvolatile memory apparatus configured to receive at least one of the command, the control signal, the address signal, and the data from the host, to provide a process result to the host, and to determine data levels of memory cells included in an overlap section of memory cell threshold voltage distributions based on an initial read bias voltage. | 2012-12-20 |
20120320677 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line. | 2012-12-20 |
20120320678 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block. | 2012-12-20 |
20120320679 | SYSTEM AND METHOD FOR MINIMIZING WRITE AMPLIFICATION WHILE MAINTAINING SEQUENTIAL PERFORMANCE USING LOGICAL GROUP STRIPPING IN A MULTI-BANK SYSTEM - A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group. | 2012-12-20 |
20120320680 | METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE - A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory. | 2012-12-20 |
20120320681 | REDUCING THE PROGRAMMING CURRENT FOR MEMORY MATRICES - A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells. | 2012-12-20 |
20120320682 | Semiconductor Memory System Including A Plurality Of Semiconductor Memory Devices - A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current. | 2012-12-20 |
20120320683 | COMPENSATING FOR COUPLING DURING PROGRAMMING - Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location). | 2012-12-20 |
20120320684 | METHOD FOR DISCHARGING A VOLTAGE FROM A CAPACITANCE IN A MEMORY DEVICE - In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit. | 2012-12-20 |
20120320685 | ERASE OPERATION CONTROL SEQUENCING APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage. | 2012-12-20 |
20120320686 | SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING THE SAME, AND CONTROLLER - A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal. | 2012-12-20 |
20120320687 | LOW VOLTAGE SENSING SCHEME HAVING REDUCED ACTIVE POWER DOWN STANDBY CURRENT - A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2012-12-20 |
20120320688 | SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE - Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated. | 2012-12-20 |
20120320689 | Performing Logic Functions on More Than One Memory Cell Within an Array of Memory Cells - A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality of bit-line transistors associated with a plurality of physically adjacent memory cells to a read bit-line. In response to an associated memory cell within the memory storing a first value, each of the plurality of read bit-line transistors turns on and provides a path to ground thereby causing a first output value to be output on the read bit-line. In response to all of the plurality of memory cells storing a second value, the plurality of read bit-line transistors turn off thereby preventing a path to ground and a second output value is output on the read bit-line. | 2012-12-20 |
20120320690 | SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING THE SAME, AND CONTROLLER - A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively. | 2012-12-20 |
20120320691 | CLAMPED BIT LINE READ CIRCUIT - One embodiment of the present invention sets forth a clamping circuit that is used to maintain a bit line of a storage cell in a memory array at a nearly constant clamp voltage. During read operations the bit line is pulled high or low from the clamp voltage by the storage cell and a change in current on the bit line is converted by the clamping circuit to produce an amplified voltage that may be sampled to read a value stored in the storage cell. The clamping circuit maintains the nearly constant clamp voltage on the bit line. Clamping the bit line to the nearly constant clamp voltage reduces the occurrence of read disturb faults. Additionally, the clamping circuit functions with a variety of storage cells and does not require that the bit lines be precharged prior to each read operation. | 2012-12-20 |
20120320692 | RANDOM ACCESS MEMORY FOR USE IN AN EMULATION ENVIRONMENT - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. | 2012-12-20 |
20120320693 | DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE - A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation. | 2012-12-20 |
20120320694 | Write assist in a dual write line semiconductor memory - A semiconductor memory storage device is disclosed, the memory having a plurality of storage cells. Each storage cell comprises two access control devices, each of the access control devices providing the storage cell with access to or isolation from a respective one of two data lines in response to an access control signal, the two data lines being connected to one data port; access control circuitry for applying the access control signal via one of two access control lines to control a plurality of the access control devices; wherein one of the two access control devices of each storage cell is controlled by the access control signal received from a first of the two access control lines to provide the storage cell with access to or isolation from a first of the two data lines, and one further of the two access control devices is controlled by the access control signal received from a second of the two access control lines to provide the storage cell with access to or isolation from a second of the two data lines. The access control circuitry is responsive to a data access request, the data access request being a write request, to apply a data value to be written to both of the first and second data lines and to apply the access control signal to both of the first and second access control lines. In some cases the access control signal is applied to the second of the two access control lines a predetermined time after it is applied to the first of the two access control lines. | 2012-12-20 |