51st week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130334591 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method includes forming a second stacked body on the planarized interlayer insulating film and on the uppermost stair. The second stacked body includes a second conductive film thicker than the first conductive film and a second insulating film stacked on the second conductive film. The method includes dividing the second stacked body into a select gate on the uppermost stair and a plurality of wall portions in a staircase region below the uppermost stair. The method includes forming a plurality of vias piercing the interlayer insulating film under a region between the wall portions and reaching the first conductive film of each of the stairs. | 2013-12-19 |
20130334592 | Semiconductor Device - A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section. | 2013-12-19 |
20130334593 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 2013-12-19 |
20130334594 | RECESSED GATE MEMORY APPARATUSES AND METHODS - Some embodiments include a memory device and a method of forming the memory device. One such memory device includes a string of stacked memory cells. Each of the memory cells in the string includes a charge storage structure and a recessed control gate. The recessed control gate has a substantially smooth surface separated from the charge storage structure by dielectric material. One such method includes etching heavily boron doped polysilicon selective to oxide to form a recessed control gate having a surface with nubs. A smoothing solution is applied to the surface of the recessed control gate to smoothen the nubs. Additional apparatuses and methods are described. | 2013-12-19 |
20130334595 | STRUCTURE AND METHOD FOR A FIELD EFFECT TRANSISTOR - Provided is one embodiment of a semiconductor structure that includes a STI feature, wherein the STI feature is a continuous feature and includes a first portion in a first region and a second portion in a second region, and the first portion is recessed relative to the second portion; an active region bordered by the STI feature; a gate stack disposed on the active region and extended in a first direction to the first region of the STI feature; source and drain features formed in the active region and interposed by the gate stack; and a channel formed in the active region and spanned between the source and drain features in a second direction being different from the first direction. The channel includes top portion having a width W in the first direction and two side portions each having a height H less than the width W. | 2013-12-19 |
20130334596 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a substrate comprising a trench; a first electrode disposed below the trench; a second electrode disposed above the trench, a first insulating layer being disposed between the first electrode and the second electrode; a first contact arranged in a first direction of the substrate and connected to the first electrode; and a second contact arranged in second direction that is different from the first direction, the second contact being connected to the second electrode. | 2013-12-19 |
20130334597 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region. | 2013-12-19 |
20130334598 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes first to fourth semiconductor layers, a gate electrode, a field plate electrode, an insulating film, first and second main electrodes, and an insulating section. The second semiconductor layer has the first conductivity type and is provided on the first semiconductor layer. The third semiconductor layer has a second conductivity type and is provided on the second semiconductor layer. A concentration of impurity of the first conductivity type included in the third semiconductor layer is lower than the concentration of impurity of the first conductivity type included in the second semiconductor layer. The fourth semiconductor layer is provided on the third semiconductor layer. The gate electrode extends from the fourth semiconductor layer toward the second semiconductor layer. The field plate electrode is provided below the gate electrode. | 2013-12-19 |
20130334599 | INTEGRATED SNUBBER IN A SINGLE POLY MOSFET - A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2013-12-19 |
20130334600 | TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF - A transistor device and a manufacturing method thereof are provided. The transistor device includes a substrate, a first well, a second well, a shallow trench isolation (STI), a source, a drain and a gate. The first well is disposed in the substrate. The second well is disposed in the substrate. The STI is disposed in the second well. The STI has at least one floating diffusion island. The source is disposed in the first well. The drain is disposed in the second well. The electric type of the floating diffusion island is different from or the same with that of the drain. The gate is disposed above the first well and the second well, and partially overlaps the first well and the second well. | 2013-12-19 |
20130334601 | HIGH VOLTAGE TRENCH TRANSISTOR - A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having a gate electrode, first and second gate dielectric layers is formed in a trench. The trench has an upper trench portion and a lower trench portion. A field plate is formed in the trench. First and second diffusion regions are formed. The gate is displaced from the second diffusion region. | 2013-12-19 |
20130334602 | CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS - Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed. | 2013-12-19 |
20130334603 | ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES - A method including etching a shallow trench laterally surrounding a portion of a semiconductor substrate, the semiconductor substrate comprising a semiconductor-on-insulator SOI layer, a pad oxide layer, and a pad nitride layer, depositing a first nitride liner, a dielectric liner, and a second nitride liner in the shallow trench, wherein the dielectric liner is located between the first and the second nitride liner, and filling the shallow trench with a shallow trench fill portion. | 2013-12-19 |
20130334604 | SOI SEMICONDUCTOR DEVICE COMPRISING A SUBSTRATE DIODE AND A FILM DIODE FORMED BY USING A COMMON WELL IMPLANTATION MASK - When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer. | 2013-12-19 |
20130334605 | MECHANISMS FOR FORMING ULTRA SHALLOW JUNCTION - A fin field-effect transistor (FinFET) includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region uniformly beneath a top surface and sidewall surfaces of the fin structure, the LDD region having a depth less than about 25 nm. Another FinFET includes a substrate and a fin structure over the substrate. The fin structure comprises a lightly doped source and drain (LDD) region, and a top surface of the fin structure has a different crystal structure from a sidewall surface of the fin structure. A method of making a FinFET includes forming a fin structure on a substrate. The method further includes performing a pulsed plasma doping on the fin structure to form lightly doped drain (LDD) regions in the fin structure. | 2013-12-19 |
20130334606 | FinFET with High Mobility and Strain Channel - An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions. | 2013-12-19 |
20130334607 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure. | 2013-12-19 |
20130334608 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor formed on a semiconductor substrate, and including a first channel region, and a first gate electrode formed on the first channel region, and a second transistor formed on the semiconductor substrate, and including a second channel region having a conductivity type identical to a conductivity type of the first channel region, and a second gate electrode formed on the second channel region and having a potential identical to a potential of the first gate electrode. A drain of the first transistor is electrically connected to a source of the second transistor. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor. | 2013-12-19 |
20130334609 | SEMICONDUCTOR DEVICE - In a semiconductor device, an active region includes: a first impurity region to which a predetermined voltage is applied; second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor; and at least one impurity region disposed between the first and second impurity regions. A voltage that causes electrical conduction between the second and third impurity regions is applied to a gate electrode disposed between the second and third impurity regions. All gate electrodes disposed between the first and second impurity regions are configured to be electrically connected to the first impurity region constantly. All impurity regions disposed between the first and second impurity regions are electrically isolated from the first and second impurity regions and maintained in a floating state. | 2013-12-19 |
20130334610 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH - A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements. | 2013-12-19 |
20130334611 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating layer, a first resin layer provided over the insulating layer and the first conductive layer, a layer containing conductive particles which is electrically connected to the first conductive layer through an opening portion provided in the first resin layer, and a substrate provided with a second resin layer and a second conductive layer serving as an antenna. In the semiconductor device having the above-described structure, the second conductive layer is electrically connected to the first conductive layer with the layer containing conductive particles interposed therebetween. In addition, the second resin layer is provided over the first resin layer. | 2013-12-19 |
20130334612 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - An integrated circuit includes a plurality of transistors. Each transistor is associated with a corresponding body terminal. At least one transistor is reverse biased at a first voltage level, and at least one other transistor is reverse biased at a second voltage level that is different from the first voltage level. Each body terminal is electrically isolated from every other body terminal via an isolation barrier. A transistor that is reverse biased at the first voltage level is electrically connected to a transistor that is reverse biased at the second voltage level, such that the electrically connected transistors operate to interact with each other while the respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit. | 2013-12-19 |
20130334613 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE - A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. | 2013-12-19 |
20130334614 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides one embodiment of a field effect transistor (FET) structure. The FET structure includes shallow trench isolation (STI) features formed in a semiconductor substrate; a plurality of semiconductor regions defined in the semiconductor substrate and isolated from each other by the STI features; and a multi-fin active region of a first semiconductor material disposed on one of the semiconductor regions of the semiconductor substrate. | 2013-12-19 |
20130334615 | FinFETs and the Methods for Forming the Same - A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region. | 2013-12-19 |
20130334616 | RELIABLE CONTACTS - A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias. | 2013-12-19 |
20130334617 | GATE STRUCTURE HAVING LIGHTLY DOPED REGION - A gate structure includes a gate dielectric over a substrate, and a gate electrode over the gate dielectric, wherein the gate dielectric contacts sidewalls of the gate electrode. The gate structure further includes a nitrogen-containing dielectric layer surrounding the gate electrode, and a contact etch stop layer (CESL) surrounding the nitrogen-containing dielectric layer. The gate structure further includes an interlayer dielectric layer surrounding the CESL and a lightly doped region in the substrate, the lightly doped region extends beyond an interface of the sidewalls of the gate electrode and the gate dielectric. | 2013-12-19 |
20130334618 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION - A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure. | 2013-12-19 |
20130334619 | INTEGRATED CIRCUIT WITH ION SENSITIVE SENSOR AND MANUFACTURING METHOD - Disclosed is an integrated circuit comprising a substrate ( | 2013-12-19 |
20130334620 | MEMS Devices and Fabrication Methods Thereof - A method for fabricating a MEMS device includes providing a micro-electro-mechanical system (MEMS) substrate having a sacrificial layer on a first side, providing a carrier including a plurality of cavities, bonding the first side of the MEMS substrate on the carrier, forming a first bonding material layer on a second side of the MEMS substrate, applying a sacrificial layer removal process to the MEMS substrate, providing a semiconductor substrate including a second bonding material layer and bonding the semiconductor substrate on the second side of the MEMS substrate. | 2013-12-19 |
20130334621 | HYBRID INTEGRATED COMPONENT AND METHOD FOR THE MANUFACTURE THEREOF - An expansion of the functional scope of a hybrid integrated component including an MEMS element, a cap for the micromechanical structure of the MEMS element, and an ASIC element having circuit components is provided. In this component, the circuit components of the ASIC element interact with the micromechanical structure of the MEMS element. The MEMS element is mounted on the ASIC element in such a way that the micromechanical structure of the MEMS element is situated in a cavity between the cap and the ASIC element. The ASIC element is additionally equipped with the circuit components of a magnetic sensor system. These circuit components are produced in or on the CMOS back-end stack of the ASIC element. The magnetic sensor system may thus be implemented without enlarging the chip area. | 2013-12-19 |
20130334622 | MICROMECHANICAL DEVICE AND METHOD FOR MANUFACTURING A MICROMECHANICAL DEVICE - A micromechanical device, in particular a sensor device, and a method for manufacturing a micromechanical device are provided. The micromechanical device has a housing, the housing including a first cavity, and the housing including a second cavity that is separate from the first cavity. The micromechanical device is configured in such a way that a predetermined first gas pressure prevails in the first cavity, and a predetermined second gas pressure which is reduced compared to the first gas pressure prevails in the second cavity. A heating element is situated in the area of the second cavity. The micromechanical device has a printed conductor, the heating element being heatable with the aid of the printed conductor. | 2013-12-19 |
20130334623 | MEMS Sensing Device and Method for the Same - The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface. | 2013-12-19 |
20130334624 | METHOD OF PROVIDING A SEMICONDUCTOR STRUCTURE WITH FORMING A SACRIFICIAL STRUCTURE - A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate. | 2013-12-19 |
20130334625 | METHOD FOR FABRICATING PATTERNED POLYIMIDE FILM AND APPLICATIONS THEREOF - A method for fabricating a patterned polyimide film, wherein the method comprises steps as follows: Firstly, a polyimide film is provided on a substrate. A wet planarization process is then performed to remove a portion of the polyimide film. Subsequently the planarized polyimide film is patterned. | 2013-12-19 |
20130334626 | HYBRID INTEGRATED COMPONENT AND METHOD FOR THE MANUFACTURE THEREOF - A hybrid integrated component includes: at least one ASIC element having integrated circuit elements and a back-end stack; an MEMS element having a micromechanical structure, which extends over the entire thickness of the MEMS substrate; and a cap wafer. The hybrid integrated component is provided with an additional micromechanical function. The MEMS element is mounted on the ASIC element, so that a gap exists between the micromechanical structure and the back-end stack of the ASIC element. The cap wafer is mounted above the micromechanical structure of the MEMS element. A pressure-sensitive diaphragm structure having at least one deflectable electrode of a capacitor system is implemented in the back-end stack of the ASIC element, which diaphragm structure spans a pressure connection in the rear side of the ASIC element. | 2013-12-19 |
20130334627 | SEMICONDUCTOR INTEGRATED DEVICE ASSEMBLY AND RELATED MANUFACTURING PROCESS - Described herein is a semiconductor integrated device assembly, which envisages: a package defining an internal space; a first die including semiconductor material; and a second die, distinct from the first die, also including semiconductor material; the first die and the second die are coupled to an inner surface of the package facing the internal space. The second die is shaped so as to partially overlap the first die, above the inner surface, with a portion suspended in cantilever fashion above the first die, by an overlapping distance. | 2013-12-19 |
20130334628 | PROCESS FOR MANUFACTURING ELECTRO-MECHANICAL SYSTEMS - A method of avoiding stiction during vapor hydrofluoride (VHF) release of a microelectromechanical system (MEMS) or nanoelectromechanical system (NEMS) composed of a mechanical device and a substrate is described. A silicon nitride layer is provided between the substrate and a sacrificial oxide layer and/or between a device layer and the sacrificial oxide layer, and/or on a side of the device layer facing away from the sacrificial oxide layer, and converted to thicker ammonium hexafluorosilicate with VHF while simultaneously removing a portion of the sacrificial oxide. The ammonium hexafluorosilicate acts as a temporary support, shim, wedge, or tether which limits device movement during fabrication and is later removed by sublimation under heat and/or reduced pressure. | 2013-12-19 |
20130334629 | MTJ Element for STT MRAM - An all (111) MTJ stack is disclosed in which there are no transitions between different crystalline orientations when going from layer to layer. This is accomplished by providing strongly (111)-textured layers immediately below the MgO tunnel barrier to induce a (111) orientation therein. | 2013-12-19 |
20130334630 | MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, MEMORY SYSTEMS, AND METHODS OF FABRICATION - Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems. | 2013-12-19 |
20130334631 | MEMORY CELLS, SEMICONDUCTOR DEVICE STRUCTURES, MEMORY SYSTEMS, AND METHODS OF FABRICATION - Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely-directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication. | 2013-12-19 |
20130334632 | NONVOLATILE MAGNETIC MEMORY DEVICE - A nonvolatile magnetic memory device using a magnetic tunneling junction (MTJ) uses as a data storage unit an MTJ including a pinned magnetic layer, a nonmagnetic insulating layer, and a free magnetic layer which are sequentially stacked. The free magnetic layer includes at least one soft magnetic amorphous alloy layer in which zirconium (Zr) is added to a soft magnetic material formed of cobalt (Co) or a Co-based alloy. | 2013-12-19 |
20130334633 | Magnetic Tunnel Junction With Non-Metallic Layer Adjacent to Free Layer - A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium. | 2013-12-19 |
20130334634 | Single-Package Bridge-Type Magnetic-Field Angle Sensor - A single-package bridge-type magnetic-field angle sensor comprising one or more pairs of magnetic tunnel junction sensor chips rotated relative to each other by 90 degrees in order to detect two magnetic field components in orthogonal directions respectively is disclosed. The magnetic-field angle sensor may comprise a pair of MTJ full-bridges or half-bridges interconnected with a semiconductor package lead. The magnetic-field angle sensor can be packaged into various low-cost standard semiconductor packages. | 2013-12-19 |
20130334635 | PIXEL STRUCTURE WITH REDUCED VACUUM REQUIREMENTS - A pixel structure, which may be used for infrared bolometers or other microelectromechanical systems (MEMS) devices, configured to increase immunity of the pixel to molecular heat transfer and reduce the vacuum requirements for a wafer level packaged device incorporating the pixel or an array thereof. In one example, the pixel has a perforated body or discontinuous surface structure. | 2013-12-19 |
20130334636 | BACK-ILLUMINATED IMAGE SENSOR AND FABRICATING METHOD THEREOF - A fabricating method of a back-illuminated image sensor includes the following steps. First, a silicon wafer having a first surface and a second surface is provided, wherein a number of trench isolations are formed in the first surface, and at least one image sensing member is formed between the trench isolations. Then, a first chemical mechanical polishing (CMP) process is performed to the second surface using the trench isolations as a polishing stop layer to thin the silicon wafer. Because the polishing rate of the silicon material in the silicon wafer is different with that of the isolation material of the trench isolations in the first CMP process, at least one dishing depression is formed in the second surface of the silicon wafer. Finally, a microlens is formed above the dishing depression, and a surface of the microlens facing the dishing depression is a curved surface. | 2013-12-19 |
20130334637 | CMOS SENSOR WITH BACKSIDE ILLUMINATION ELECTRONIC GLOBAL SHUTTER CONTROL - An apparatus comprising an image capture circuit and method for making the same. Electronic devices are formed on a first side of a substrate, each comprising a photo detector. A plurality of opaque shields are formed on a second side of the substrate corresponding to the electronic devices on the first side of the substrate and each directly opposite one of the electronic devices. | 2013-12-19 |
20130334638 | Apparatus and Method for Backside Illuminated Image Sensors - A backside illuminated image sensor comprises a photodiode and a first transistor located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads. | 2013-12-19 |
20130334639 | PHOTODIODE WITH REDUCED DEAD-LAYER REGION - A photodiode structure having an illuminated front-side surface and a back-side surface includes a front-side doped layer having a first conductivity type, a back-side doped layer having the first conductivity type, a front-side active cell region made sensitive to light by the action of at least one plug region formed in the front-side doped layer having a second conductivity type, and a front-side inactive cell region substantially insensitive to light, wherein the first and second conductivity types are opposite conductivity types. | 2013-12-19 |
20130334640 | IMAGE SENSOR, IMAGE PROCESSING DEVICE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME - An image sensor includes a dielectric layer including a reflector, a photo-electric conversion region on the dielectric layer, and a resonance layer on the photo-electric conversion region, the resonance layer including ribbed materials arranged in a concentric pattern. | 2013-12-19 |
20130334641 | SOLID-STATE IMAGE SENSOR, METHOD FOR MANUFACTURING THE SAME, AND CAMERA - A method for manufacturing a solid-state image sensor having a pixel region, a peripheral circuit region, and an intermediate region interposed between the pixel region and the peripheral circuit region, includes forming a high melting point metal compound in active regions of the peripheral circuit region and the intermediate region, forming an etch stop film on the high melting point metal compound formed in the active regions of the peripheral circuit region and the intermediate region, forming an interlayer insulating film on the etch stop film, and forming, by using the etch stop film, a contact plug to contact the high melting point metal compound in the active region of the peripheral circuit region. | 2013-12-19 |
20130334642 | SOLID-STATE IMAGING DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device includes photoelectric conversion elements on an imaging surface of a substrate, receiving light incident on a light receiving surface and performing photoelectric conversion to produce a signal charge. Electrodes are interposed between the photoelectric conversion elements and light blocking portions are provided above the electrodes and interposed between the photoelectric conversion elements. The light blocking portions include an electrode light blocking portion formed to cover the corresponding electrode, and a pixel isolation and light blocking portion protruding convexly from the upper surface of the electrode light blocking portion. The photoelectric conversion elements are arranged at first pitches on the imaging surface. The electrode light blocking portions and the pixel isolation and light blocking portions are arranged at second and third pitches on the imaging surface. At least the third pitch increases with distance from the center toward the periphery of the imaging surface. | 2013-12-19 |
20130334643 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - An image pickup apparatus includes a semiconductor chip including a light receiving section, a frame-like spacer arranged on the semiconductor chip to surround the light receiving section, a transparent flat plate section arranged on the semiconductor chip via the spacer and having a plan view dimension larger than a plan view dimension of the spacer and smaller than a plan view dimension of the semiconductor chip, and a reinforcing member for filling a gap between the semiconductor chip and the transparent flat plate section on the outer side of the spacer and having a plan view dimension larger than the plan view dimension of the transparent flat plate section and smaller than the plan view dimension of the semiconductor chip. | 2013-12-19 |
20130334644 | INTEGRATED PHOTODIODE FOR SEMICONDUCTOR SUBSTRATES - A substrate section that is at least partially fabricated to include contact elements and materials. The substrate section includes doped regions that have a heavily doped N-type region and a heavily doped P-type region adjacent to one another. An exterior surface of the substrate has a topography that includes a light-transparent region in which light, from a light source, is able to reach a surface of the substrate. An application of light onto the light transparent region is sufficient to cause a voltage potential to form across a junction of the heavily doped regions. The substrate section may further comprise one or more electrical contacts, positioned on the substrate section to conduct current, resulting from the voltage potential created with application of light onto the light transparent region, to a circuit on the semiconductor substrate. | 2013-12-19 |
20130334645 | FRONT SIDE IMPLANTED GUARD RING STRUCTURE FOR BACKSIDE - A method of forming a backside illuminated image sensor includes forming a guard ring structure of a predetermined depth in a front-side surface of a semiconductor substrate, the guard ring structure outlining a two-dimensional array of pixels, each pixel of the array of pixels separated from an adjacent pixel by the guard ring structure. The method further includes forming at least one image sensing element on the front-side surface of the semiconductor substrate, the at least one image sensing element being formed in a pixel of the array of pixels and surrounded by the guard ring structure. The method further includes reducing a thickness of the semiconductor substrate until the guard ring structure is co-planar with a back-side surface of the semiconductor substrate. | 2013-12-19 |
20130334646 | METALLIC THERMAL SENSOR FOR IC DEVICES - A thermal sensor for use in an IC device is formed of a plurality of metal resistor units connected in series where each of the plurality of metal resistor units are formed on different wiring layers of the IC device connected by via segments and the metal resistor units are in a superimposed alignment with each other forming a stack. | 2013-12-19 |
20130334647 | SEMICONDUCTOR DEVICE - A semiconductor device has a gate electrode including a leg part and a canopy part. A barrier layer is formed on a bottom face of the leg part of the gate electrode. In addition, on the lower surface of the barrier layer, a Schottky metal layer with an electrode width wider than the electrode width of the barrier layer is formed to have a Schottky junction with a semiconductor layer. | 2013-12-19 |
20130334648 | Methods and Apparatus for High Voltage Diodes - High voltage diodes are disclosed. A semiconductor device is provided having a P well region; an N well region adjacent to the P well region and forming a p-n junction with the P well region; a P+ region forming an anode at the upper surface of the semiconductor substrate in the P well region; an N+ region forming a cathode at the upper surface of the semiconductor substrate in the N well region; and an isolation structure formed over the upper surface of the semiconductor substrate between the anode and the cathode and electrically isolating the anode and cathode including a first dielectric layer overlying a portion of the upper surface of the semiconductor substrate, and a second dielectric layer overlying a portion of the first dielectric layer and a portion of the upper surface of the semiconductor substrate. Methods for forming the devices are disclosed. | 2013-12-19 |
20130334649 | SEMICONDUCTOR DEVICE HAVING VARIABLY LATERALLY DOPED ZONE WITH DECREASING CONCENTRATION FORMED IN THE TERMINATION REGION - In a semiconductor body, a semiconductor device has an active region with a vertical drift section of a first conduction type and a near-surface lateral well of a second, complementary conduction type. An edge region surrounding this active region comprises a variably laterally doped doping material zone (VLD zone). This VLD zone likewise has the second, complementary conduction type and adjoins the well. The concentration of doping material of the VLD zone decreases to the concentration of doping material of the drift section along the VLD zone towards a semiconductor chip edge. Between the lateral well and the VLD zone, a transitional region is provided which contains at least one zone of complementary doping located at a vertically lower point than the well in the semiconductor body. | 2013-12-19 |
20130334650 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 2013-12-19 |
20130334651 | DUAL SHALLOW TRENCH ISOLATION LINER FOR PREVENTING ELECTRICAL SHORTS - A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate. | 2013-12-19 |
20130334652 | NITRIDE SHALLOW TRENCH ISOLATION (STI) STRUCTURES - A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride. | 2013-12-19 |
20130334653 | Semiconductor Device with an Edge Termination Structure - A semiconductor device having a semiconductor die and an edge termination structure is provided. The semiconductor die includes an outer edge and an active area defining a main horizontal surface and being spaced apart from the outer edge. The edge termination structure includes at least one vertical trench having an insulated side wall forming, in a horizontal cross-section, an acute angle with the outer edge. The acute angle is lower than about 20°. | 2013-12-19 |
20130334654 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device including: a semiconductor substrate, an element isolating trench structure that includes an element isolating trench formed in one main surface of the semiconductor substrate, an insulating material that is formed within the element isolating trench, element formation regions that are surrounded by the element isolating trench, and semiconductor elements that are respectively formed in the element formation regions. The element isolating trench includes first element isolating trenches extending in a first direction, second element isolating trenches extending in a second direction that are at a right angle to the first direction, and third element isolating trenches extending in a third direction inclined at an angle θ (0°<θ<90°) from the first direction. | 2013-12-19 |
20130334655 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device including: a semiconductor substrate; first and second element isolating trenches that are formed in one main surface of the semiconductor substrate separately from each other; a first insulating material that is formed within the first element isolating trench; a plurality of first element formation regions that are surrounded by the first element isolating trench; first semiconductor elements that are respectively formed in the first element formation regions; a second insulating material that is formed within the second element isolating trench; a second element formation region that is surrounded by the second element isolating trench; a second semiconductor element that is formed in the second element formation region; and a stress relaxation structure that is formed between the first element isolating trench and the second element isolating trench. | 2013-12-19 |
20130334656 | ELECTRICAL INTERCONNECTION STRUCTURES INCLUDING STRESS BUFFER LAYERS - Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening. | 2013-12-19 |
20130334657 | PLANAR INTERDIGITATED CAPACITOR STRUCTURES AND METHODS OF FORMING THE SAME - A planar interdigitated capacitor structure, methods of forming, and devices including, the same. The device includes first and second planar electrode structures including respective first and second pluralities of planar continuous rectangular plate electrode elements formed above a semiconductor substrate and extending continuously in first and second orthogonal directions substantially parallel to a plane of the substrate, and first and second conductors interconnecting the respective first and second pluralities of planar electrode elements parallel to a third axis substantially normal to the plane of the substrate. The first and second planar electrode structures are arranged with respective continuous rectangular plate electrode elements of each planar electrode structure interleaved and substantially parallel with each other between the first and second conductors. The device also includes a dielectric material between the first planar electrode structure and the second planar electrode structure. | 2013-12-19 |
20130334658 | Method And System For Improved Matching For On-Chip Capacitors - Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern. | 2013-12-19 |
20130334659 | Multiple Depth Vias In An Integrated Circuit - An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias. | 2013-12-19 |
20130334660 | Capacitor Structure - One or more embodiments relate to a semiconductor device, comprising: a substrate; and a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias. | 2013-12-19 |
20130334661 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A two-layered polysilicon capacitive element is manufactured to enable suppression of both of an increase in the applied electric field dependence of the capacitance value and the initial defect of the dielectric film. Included are a lower electrode into which phosphorous ions are implanted, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film. The dielectric film includes a thermal oxide film formed by partially oxidizing a polysilicon film constituting the lower electrode and etching out its outer layer part, and a deposited oxide film formed on the thermal oxide film. | 2013-12-19 |
20130334662 | Current Sensing Using a Metal-on-Passivation Layer on an Integrated Circuit Die - A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor. | 2013-12-19 |
20130334663 | METAL-ON-PASSIVATION RESISTOR FOR CURRENT SENSING IN A CHIP-SCALE PACKAGE - A current sense resistor integrated with an integrated circuit die housed in a chip-scale semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are to be electrically connected to a first conductive electrode and a second conductive electrode external to the chip-scale semiconductor package where the first conductive electrode and the second conductive electrode are physically separated from each other by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second conductive electrodes. In some embodiments, a semiconductor device including an integrated circuit die housed in a chip-scale semiconductor package includes a current sense resistor formed in a metal layer formed over a passivation layer of the integrated circuit die. | 2013-12-19 |
20130334664 | INTERFACE CONTROL IN A BIPOLAR JUNCTION TRANSISTOR - Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer. | 2013-12-19 |
20130334665 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed with a protection device formed of a parasitic bipolar transistor, a parasitic diode and a parasitic resistance and operated at a lowered operating voltage to be capable of improving a blocking capability against an over voltage. The impurity concentration in a semiconductor layer as the base of a parasitic bipolar transistor is lower compared with the impurity concentration of a semiconductor layer of the same conduction type arranged adjacently to the semiconductor layer as the base and to be the anode of a parasitic diode. The lowered impurity concentration is determined to be the concentration for making the parasitic bipolar transistor have a snapback phenomenon occur. | 2013-12-19 |
20130334666 | Plasma-Assisted Atomic Layer Epitaxy of Cubic and Hexagonal InN and its alloys with AlN at Low Temperatures - Described herein is a method for growing indium nitride (InN) materials by growing hexagonal and/or cubic InN using a pulsed growth method at a temperature lower than 300° C. Also described is a material comprising InN in a face-centered cubic lattice crystalline structure having an NaCl type phase. | 2013-12-19 |
20130334667 | Alkaline Etching Liquid for Texturing a Silicon Wafer Surface - An etching liquid for texturing a silicon wafer surface is provided. The etching liquid may include an aqueous solution of at least one alkaline etching agent and at least one polysaccharide or derivative thereof. Also provided is a process for texture etching a silicon wafer using the etching liquid of the invention. | 2013-12-19 |
20130334668 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an integrated circuit device having a device contact surface, a device lateral side, and a device backside opposite the device contact surface; forming a device shell, having a shell lip, contiguous with the device backside and the device lateral side, the shell lip adjacent to and coplanar with the device contact surface; attaching a substrate to the integrated circuit device, the device shell between the integrated circuit device and the substrate; and forming an encapsulation on the substrate and covering the integrated circuit device and the device shell. | 2013-12-19 |
20130334669 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; an inter layer dielectric disposed on the substrate; a TSV penetrating the substrate and the ILD. In addition, a plurality of shallow trench isolations (STI) is disposed in the substrate, and a shield ring is disposed in the ILD surrounding the TSV on the STI. During the process of forming the TSV, the contact ring can protect adjacent components from metal contamination. | 2013-12-19 |
20130334670 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer. | 2013-12-19 |
20130334671 | SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREOF - A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound. | 2013-12-19 |
20130334672 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, semiconductor chips and lead frames are soldered at the same time on an insulating circuit board by one reflow soldering, and the positions of the externally led out lead frames undergo no change. In manufacturing the semiconductor device, after power semiconductor chips and control ICs are mounted on an insulating circuit board, and lead frames are disposed thereon, the semiconductor chips and lead frames are soldered at the same time on the insulating circuit board by one reflow soldering. Furthermore, after a primary bending work is carried out on the lead frames, and a terminal case is mounted over the insulating circuit board, a secondary bending work is carried out on the lead frames. | 2013-12-19 |
20130334673 | FLEXIBLE POWER MODULE SEMICONDUCTOR PACKAGES - Power module semiconductor packages that contain a flexible circuit board and methods for making such packages are described. The semiconductor package contain a flexible circuit board, a conductive film on a first portion of the upper surface of the flexible circuit board, a land pad on a second portion of the upper surface of the flexible circuit board, a heat sink on a portion of the bottom surface of the flexible circuit board, a passive component, a discrete device, or an IC device connected to a portion of the conductive film, and a lead of a lead frame connected to the land pad. These packages can have a high degree of design flexibility of the layout of the package and simpler routing designs, reducing the time to design the packages and reducing the costs of the packages. Other embodiments are also described. | 2013-12-19 |
20130334674 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TIEBAR-LESS DESIGN AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead. | 2013-12-19 |
20130334675 | PACKAGE STRUCTURE HAVING LATERAL CONNECTIONS - An embodiment of a packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor. Thus, well-established techniques for incorporating a lead frame or any other conductive system in a package may be applied in order to impart wireless lateral connectivity to packaged semiconductor devices in an electronic system. | 2013-12-19 |
20130334676 | SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - A semiconductor module is manufactured by bonding a resin case having a first opening through which surfaces of main circuit terminals and control terminals are exposed, onto a metal heat-dissipating substrate onto which is bonded, a conductive-patterned insulating substrate onto which are bonded, semiconductor chips, the main circuit terminals, and the control terminals; inserting into and attaching to a second opening formed on a side wall constituting a resin case, a resin body having a nut embedded therein to fix the main circuit terminals and the control terminals; and filling the resin case with a resin material. A side wall of the first opening is tapered toward the surface thereof; a tapered contact portion contacting the tapered side wall is disposed on the control terminal; and the resin body having the embedded nut fixes the control terminal having a one-footing structure that is an independent terminal. | 2013-12-19 |
20130334677 | Semiconductor Modules and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead. | 2013-12-19 |
20130334678 | DEVICE FOR SUPPORTING A SUBSTRATE, AS WELL AS METHODS FOR MANUFACTURING AND USING SUCH A DEVICE | 2013-12-19 |
20130334679 | METAL CONSERVATION WITH STRIPPER SOLUTIONS CONTAINING RESORCINOL - Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods. | 2013-12-19 |
20130334680 | WAFER LEVEL PACKAGES OF HIGH VOLTAGE UNITS FOR IMPLANTABLE MEDICAL DEVICES AND CORRESPONDING FABRICATION METHODS - A multi-chip modular wafer level package of a high voltage unit for an implantable cardiac defibrillator includes one or more high voltage (HV) component chips encapsulated with other components thereof in a polymer mold compound of a single reconstituted wafer, wherein all interconnect segments are preferably located on a single side of the wafer. To electrically couple a contact surface of each HV chip, located on a side of the chip opposite the interconnect side of the wafer, the reconstituted wafer may include conductive through polymer vias; alternately, either wire bonds or layers of conductive polymer are formed to couple the aforementioned contact surface to the corresponding interconnect, prior to encapsulation of the HV chips. In some cases one or more of the components encapsulated in the reconstituted wafer of the package are reconstituted chips. | 2013-12-19 |
20130334681 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate. | 2013-12-19 |
20130334682 | EMBEDDED PACKAGES INCLUDING A MULTI-LAYERED DIELECTRIC LAYER AND METHODS OF MANUFACTURING THE SAME - The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers. | 2013-12-19 |
20130334683 | ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURING THE SAME - An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip. | 2013-12-19 |
20130334684 | SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE - A substrate structure is provided, including a substrate body and a plurality of traces formed on a surface of the substrate body. At least one of the traces has an electrical contact formed in a groove thereof for electrically connecting an external element, thereby meeting the demands of fine line/fine pitch and miniaturization and improving the product yield. | 2013-12-19 |
20130334685 | EMBEDDED PACKAGES AND METHODS OF MANUFACTURING THE SAME - An embedded package that may be realized by surrounding a semiconductor chip (or a semiconductor die) in a package substrate. A semiconductor chip of an embedded package may be electrically connected to external connection terminals through interconnection wires instead of bumps, and the interconnection wires may be formed using a wire bonding process. A high reliability embedded package results. | 2013-12-19 |
20130334686 | CARRIER-FREE LAND GRID ARRAY IC CHIP PACKAGE AND PREPARATION METHOD THEREOF - A carrier-free land grid array (LGA) Integrated Circuit (IC) chip package and a preparation method thereof are provided. The IC chip package includes: an inner pin, an IC chip, a pad, a bonding wire, and a mold cap. The inner pin is designed to be a multi-row matrix form at a front side of the package, and is designed to be an exposed multi-row approximate square-shaped circular gold-plated contacts at a back side; the IC chip is provided on the inner pin, the inner pin is adhered to the IC chip with an adhesive film sheet, the pad on the IC chip is connected to the inner pin by the bonding wire, and the mold cap encircles the adhesive film sheet, the IC chip, the bonding wire, and edges of the inner pin, so as to form a whole circuit. The present invention adopts approximate square-shaped spherical array contacts, thereby having a simple and flexible structure, and achieving a desirable heat-dissipation effect. A cooper lead frame (L/F) has a high yield, and reduces the material cost. The L/F is used to replace a ceramic substrate, PCB substrate, or BT substrate, thereby saving the complicated layout design, shortening the designing and manufacturing cycle, accelerating the trial production course, and enabling the product to be early listed to obtain market opportunities. | 2013-12-19 |
20130334687 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and to which the first bonding portion is bonded. The lead includes a second bonding surface and a third bonding surface both facing to the first side in the first direction and forming an angle larger than 180° on the first side in the first direction. The semiconductor device further includes a ball bump extending onto both the second bonding surface and the third bonding surface. The second bonding portion is bonded to the lead via the ball bump. | 2013-12-19 |
20130334688 | MULTI-ELEMENTS-DOPED ZINC OXIDE FILM, MANUFACTURING METHOD AND APPLICATION THEREOF - The invention relates to the semiconductor material manufacturing technical field. A multi-elements-doped zinc oxide film as well as manufacturing method and application in photo-electric devices thereof are provided. The manufacturing method comprises the following steps: (1) mixing the powder of Ga | 2013-12-19 |
20130334689 | APPARATUS AND METHOD FOR LOW CONTACT RESISTANCE CARBON NANOTUBE INTERCONNECT - An apparatus comprises a first dielectric layer formed over a substrate, a first metal line embedded in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, a second metal line embedded in the second dielectric layer, an interconnect structure formed between the first metal line and the second metal line, a first carbon layer formed between the first metal line and the interconnect structure and a second carbon layer formed between the second metal line and the interconnect structure. | 2013-12-19 |
20130334690 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided. | 2013-12-19 |