51st week of 2013 patent applcation highlights part 15 |
Patent application number | Title | Published |
20130334491 | Methods for Forming Nickel Oxide Films for Use With Resistive Switching Memory Devices - Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH) | 2013-12-19 |
20130334492 | LIGHT RECEIVING ELEMENT AND OPTICAL DEVICE - A light-receiving element includes a III-V group compound semiconductor substrate, a light-receiving layer having a type II multi-quantum well structure disposed on the substrate, and a type I wavelength region reduction means for reducing light in a wavelength region of type I absorption in the type II multi-quantum well structure disposed on a light incident surface or between the light incident surface and the light-receiving layer. | 2013-12-19 |
20130334493 | SEMICONDUCTOR LIGHT EMITTING STRUCTURE - A semiconductor light emitting structure including an n-type semiconductor layer, a p-type semiconductor layer and an active layer is provided. The active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer is a multi-quantum well structure consisting of well layers and barrier layers interlaced and stacked to each other. The well layers near the n-type semiconductor layer at least include a first well layer having a first thickness, and the well layers near the p-type semiconductor layer at least include a second well layer having a second thickness smaller than the first thickness, so that the ability to restrict electrons within the area of the active layer near the n-type semiconductor layer is increased, and the conversion efficiency of the active layer is enhanced. There is a differential Δd | 2013-12-19 |
20130334494 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A solid-state imaging device includes a first electrode, a second electrode disposed opposing to the first electrode, and a photoelectric conversion layer, which is disposed between the first electrode and the second electrode and in which narrow gap semiconductor quantum dots are dispersed in a conductive layer, wherein one electrode of the first electrode and the second electrode is formed from a transparent electrode and the other electrode is formed from a metal electrode or a transparent electrode. | 2013-12-19 |
20130334495 | SUPERLATTICE STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A superlattice structure, and a semiconductor device including the same, include a plurality of pairs of layers are in a pattern repeated at least two times, in which a first layer and a second layer constitute a pair, the first layer is formed of Al | 2013-12-19 |
20130334496 | SEMICONDUCTOR DEVICE, SUPERLATTICE LAYER USED IN THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a silicon substrate; a nitride nucleation layer disposed on the silicon substrate; at least one superlattice layer disposed on the nitride nucleation layer; and at least one gallium nitride-based semiconductor layer disposed on the superlattice layer. The at least one superlattice layer includes a stack of complex layers, each complex layer including a first layer and a second layer such that each of the complex layers has a plurality of nitride semiconductor layers having different compositions, at least one of the plurality of nitride semiconductor layers having a different thickness based on a location of the at least one nitride semiconductor layer within the stack, and at least one stress control layer having a thickness greater than a critical thickness for pseudomorphic growth. | 2013-12-19 |
20130334497 | NANOWIRE EPITAXY ON A GRAPHITIC SUBSTRATE - A composition of matter comprising at least one nanowire on a graphitic substrate, said at least one nanowire having been grown epitaxially on said substrate, wherein said nanowire comprises at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group (IV) element. | 2013-12-19 |
20130334498 | TRANSPORT CONDUITS FOR CONTACTS TO GRAPHENE - An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart relative to one another on the substrate. The graphene layer comprises at least a first portion and a second portion, the first portion being in contact with the first source/drain region and the second portion being in contact with the second source/drain region. One or more cuts are formed in at least one of the first and second portions of the graphene layer. The apparatus allows for lowered contact resistance in graphene/metal contacts. | 2013-12-19 |
20130334499 | METHOD OF ISOLATING NANOWIRES FROM A SUBSTRATE - A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate. | 2013-12-19 |
20130334500 | TUNNEL FIELD EFFECT TRANSISTOR DEVICE AND METHOD FOR MAKING THE DEVICE - A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer. | 2013-12-19 |
20130334501 | Field-Effect P-N Junction - Embodiments described herein provide a field-effect p-n junction. In some embodiments, the field-effect p-n junction includes (1) an ohmic contact, (2) a semiconductor layer above the ohmic contact, (3) at least one rectifying contact above the semiconductor layer, where the lateral width of the rectifying contact is less than the semiconductor depletion width of the semiconductor layer, and (4) a gate above the rectifying contact. In some embodiments, the field-effect p-n junction includes (1) an ohmic contact, (2) a semiconductor layer above the ohmic contact, (3) a thin top contact above the semiconductor layer, where the out of plane thickness of the thin top contact is less than the Debye screening length of the thin top contact, and (4) a gate above the thin top contact. | 2013-12-19 |
20130334502 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a display panel and a method for manufacturing the same. The display panel comprises a substrate, pixels, active elements and storage capacitors, and the active elements and storage capacitors are disposed in the pixels. Each of the storage capacitors includes a first storage electrode and a second storage electrode, and the second storage electrode is disposed in a recess of an insulating layer and positioned to the first storage electrode. In the method for manufacturing the display panel, portions of the insulating layer are removed to form the recesses positioned to the first storage electrodes. The present invention can increase the aperture ratio of the pixels. | 2013-12-19 |
20130334503 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An organic light-emitting display apparatus includes a plurality of first emission units, each including a first organic light-emitting device configured to emit light in at least a first direction and through a first display surface, a plurality of second emission units, each including a second organic light-emitting device configured to emit in a second direction opposite to the first direction and through a second display surface. The first emission units and the second emission units are alternately disposed. The apparatus further includes a transmissive area disposed adjacent to but not overlapping with the plurality of first emission units and the plurality of second emission units when viewed from a direction perpendicular to the first display surface, and capable of transmitting external light through the first and second display surfaces in the transmissive area. | 2013-12-19 |
20130334504 | ORGANIC LIGHT EMITTING DIODE LIGHTING DEVICES - An organic light emitting diode (OLED) device includes a substrate, an anode, a cathode, an active region including an organic material, wherein the active region is electrically coupled to the anode and the cathode, at least one coupler configured to electrically couple at least one of the anode or the cathode to a power supply, and an encapsulation that isolates the active region from an ambient environment. A lighting system can be made including a plurality of OLED devices. A lighting system can be assembled using the OLED devices from a kit. The OLED devices may be polymer light emitting diode (PLED) devices or small molecule light emitting diode (SMOLED) devices. The OLED devices can use regio-regular poly-thiophene. | 2013-12-19 |
20130334505 | Polymers, Their Preparation and Uses - A polymer containing an optionally substituted repeat unit of formula (I) wherein each R is the same or different and represents H or an electron withdrawing group, and each R | 2013-12-19 |
20130334506 | ORGANIC ELECTROLUMINESCENT ELEMENT - It is an object of the present invention to provide an organic electroluminescent element with which no light extraction layer needs to be produced separately, which has a transparent electrode that is advantageous in terms of cost and a simple film formation process, and which is excellent from the standpoint of light extraction efficiency. The present invention provides an organic electroluminescent element in which a substrate, a first electrode adjacent to this substrate, an organic layer including at least one organic light-emitting layer, and a second electrode adjacent to this organic layer are formed in this order, with this organic electroluminescent element being such that at least one of the aforementioned electrodes is a transparent electrode which is transparent, which contains at least one type of light scattering particles that are transparent and that have a primary particle size of at least 0.5 μm, and which is composed of the aforementioned light scattering particles and a component having a refractive index equal to or higher than the refractive index of the aforementioned organic light-emitting layer. | 2013-12-19 |
20130334507 | Organic EL Light Emitting Device and Manufacturing Method Thereof - There is provided a layered color filter which can improve optical selectivity, without reducing optical transparency, an organic EL light emitting device on which such a layered color filter is mounted, and a fabrication method of such an organic EL light emitting device. The layered color filter includes a substrate | 2013-12-19 |
20130334508 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING AN ORGANIC LIGHT EMITTING DIODE DISPLAY - An OLED display is disclosed which included gate wires provided on a substrate and extended in a first direction, data wires provided on the gate wires and extended in a second direction that crosses the first direction; a pixel circuit including first thin film transistors respectively connected to the gate wires and the data wires; and an organic light emitting diode connected to the pixel circuit. The thin film transistor includes a first active layer provided on the substrate to connect the data wires and the organic light emitting diode, and includes a channel area, a source area, and a drain area. The source area and the drain area doped with an impurity and a first gate electrode is not doped with the impurity and provided on the first active layer, interposing sequentially layered first and second insulation layers therebetween. | 2013-12-19 |
20130334509 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE - Organic light-emitting display devices are provided. One organic light-emitting display device includes a substrate, a first wire on the substrate, a second wire insulated from and crossing the first wire, and a static electricity dispersion pattern insulated from and crossing the second wire. Another organic light-emitting display device includes: a substrate; a gate line and a data line on the substrate, insulated from and crossing each other; a dummy wire that is part of a same layer as one of the gate line or the data line, and having at least one end aligned with a sidewall of the substrate; a dummy intersection wire insulated from and crossing the dummy wire; and a static electricity dispersion pattern insulated from and crossing the dummy intersection wire. | 2013-12-19 |
20130334510 | ELECTRONIC DEVICES WITH IMPROVED SHELF LIVES - Embodiments of the present invention provide electronic devices such as OLEDs that have enhanced mechanical integrity and prolonged shelf, by minimizing the spread of a delamination region using topographical non-uniformities introduced in the device structure. For example, a device may be made deliberately non-planar by introducing multiple energy barriers which can prevent or minimize the propagation of a delamination, because the delamination will have to cross the energy barriers in order to spread to a larger area. | 2013-12-19 |
20130334511 | METHOD FOR DEPOSITION OF HIGH-PERFORMANCE COATINGS AND ENCAPSULATED ELECTRONIC DEVICES - A method is disclosed for forming leak-free coatings on polymeric or other surfaces that provide optical functions or protect underlying layers from exposure to oxygen and water vapor and do not crack or peel in outdoor environments. This method may include both cleaning and surface modification steps preceding coating. The combined method greatly reduces defects in any barrier layer and provides weatherability of coatings. Specific commercial applications that benefit from this include manufacturing of photovoltaic devices or organic light emitting diode devices (OLED) including lighting and displays. | 2013-12-19 |
20130334512 | ORGANIC ELECTROLUMINESCENT ELEMENT, COMPOSITION FOR ORGANIC ELECTROLUMINESCENT ELEMENT, AND ORGANIC ELECTROLUMINESCENT DEVICE - The present invention relates to an organic electroluminescent element which comprises two or more hole injection/transport layers each formed by a wet film formation method using a composition containing, as a hole-injecting/transporting compound, an arylamine polymer compound that has a repeating unit having a triarylamine structure therein, in which when the number of atoms present on the path which is the smallest in the number of atoms present thereon, of the paths which each connect the nonaromatic tertiary nitrogen atoms contained in any two triarylamine structures present in each polymer compound, is taken as N: the minimum number of atoms between nitrogen atoms in the compound, then the N in each hole injection/transport layer is in a specific state. | 2013-12-19 |
20130334513 | THIN-FILM TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING SAME, ORGANIC ELECTROLUMINESCENT DISPLAY ELEMENTS AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - A thin film transistor element is formed in each of a first aperture and a second aperture defined by partition walls, which further define a third aperture that is adjacent to the first aperture with a gap therebetween and is located in a direction, from the first aperture, differing from a direction of the second aperture. In plan view, at a bottom portion of the first aperture, a center of area of a liquid-philic layer portion is offset from a center of area of the bottom portion in a direction differing from a direction of the third aperture, and at a bottom portion of one of the first and second apertures, a center of area of a liquid-philic layer portion is offset from a center of area of the bottom portion in a direction differing from a direction of the other one of the first and second apertures. | 2013-12-19 |
20130334514 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes. | 2013-12-19 |
20130334515 | MASK ASSEMBLY AND ORGANIC LIGHT EMITTING DIODE DISPLAY MANUFACTURED USING THE SAME - A mask assembly includes a frame forming an opening, and a plurality of unit masks which form a plurality of deposition openings, the longitudinal ends of the unit masks being fixed to the frame. At least two adjacent ones of the plurality of unit masks have deposition recesses formed on both sides facing each other. The width of the deposition recesses along a width direction of the unit masks is equal to or greater than the width of the deposition openings along the width direction of the unit masks. | 2013-12-19 |
20130334516 | OPTOELECTRONIC COMPONENT HAVING DOPED LAYERS - The invention relates to an organic electronic or optoelectronic component, comprising an electrode and a counter-electrode and a layer system between the electrode and the counter-electrode, wherein the layer system contains at least one organic layer and at least one doped layer, wherein the dopant in the doped layer represents a stronger Lewis acid than antimony pentafluoride (SbF5) or a stronger Lewis base than 1,8-bis(dimethylamino)napthalene based on the calculation of fluoride ion affinity. | 2013-12-19 |
20130334517 | NOVEL COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE COMPRISING SAME - The present invention relates to a novel compound and an organic light emitting device comprising the same. The compound according to the present invention may be used as hole injection, hole transport, electron injection and transport, and light emitting materials in an organic light emitting device, and the organic light emitting device according to the present invention has excellent properties in terms of efficiency, driving voltage, and life-span. | 2013-12-19 |
20130334518 | COMPOUND AND ORGANIC ELECTRICAL ELEMENT USING SAME, AND ELECTRONIC DEVICE AND HEAT-RESISTANCE MEASURING METHOD THEREWITH - The present invention provides a diphenyl diamine derivative which is a combination of a nitrogen-containing diphenyl fluorenyl group and a spiro fluorenyl group; an organic electroluminescent device using the same; and a display apparatus which uses the organic electroluminescent device. | 2013-12-19 |
20130334519 | Organic Light-Emitting Component and Use of a Copper Complex in a Charge Transport Layer - An organic light-emitting component has an active layer for emitting electromagnetic radiation. It also has an anode and an organic charge transport layer, arranged between the active layer and the anode, for transporting charge carriers from the anode to the active layer. The anode can be used to decouple electromagnetic radiation emitted by the active layer from the organic light-emitting component. The organic charge transport layer comprises a copper complex which has at least one ligand with the chemical structure as per a formula I. | 2013-12-19 |
20130334520 | GERMOLE CONTAINING CONJUGATED MOLECULES AND POLYMERS - Embodiments of the invention are directed to Ge comprising heterocyclic compounds which can be used for the preparation of homopolymers and copolymers. The copolymers can be donor-acceptor (DA) alternating copolymers where the donor unit is a Ge comprising heterocyclic unit. The polymers can be used as materials in solar cells and other photovoltaic devices, transistors, diodes, light emitting devices (LEDs), conductors, supercapacitors, batteries, and electrochromic devices. | 2013-12-19 |
20130334521 | NOVEL ORGANOMETALLIC COMPOUND, AND ORGANIC LIGHT-EMITTING DIODE USING SAME - The present invention relates to a novel organometallic compound, and more particularly, to a luminescent organometallic compound in which intermolecular interaction is inhibited by means of introducing a germanium substituent, thereby improving light-emitting characteristics. The present invention also relates to an organic electronic device, specifically, to an organic light-emitting diode using the compound. According to the present invention, a germanium substituent is introduced to the parent organometallic iridium compound, thus inhibiting an intermolecular interaction in the solid state and enabling the compound of the present invention to be effectively used in solution processing. When the compound of the present invention is used as part of a light-emitting layer of an organic light-emitting diode, the light-emitting efficiency of the light-emitting diode may be significantly improved. Therefore, the compound of the present invention may be effectively used as a material for an organic light-emitting diode. | 2013-12-19 |
20130334522 | METHOD OF FABRICATING OXIDE THIN FILM DEVICE USING LASER LIFT-OFF AND OXIDE THIN FILM DEVICE FABRICATED BY THE SAME - Provided is a method of fabricating an oxide thin film device using laser lift-off and an oxide thin film device fabricated by the same. The method includes: forming an oxide thin film on a growth substrate; bonding a temporary substrate on the oxide thin film; irradiating laser onto the growth substrate to separate the oxide thin film on which the temporary substrate has been bonded from the growth substrate; bonding a device substrate on the oxide thin film on which the temporary substrate has been bonded; and forming an upper electrode film on the oxide thin film. Therefore, it is possible to overcome problems caused by a defective layer by transferring an oxide thin film transferred on a polymer-based temporary substrate onto a device substrate, without using an interface on which a defective layer formed due to oxygen diffusion upon laser lift-off is formed. | 2013-12-19 |
20130334523 | SEMICONDUCTOR DEVICE - High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed. | 2013-12-19 |
20130334524 | DISPLAY DEVICE AND MANUFACTURING METHOD FOR SAME - The present invention provides a display device having: gate electrodes formed on a transparent substrate; a gate insulating film for covering the gate electrodes; an oxide semiconductor formed on the gate insulating film; drain electrodes and source electrodes formed at a distance from each other with channel regions of the oxide semiconductor in between; an interlayer capacitor film for covering the drain electrodes and source electrodes; common electrodes formed on top of the interlayer capacitor film; and pixel electrodes formed so as to face the common electrodes, and wherein an etching stopper layer for covering the channel regions is formed between the oxide semiconductor and the drain electrodes and source electrodes, the drain electrodes are a multilayer film where a transparent conductive film and a metal film are layered on top of each other, and the drain electrodes and source electrodes make direct contact with the oxide semiconductor. | 2013-12-19 |
20130334525 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver circuit are provided over the same substrate, manufacturing cost can be reduced. | 2013-12-19 |
20130334526 | THIN FILM TRANSISTOR - A thin film transistor includes a gate electrode formed on a substrate; a gate insulation film covering the gate electrode; an oxide semiconductor layer formed on the gate insulation film; a source electrode and a drain electrode covering an edge portion of the oxide semiconductor layer, and a passivation film covering the source electrode, the drain electrodes, and the oxide semiconductor layer. The passivation film is made of an insulating material, and the insulating material is capable of attenuating a light of wavelength not greater than 450 nm. | 2013-12-19 |
20130334527 | SEMICONDUCTOR DEVICE - One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal. | 2013-12-19 |
20130334528 | SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR THE SAME, AND DISPLAY APPARATUS - A semiconductor device including a semiconductor layer, a plurality of electrode portions each overlapping the semiconductor layer, and an insulating film placed between the plurality of electrode portions to lie on the semiconductor layer is fabricated. The fabrication method includes the steps of: forming an oxide semiconductor layer part of which is covered with the insulating film; forming a conductive material layer to cover the oxide semiconductor layer and the insulating film; forming the plurality of electrode portions from the conductive material layer by photolithography and plasma dry etching, to expose part of the oxide semiconductor layer from the plurality of electrode portions and the insulating film; and removing the part of the oxide semiconductor layer exposed from the plurality of electrode portions and the insulating film to form the semiconductor layer. | 2013-12-19 |
20130334529 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad. | 2013-12-19 |
20130334530 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE - The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor. | 2013-12-19 |
20130334531 | SYSTEMS AND METHODS FOR MEASURING TEMPERATURE AND CURRENT IN INTEGRATED CIRCUIT DEVICES - Embodiments relate to measurement of temperature and current in semiconductor devices. In particular, embodiments relate to monolithic semiconductor, such as power semiconductor, and sensor, such as a current or temperature sensor, device. In embodiments, temperature and/or current sensing features are monolithically integrated within semiconductor devices. These embodiments thereby can provide direct measurement of temperature and current, in contrast with conventional solutions that provide temperature and current sensing near or alongside but not integrated within the actual semiconductor device. For example, in one embodiment an additional layer structure is applied to a power semiconductor stack in backend processing. This monolithic integration provides for localized measurement of temperature and/or current, an advantage over conventional side-by-side configurations. | 2013-12-19 |
20130334532 | STRESS GAUGE COMPRISED OF A PIEZOELECTRIC MATERIAL FOR USE WITH INTEGRATED CIRCUIT PRODUCTS - In one example, a stress gauge for an integrated circuit product is disclosed that includes a layer of insulating material, a body positioned at least partially in the layer of insulating material, wherein the body is comprised of a material having a piezoelectric constant of at least about 0.1 pm/V, and a plurality of spaced apart conductive contacts, each of which is conductively coupled to the body. | 2013-12-19 |
20130334533 | SEMICONDUCTOR DEVICE - A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity. | 2013-12-19 |
20130334534 | LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display which includes a first substrate having thin film transistors, and a second substrate disposed to face the first substrate, wherein the first substrate includes: a gate electrode, a source electrode, and a drain electrode; a gate wiring; a first insulating film formed on the gate electrode and the gate wiring; a source wiring; a pixel electrode that is formed on the drain electrode to partially overlap the drain electrode; a second insulating film that covers the pixel electrode; a counter electrode; and a side wall that is formed on side portions of the source wiring, the source electrode, and the drain electrode, the third insulating film made of third insulating film; and wherein at least a part of the pixel electrode is formed to directly overlap the drain electrode and the side wall formed on the side portion of the drain electrode. | 2013-12-19 |
20130334535 | Semiconductor Device, Display Device, And Electronic Device - A display device includes a load, a transistor for controlling a current value supplied to the load, a capacitor, a first wiring, a second wiring, and first to fourth switches. Variations in the current value caused by variations in the threshold voltage of the transistor can be suppressed through the steps of: (1) holding the threshold voltage of the transistor in the storage capacitor, (2) inputting a potential in accordance with a video signal, and (3) holding a voltage that is the sum of the threshold voltage and the potential in accordance with the video signal, in the storage capacitor. Accordingly, a desired current can be supplied to the load such as a light emitting element. | 2013-12-19 |
20130334536 | SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx - A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° C. The rare earth metal forms a layer of rare earth silicide on the substrate. A first layer of rare earth oxide is deposited on the layer of rare earth silicide with a structure and lattice constant substantially similar to the substrate. The structure is annealed in an oxygen ambience to transform the layer of rare earth silicide to a layer of amorphous silicon and an intermediate layer of rare earth oxide between the substrate and the first layer of rare earth oxide. | 2013-12-19 |
20130334537 | Optically Controlled Power Devices - An electro-optically triggered power switch is disclosed utilizing a wide bandgap, high purity III-nitride semiconductor material such as BN, AN, GaN, InN and their compounds. The device is electro-optically triggered using a laser diode operating at a wavelength of 10 to 50 nanometers off the material's bandgap, and at a power level of 10 to 100 times less than that required in a conventionally triggered device. The disclosed device may be configured as a high power RF MOSFET, IGBT, FET, or HEMT that can be electro-optically controlled using photons rather than an electrical signal. Electro-optic control lowers the power losses in the semiconductor device, decreases the turn-on time, and simplifies the drive signal requirements. It also allows the power devices to be operated from the millisecond to the sub-picosecond timeframe, thus allowing the power device to be operated at RF frequencies (i.e., kilohertz to terahertz range) and at high temperatures where the bandgap changes with temperature. | 2013-12-19 |
20130334538 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE AND METHOD - Embodiments of the present disclosure describe structural configurations of an integrated circuit (IC) device such as a high electron mobility transistor (HEMT) switch device and method of fabrication. The IC device includes a buffer layer formed on a substrate, a channel layer formed on the buffer layer to provide a pathway for current flow in a transistor device, a spacer layer formed on the channel layer, a barrier layer formed on the spacer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) or gallium (Ga), a gate dielectric directly coupled with the spacer layer or the channel layer, and a gate formed on the gate dielectric, the gate being directly coupled with the gate dielectric. Other embodiments may also be described and/or claimed. | 2013-12-19 |
20130334539 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, and an inorganic film. The semiconductor layer includes a first surface having an unevenness, a second surface opposite to the first surface, and a light emitting layer. The semiconductor layer includes gallium nitride. The inorganic film is provided to conform to the unevenness of the first surface and in contact with the first surface. The inorganic film has main components of silicon and nitrogen. The inorganic film has a refractive index between a refractive index of the gallium nitride and a refractive index of air. An unevenness is formed also in a surface of the inorganic film. | 2013-12-19 |
20130334540 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first electrode, an intrinsic first compound semiconductor layer over the first electrode, a second compound semiconductor layer whose band gap is smaller than that of the first compound semiconductor layer on the first compound semiconductor layer, and a second electrode over the second compound semiconductor layer are provided. | 2013-12-19 |
20130334541 | THREE DIMENSIONAL STRAINED SEMICONDUCTORS - In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure. | 2013-12-19 |
20130334542 | NORMALLY-OFF POWER JFET AND MANUFACTURING METHOD THEREOF - In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times. | 2013-12-19 |
20130334543 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a display panel, a gate driver, and a data driver. The display panel includes a display area in which an image is displayed and a non-display area disposed adjacent to the display area. The display panel includes an insulating substrate which has a groove. The gate driver is disposed to overlap with the display area when viewed in a plan view. At least part of the gate driver is formed on the groove. | 2013-12-19 |
20130334544 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT, METHOD FOR PRODUCING SAME AND USE OF SUCH A COMPONENT - An opto-electronic component includes a housing, a radiation-emitting semiconductor chip and a radiation-detecting semiconductor chip. A first cavity and a second cavity are formed in the housing, wherein the radiation-emitting semiconductor chip is arranged in the first cavity and is cast by means of a first casting compound. The radiation-detecting semiconductor chip is arranged in the second cavity and cast by means of a second casting compound, wherein absorber particles are embedded in the second casting compound which are suitable for at least partially absorbing the radiation emitted by the radiation-emitting semiconductor chip. | 2013-12-19 |
20130334545 | Surface light source and display device - The present invention provide a surface light source, wherein, the surface light source comprises a LED light source, the diffusion plate and condenser plant. The diffusion plate has a phosphor, and the diffusion plate and the LED light source are disposed separately to form a heat dissipation space. The condenser device disposes between the LED light source and the diffuser plate for converging the light emitted from LED light source to the diffusion plate. | 2013-12-19 |
20130334546 | NOVEL ILLUMINATION DEVICES - Illumination device comprising at least one LED and at least one colour converter comprising at least one organic fluorescent colorant in a matrix consisting essentially of polystyrene or polycarbonate, wherein LED and colour converter are present in a remote phosphor arrangement. | 2013-12-19 |
20130334547 | LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE USING SAME - A light-emitting element includes a reflective electrode, a light-transmitting electrode disposed opposite the reflective electrode, a light-emitting layer emitting blue light disposed between the reflective electrode and the light-transmitting electrode, and a functional layer disposed between the reflective electrode and the light-emitting layer. The optical thickness of the functional layer is no less than 428.9 nm and no more than 449.3 nm. | 2013-12-19 |
20130334548 | LIGHT EMITTING DEVICES AND METHODS - Light emitting devices and methods are disclosed. In one embodiment a light emitting device can include a submount and a plurality of light emitting diodes (LEDs) disposed over the submount. At least a portion of the submount can include a reflective layer at least partially disposed below a solder mask. One or more layers within the submount may include one or more holes, a rough surface texture, or combinations thereof to improve adhesion within the device. The device can further include a retention material dispensed about the plurality of LEDs. Devices and methods are disclosed for improved solder mask adhesion. | 2013-12-19 |
20130334549 | LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND PACKAGE ARRAY - In a light emitting device, a first lead has a first terminal part that is contiguous with a first connector. The first terminal part includes a first convex part that is exposed from a molded article at the inner peripheral face of a mounting recess, and a first concave part that is formed in the rear face of the first convex part. | 2013-12-19 |
20130334550 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND ILLUMINATION SYSTEM - A light emitting device is provided. The light emitting device includes a first semiconductor layer, an uneven part on the first semiconductor layer, a first nonconductive layer including a plurality of clusters on the uneven part, a first substrate layer on the nonconductive layer, and a light emitting structure layer. The light emitting structure layer includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer on the first substrate layer. | 2013-12-19 |
20130334551 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device comprising: a substrate having a first surface and a second surface, wherein the second surface is opposite to the first surface; a semiconductor structure formed on the first surface of the substrate, comprising a first type semiconductor layer, an active layer and a second type semiconductor layer; and an isolation region separating at least the active layer into a first part and a second part, wherein the first part is capable of generating the electromagnetic radiation, and the second part comprises a breakdown diode. | 2013-12-19 |
20130334552 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND LIGHT EMITTING DEVICE - A semiconductor light emitting element includes a light emitting structure including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer. A first electrode structure includes a conductive via connected to the first conductivity type semiconductor layer. A second electrode structure is connected to the second conductivity type semiconductor layer. An insulating part having an open region exposes part of the first and second electrode structures while covering the first and second electrode structures. First and second pad electrodes are formed on the first and second electrode structures exposed by the open region and are connected to the first and second electrode structures. | 2013-12-19 |
20130334553 | Light Emitting Diode Package Structure And Manufacturing Method Thereof - Various examples of a light emitting diode (LED) package structure and a manufacturing method thereof are described. In one aspect, a LED package structure includes a carrier, a LED chip, a first annular barricade, a second annular barricade and a fluorescent encapsulant. The LED chip is electrically connected to the carrier. The first annular barricade and the second annular barricade are disposed around the LED chip, with the second annular barricade disposed between the LED chip and the first annular barricade. The fluorescent encapsulant is disposed on the carrier and at least covers the LED chip and the second annular barricade. The fluorescent encapsulant includes at least a type of phosphor and at least a type of gel with the phosphor distributed over a surface of the LED chip. | 2013-12-19 |
20130334554 | LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE SAME - Embodiments of a light emitting device and a method for fabricating the same are provided. The light emitting device comprises a cavity and one or more light emitting elements. The cavity is formed to a depth of 450 μm or less, and the light emitting elements are installed in the cavity. A fabricating method includes forming a package body having a cavity with a depth of 250 μm to 450 μm and at least one lead frame disposed at the bottom surface of the cavity, mounting at least one light emitting element on the lead frame, and molding a molding member in the cavity. | 2013-12-19 |
20130334555 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprising: a substrate; and a transition stack formed on the substrate comprising one first transition layer formed on the substrate having a first hollow component formed inside the first transition layer and a second transition layer formed on the first transition layer having a second hollow component formed inside the second transition layer wherein the first hollow component and the second hollow component having a volume respectively, and the volume of the first hollow component is different with the second hollow component and the material of the transition stack comprises at least two element. | 2013-12-19 |
20130334556 | LIGHT EMITTING DEVICE AND LIGHT UNIT HAVING THE SAME - Provided are a light emitting device and a light unit including the same. The light emitting device includes a body, a first cavity disposed at a center of the body, the first cavity having an opened upper side, a second cavity disposed around an upper portion of the body, the second cavity being spaced from the first cavity, first and second lead electrodes disposed within the first cavity, a light emitting chip disposed on at least one of the first and second lead electrodes, and a first molding member in the first cavity. The second cavity has an upper width grater than a lower width thereof and a side surface of the second cavity is formed of a vertical side surface with respect to a top surface of the body. | 2013-12-19 |
20130334557 | COMPOSITION CONTAINING QUANTUM DOT FLUORESCENT BODY, MOLDED BODY OF QUANTUM DOT FLUORESCENT BODY DISPERSION RESIN, STRUCTURE CONTAINING QUANTUM DOT FLUORESCENT BODY, LIGHT-EMITTING DEVICE, ELECTRONIC APPARATUS, MECHANICAL DEVICE, AND METHOD FOR PRODUCING MOLDED BODY OF QUANTUM DOT FLUORESCENT BODY DISPERSION RESIN - Provided are a composition that contains a quantum dot fluorescent body and that is able to suppress quenching of the quantum dot fluorescent body, a molded body of a quantum dot fluorescent body dispersion resin, a structure containing a quantum dot fluorescent body, a light-emitting device, an electronic apparatus, or a mechanical device, and a method for producing the molded body of a quantum dot fluorescent body dispersion resin. | 2013-12-19 |
20130334558 | METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT, AND OPTOELECTRONIC COMPONENT - A method of producing an optoelectronic component includes providing a cavity; introducing a liquid matrix material with phosphor particles distributed therein into the cavity; introducing a semiconductor chip into the matrix material; sedimenting the phosphor particles in the matrix material; and curing the matrix material, wherein a conversion layer including phosphor particles is produced, said conversion layer being arranged on the semiconductor chip. | 2013-12-19 |
20130334559 | LIGHT EMITTING MODULE, A LAMP, A LUMINAIRE AND A DISPLAY DEVICE - A light emitting module | 2013-12-19 |
20130334560 | LIGHT EMITTING DIODE CHIP - The present invention relates to a light-emitting diode chip. According to the present invention, the light-emitting diode chip comprises: a substrate, the thickness of which is greater than 120 μm; and a light-emitting diode provided on the surface of the substrate, at one side thereof. | 2013-12-19 |
20130334561 | METHOD FOR BONDING LED WAFER, METHOD FOR MANUFACTURING LED CHIP AND BONDING STRUCTURE - A method for bonding an LED wafer, a method for manufacturing an LED chip, and a bonding structure are provided. The method for bonding an LED wafer includes the following steps. A first metal film is formed on an LED wafer. A second metal film is formed on a substrate. A bonding material layer whose melting point is lower than or equal to about 110° C. is formed on the surface of the first metal film. The LED wafer is placed on the substrate. The bonding material layer is heated at a pre-solid reaction temperature for a pre-solid time to perform a pre-solid reaction. The bonding material layer is heated at a diffusion reaction temperature for a diffusing time to perform a diffusion reaction, wherein the melting points of the first and the second inter-metallic layers after diffusion reaction are higher than about 110° C. | 2013-12-19 |
20130334562 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process. | 2013-12-19 |
20130334563 | LED HAVING VERTICAL CONTACTS REDISTRUTED FOR FLIP CHIP MOUNTING - A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-Type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described. | 2013-12-19 |
20130334564 | MONOLITHIC COMPOUND SEMICONDUCTOR STRUCTURE - A monolithic compound semiconductor structure is disclosed. The monolithic compound semiconductor structure comprises a substrate, an n-type FET epitaxial structure, an n-type etching-stop layer, a p-type insertion layer, and an npn HBT epitaxial structure, and it can be used to form an FET, an HBT, or a thyristor. | 2013-12-19 |
20130334565 | Method of Manufacturing a Semiconductor Device Using an Impurity Source Containing a Metallic Recombination Element and Semiconductor Device - Source zones of a first conductivity type and body zones of a second conductivity type are formed in a semiconductor die. The source zones directly adjoin a first surface of the semiconductor die. A dielectric layer adjoins the first surface. Polysilicon plugs extend through the dielectric layer and are electrically connected to the source and the body zones. An impurity source containing at least one metallic recombination element is provided in contact with deposited polycrystalline silicon material forming the polysilicon plugs and distant to the semiconductor die. Atoms of the metallic recombination element, for example platinum atoms, may be diffused out from the impurity source into the semiconductor die to reliably reduce the reverse recovery charge. | 2013-12-19 |
20130334566 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A POWER SEMICONDUCTOR DEVICE - An insulated gate bipolar device is disclosed which can include layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness t | 2013-12-19 |
20130334567 | SEMICONDUCTOR DEVICE HAVING DIODE-BUILT-IN IGBT AND SEMICONDUCTOR DEVICE HAVING DIODE-BUILT-IN DMOS - A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode. | 2013-12-19 |
20130334568 | MULTILAYER SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A multilayer substrate structure comprises a substrate, a thermal matching layer formed on the substrate and a lattice matching layer above the thermal matching layer. The thermal matching layer includes at least one of molybdenum, molybdenum-copper, mullite, sapphire, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides, and rare earth oxides. The lattice matching layer includes a first chemical element and a second chemical element to form an alloy. The first and second chemical element has similar crystal structures and chemical properties. The coefficient of thermal expansion of the thermal matching layer and the lattice parameter of the lattice matching layer are both approximately equal to that of a member of group III-V compound semiconductors. The lattice constant of the lattice matching layer is approximately equal to that of a member of group III-V compound semiconductor. | 2013-12-19 |
20130334569 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACUTRING THE SAME - A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region. | 2013-12-19 |
20130334570 | INTEGRATED STRUCTURE OF COMPOUND SEMICONDUCTOR DEVICES - An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET. | 2013-12-19 |
20130334571 | EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM - A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate. | 2013-12-19 |
20130334572 | JUNCTIONLESS ACCUMULATION-MODE DEVICES ON DECOUPLED PROMINENT ARCHITECTURES - A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy. | 2013-12-19 |
20130334573 | Multi-Channel HEMT - A transistor device includes a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure. The 2DEGs form current channels of the transistor device. The transistor device further includes a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, and a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels. The transistor device also includes a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material. | 2013-12-19 |
20130334574 | Monolithic Integrated Composite Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench. | 2013-12-19 |
20130334575 | Damascene Word Line - The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures. | 2013-12-19 |
20130334576 | Gate array architecture with multiple programmable regions - An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces attic upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit. | 2013-12-19 |
20130334577 | Image Sensors Having Reduced Dark Level Differences - An image sensor including a semiconductor layer including a plurality of unit pixels each including a photoelectric conversion device and read devices; and an insulating layer including a light-shielding pattern defining a light-receiving region and a light-shielding region of the semiconductor layer, the insulating layer covering one surface of the semiconductor layer. The semiconductor layer further includes a potential drain region formed adjacent to an interface between the semiconductor layer and an insulating layer in the light-shielding region, wherein electrons generated due to defects occurring at the interface are accumulated in the potential drain region. At least one of the unit pixels in the light-shielding region provides a drain path for draining the electrons accumulated in the potential drain region. | 2013-12-19 |
20130334578 | MOLECULE SENSOR DEVICE - A molecule sensor included in a molecule sensor device has a semiconductor substrate, a bottom gate, a source portion, a drain portion, and a nano-scale semiconductor wire. The bottom gate is for example a poly-silicon layer formed on the semiconductor substrate and electrically insulated from the semiconductor substrate. The source portion is formed on the semiconductor substrate and insulated from the semiconductor substrate. The drain portion is formed on the semiconductor substrate and insulated from the semiconductor substrate. The nano-scale semiconductor wire is connected between the source portion and the drain portion, formed on the bottom gate, insulated from the bottom gate, and has a decoration layer thereon for capturing a molecular. The source portion, drain portion, and nano-wire semiconductor wire are for example another poly-silicon layer. The bottom gate receives a specified voltage to change an amount of surface charge carriers of the nano-scale semiconductor wire. | 2013-12-19 |
20130334579 | MANUFACTURING METHOD OF A GRAPHENE-BASED ELECTROCHEMICAL SENSOR, AND ELECTROCHEMICAL SENSOR - A manufacturing method of an electrochemical sensor comprises forming a graphene layer on a donor substrate, laminating a film of dry photoresist on the graphene layer, removing the donor substrate to obtain an intermediate structure comprising the film of dry photoresist and the graphene layer, and laminating the intermediate structure onto a final substrate with the graphene layer in electrical contact with first and second electrodes positioned on the final substrate. The film of dry photoresist is then patterned to form a microfluidic structure on the graphene layer and an additional dry photoresist layer is laminated over the structure. In one type of sensor manufactured by this process, the graphene layer acts as a channel region of a field-effect transistor, whose conductive properties vary according to characteristics of an analyte introduced into the microfluidic structure. | 2013-12-19 |
20130334580 | REPLACEMENT METAL GATE PROCESSING WITH REDUCED INTERLEVEL DIELECTRIC LAYER ETCH RATE - A semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer. | 2013-12-19 |
20130334581 | Device with MOS Device Including a Secondary Metal and PVD Tool with Target for Making Same - A device includes a substrate and a metal-oxide-semiconductor (MOS) device. The MOS device includes a gate dielectric over the substrate, a gate electrode over the gate dielectric, a source/drain region adjacent the gate dielectric, and a source/drain silicide over and contacting the source/drain region. The source/drain silicide comprises silicon, nickel, and a secondary metal. A ratio of a volume percentage of the secondary metal to a volume percentage of the silicon in the source/drain silicide is between about 0.005 and about 0.1. The secondary metal has a density between about 5,000 kg/m | 2013-12-19 |
20130334582 | DRAM DEVICE - A DRAM device includes plural N-channel MIS transistors arranged in a matrix over a P well, and a plurality of capacitors formed corresponding to the plurality of N-channel MIS transistors, and plural word lines formed corresponding to each row of the plurality of N-channel MIS transistors, and a plurality of bit lines formed corresponding to each column of the plurality of N-channel MIS transistors, and a P | 2013-12-19 |
20130334583 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL TRANSISTORS, ELECTRONIC SYSTEMS INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME - The semiconductor device includes word lines on a semiconductor substrate, common gates connected to each of the word lines and vertically disposed in the semiconductor substrate, buried bit lines intersecting the word lines at a non-right angle in a plan view, and a pair of vertical transistors sharing each of the common gates. The pair of vertical transistors is disposed on both sides of one of the word lines. Further, the pair of vertical transistors is electrically connected to the two adjacent buried bit lines. Electronic systems including the semiconductor device and related methods are also provided. | 2013-12-19 |
20130334584 | INTEGRATION OF MEMORY, HIGH VOLTAGE AND LOGIC DEVICES - A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (T | 2013-12-19 |
20130334585 | SEMICONDUCTOR DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns. | 2013-12-19 |
20130334586 | NON-SELF-ALIGNED NON-VOLATILE MEMORY STRUCTURE - A non-self-aligned non-volatile memory structure, comprising: a semiconductor substrate; a left floating gate memory cell and a right floating gate memory cell; a control gate; and a gate insulation layer disposed among said two floating gate memory cells and said control gate. Drains of said two floating gate memory cells are connected to different voltage levels. Said control gate is over said two floating gate memory cells, to cover said floating gates of said two floating gate memory cells, so as to control said two floating gates simultaneously. Said non-self-aligned non-volatile memory structure mentioned above does not require line-to-line alignment of gates, thus reducing significantly the complexity of manufacturing process, and number of layers of photo masks required, in achieving production cost reduction. | 2013-12-19 |
20130334587 | Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory - High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction. | 2013-12-19 |
20130334588 | FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure. | 2013-12-19 |
20130334589 | Semiconductor device and method of manufacturing the same - In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates. | 2013-12-19 |
20130334590 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a foundation structure, a first insulating film, and a second insulating film. The foundation structure is provided on the substrate. The foundation structure includes a plurality of circuit components and a gap provided between the circuit components. The first insulating film is provided on the foundation structure. The second insulating film is provided on the first insulating film. A Young's modulus of the second insulating film is lower than a Young's modulus of the first insulating film and a Young's modulus of a silicon oxide film. | 2013-12-19 |