51st week of 2008 patent applcation highlights part 42 |
Patent application number | Title | Published |
20080311659 | RIBONUCLEIC ACID INTERFERENCE MOLECULES OF ORYZA SATIVA - Sequences of ribonucleic acid interference molecules are provided. For example, in one aspect, at least one nucleic acid molecule comprising at least one of one or more precursor sequences having SEQ_ID NO: 1 through SEQ_ID NO: 11,928 and one or more corresponding mature sequences having SEQ_ID NO: 11,929 through SEQ_ID NO: 24,555 is provided. Techniques are also provided for regulating gene expression. | 2008-12-18 |
20080311660 | Dry powder cell culture products and methods of production thereof - The present invention relates to nutritive medium, medium supplement, media subgroup and buffer formulations. The present invention provides powder nutritive medium, medium supplement and medium subgroup formulations, e.g., cell culture medium supplements (including powdered sera such as powdered fetal bovine serum (FBS)), medium subgroup formulations and cell culture media comprising all of the necessary nutritive factors that facilitate the in vitro cultivation of cells. The invention further provides powder buffer formulations that produce particular ionic and pH conditions upon reconstitution with a solvent. The invention provides methods for production of media, media supplement, media subgroup and buffer formulations, and also provides kits and methods for cultivation of prokaryotic and eukaryotic cells, particularly bacterial cells, yeast cells, plant cells and animal cells (including human cells) using these dry powder nutritive media, media supplement, media subgroup and buffer formulations. | 2008-12-18 |
20080311661 | RIBONUCLEIC ACID INTERFERENCE MOLECULES OF ARABIDOPSIS THALIANA - Sequences of ribonucleic acid interference molecules are provided. For example, in one aspect, at least one nucleic acid molecule comprising at least one of one or more precursor sequences having SEQ_ID NO: 1 through SEQ_ID NO: 3,197 and one or more corresponding mature sequences having SEQ_ID NO: 3,198 through SEQ_ID NO: 6,565 is provided. Techniques are also provided for regulating gene expression. | 2008-12-18 |
20080311662 | Method for Analyzing Oligomeric Proanthocyanidin (Opc) - The present invention provides a novel method for assaying OPC contained in natural substances, foods and beverages, pharmaceuticals and/or cosmetics. | 2008-12-18 |
20080311663 | Gas Analyzer Apparatus and Method of Analyzing Gases - A gas analyzer apparatus includes a device or platform for supporting a predetermined quantity of a reagent capable of reacting with a predetermined gas to cause a detectable change in a characteristic of the reagent, a reservoir adapted to retain the reagent, a dispenser for dispensing a controlled quantity of the reagent from the reservoir to a predetermined position on the device for supporting the predetermined quantity of the reagent, and a detector that detects the presence of the predetermined gas upon the predetermined gas and the controlled quantity of reagent reacting to cause a detectable change in a characteristic of the reagent detectable by the detector, the detector adapted to detect a change in the controlled quantity of the reagent by detecting the change in the characteristic through the predetermined quantity of the reagent. | 2008-12-18 |
20080311664 | BLANCHER WITH AUTOMATED PROCESS CONTROL - A method of operating a blanching system includes steps of automatically sampling a blanching solution and mixing the sampled blanching solution with a reagent that is formulated to change at least one property according to a concentration of a metal ion in the blanching solution. This property is automatically sensed with an automated sensor and a controller is used to automatically control a concentration of metal ions in the blanching solution in response to a signal that is received from said automated sensor | 2008-12-18 |
20080311665 | Chemical Assays - An assay device in which to carry out a fluid-phase chemical assay, comprising means for supporting a test substrate, a sample chamber for receiving a fluid sample and at least one fluid control device for controlling the movement of fluid into and/or out of the sample chamber, wherein the fluid control device comprises a fluid outlet chamber in fluid communication with the sample chamber, and a displaceable flexible diaphragm the displacement of which alters the volume of the outlet chamber so as to allow and/or restrict fluid flow between the outlet and sample chambers. The invention also provides assay apparatus incorporating such a device, an assay station for use as part of such apparatus, a fluid control unit for use as part of the assay device and a method of conducting an assay which may involve the use of such apparatus and devices. | 2008-12-18 |
20080311666 | Isotopically labeled compositions and method - Compounds having stable isotopes | 2008-12-18 |
20080311667 | Exogenous Markers for Oxidative Stress - The invention provides oxogenous markers, designed and synthesized for the measurement and characterization of oxidative/nitrosative stress levels, thus enable the identification of the type of reactive ROS/NRS involved, characterization of the damaged products and their formation kinetics, and thereby the identification of pathological conditions associated with oxidative/nitrosative stress, before appearing or at the stage of development. | 2008-12-18 |
20080311668 | Nucleic Acid Detection - Disclosed is the detection of a target nucleic acid sequence in a mixture of different nucleic acids having additional binding sites, by: hybridizing the target nucleic acid sequence with a probe in liquid phase, the probe having a first label. The additional binding sites are hybridized with single stranded nucleic acids having random primary sequences in liquid phase, the different nucleic acids are separated, and the target nucleic acid is detected by using the labeled probe. | 2008-12-18 |
20080311669 | SCREENING SEQUENCE SELECTIVITY OF OLIGONUCLEOTIDE-BINDING MOLECULES USING NANOPARTICLE BASED COLORIMETRIC ASSAY - Disclosed herein are methods of screening sequence selectivity of oligonucleotide-binding molecules using a gold nanoparticle based calorimetric assay. | 2008-12-18 |
20080311670 | Hydrogel Composition - An electrochemical sensor system comprises an electrochemical sensor and a hydrogel composition. The electrochemical sensor has at least a counter electrode and a working electrode. The hydrogel composition contacts the working electrode. The hydrogel composition comprises a first monomer, a second monomer, a cross-linking agent, and a solvent. The first monomer has hydrophilic characteristics. The second monomer has hydrophobic characteristics. The ratio of the first monomer to the second monomer is from about 0.1:99.9 to about 99.9:0.1. | 2008-12-18 |
20080311671 | Mass Spectrometry Method for Measuring Vitamin B6 in Body Fluid - Provided are methods of detecting the presence or amount of the active form of vitamin B6, pyridoxal 5′-phosphate, in a body fluid sample using tandem mass spectrometry coupled with liquid chromatography. | 2008-12-18 |
20080311672 | Membrane based concentrators - A sample concentrator for concentrating analytes in a solvent-containing liquid sample stream, including concentrator housing having a sample stream flow channel and a gas stream flow channel having an inlet and an outlet, a heater for gas in the gas stream conduit, and a hydrophilic ion exchange or non-ionic membrane barrier separating said gas stream flow channel and said sample stream flow channel. Solvent is evaporated from the liquid sample stream in said sample stream flow channel in or at the interface with said membrane, when the gas stream is at an elevated temperature. A regeneration step is used to regenerate the ion exchange membrane barrier. | 2008-12-18 |
20080311673 | Biomarkers for Breast Cancer - The present invention provides protein-based biomarkers and biomarker combinations that are useful in qualifying breast cancer status in a patient. In particular, the biomarkers of this invention are useful to classify a subject sample as breast cancer or non-breast cancer. The biomarkers can be detected by SELDI mass spectrometry. | 2008-12-18 |
20080311674 | METHODS AND COMPOSITIONS FOR ANALYZING PROTEINS - Methods, compositions and kits are disclosed for determining one or more target polypeptides in a sample where the target polypeptides have undergone a post-translational modification. A mixture comprising the sample and a first reagent comprising a cleavage-inducing moiety and a first binding agent for a binding site on a target polypeptide is subjected to conditions under which binding of respective binding moieties occurs. The binding site is the result of post-translational modification activity involving the target polypeptide. The method may be employed to determine the target polypeptide itself. In another embodiment the presence and/or amount of the target polypeptide is related to the presence and/or amount and/or activity of an agent such as an enzyme involved in the post-translational modification of the target polypeptide. The interaction between the first binding agent and the binding site brings the cleavage-inducing moiety into close proximity to a cleavable moiety, which is associated with the polypeptide and is susceptible to cleavage only when in proximity to the cleavage-inducing moiety. In this way, an electrophoretic tag for each of the polypeptides may be released. Released electrophoretic tags are separated and the presence and/or amount of the target polypeptides are determined based on the corresponding electrophoretic tags. | 2008-12-18 |
20080311675 | DYES HAVING RATIOMETRIC FLUORESCENCE RESPONSE FOR DETECTING METABOLITES - The presently disclosed subject matter provides thiol-reactive, environmentally sensitive fluorescent dyes, or fluorophores, which have an emission wavelength in the visible spectral region. When conjugated with a binding protein, the fluorophores exhibit a ratiometric response to one or more ligands or target analytes. The presently disclosed fluorophore-binding protein conjugates can be used to detect the presence of or amount of physiologically-important metabolites, such as glucose, fatty acids, and lactate, in biological samples. | 2008-12-18 |
20080311676 | IMMUNOASSAYS EXHIBITING REDUCED CROSS-REACTIVITY WITH HYDROPHOBIC DRUG ANALYTE METABOLITES - The present disclosure provides among other things immunoassays exhibiting reduced cross-reactivity with analyte metabolites. Additionally, the present disclosure provides diagnostic immunoassays to determine the concentration or level in a test sample of a hydrophobic drug that metabolizes in vivo or in vitro to form cross-reacting metabolites wherein cross-reactivity with such metabolites of the drug analyte is reduced. In particular, the disclosure provides such immunoassays where the hydrophobic drug is an immunosuppressant drug such as cyclosporine A. | 2008-12-18 |
20080311677 | SYSTEMS AND METHODS FOR DETECTING TARGET ANALYTES - A method of detecting a target substance includes contacting the target substance with a substrate. The substrate has a first receptor bound to the substrate. The target substance binds to the first receptor. The method further includes contacting a second receptor with the substrate. The second receptor is associated with the target substance. The second receptor is biotinylated. The method also includes contacting an anti-biotin antibody conjugated paramagnetic particle with the substrate. | 2008-12-18 |
20080311678 | SAMPLE ANALYZER AND SAMPLE ANALYZING METHOD - The present invention is to present a sample analyzer which is capable of separate and dispose of the reaction container and the reaction liquid respectively even when magnetic particles are included in a reagent. The sample analyzer | 2008-12-18 |
20080311679 | Biosensor Device - The invention relates to a biosensor device with an actuating element comprising a biorecognition element that is capable of binding target molecules from a sample of interest, wherein the actuating element comprises a polymer material, can be actuated by actuating means between a first and a second position. | 2008-12-18 |
20080311680 | Method for detecting high antigen concentration and device therefor - A method for detecting high antigen concentration is disclosed. The method enables the mobile-phase antibody, in the presence of excessive amount of antigen, to form the antibody-antigen-antibody sandwich with the immobilized solid-phase antibody effectively in a rapid lateral flow chromatographic immunoassay. The mobile-phase and/or immobilized solid-phase antibody are treated with soluble coatings to generate a delaying mechanism, so that antigen-antibody binding occurs only when both phases of antibodies and antigen are in very close proximity. A user friendly immunoassay device with a sample over-flow mechanism also facilitates such antigen-antibody binding. | 2008-12-18 |
20080311681 | Antibody Binding Affinity Ligands - The present application discloses a solid support material having covalently immobilized thereon an affinity ligand, said ligand comprising one or more hydrophobic functional group(s) and one or more cationic functional group(s) or one or more heteroaromatic functional group(s), wherein at least one hydrophobic functional group is separated from at least one cationic/heteroaromatic functional group by a through bond distance of from 5 Å to 20 Å, wherein said ligand has a molecular weight of from 120 Da to 5,000 Da. Typically, the affinity resin has a binding capacity larger than 5 mg monoclonal antibody per mL of affinity resin. A method for the isolation of biomolecules, such as proteins, in particular antibodies, such as monoclonal antibodies, or derivatives thereof, is also disclosed. | 2008-12-18 |
20080311682 | MICROWAVE INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FORMING SUCH PACKAGE - A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects. | 2008-12-18 |
20080311683 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device including forming a lower electrode over a substrate, increasing the temperature of the substrate with the lower electrode to a predetermined temperature under mixture gas atmosphere of inert gas and oxygen gas, forming a dielectric film on the lower electrode by using an organic metal raw material after the temperature reaches the predetermined temperature, and forming an upper electrode on the dielectric film. | 2008-12-18 |
20080311684 | Programmable Chip Enable and Chip Address in Semiconductor Memory - Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die. | 2008-12-18 |
20080311685 | METHODS RELATING TO THE RECONSTRUCTION OF SEMICONDUCTOR WAFERS FOR WAFER LEVEL PROCESSING - Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice. | 2008-12-18 |
20080311686 | Method of Forming Semiconductor Layers on Handle Substrates - A method of making a semiconductor thin film bonded to a handle substrate includes implanting a semiconductor substrate with a light ion species while cooling the semiconductor substrate, bonding the implanted semiconductor substrate to the handle substrate to form a bonded structure, and annealing the bonded structure, such that the semiconductor thin film is transferred from the semiconductor substrate to the handle substrate. | 2008-12-18 |
20080311687 | Method and Apparatus for Optimizing a Gate Channel - The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures. | 2008-12-18 |
20080311688 | Method and Apparatus for Creating a Gate Optimization Evaluation Library - The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures. | 2008-12-18 |
20080311689 | SECURING A TRANSISTOR OUTLINE CAN WITHIN AN OPTICAL COMPONENT - The present invention relates to affixing components of optical packages. The optical packages can include an optical component, such as a TO-Can. The TO-Can can house an optical transmitter and/or an optical receiver. Another optical component of the optical package can be a barrel for aligning the TO-Can with an optical fiber. The TO-Can can be affixed within an open end of the optical barrel using a bonding substance, such as an epoxy, that has wicking properties. The wicking properties cause the bonding substance to enter a gap between the optical barrel and the TO-Can by capillary action. Use of the bonding substance with wicking properties creates a more robust optical package in a cost effective manner. | 2008-12-18 |
20080311690 | ELIMINATE RELEASE ETCH ATTACK BY INTERFACE MODIFICATION IN SACRIFICIAL LAYERS - Methods of making a microelectromechanical system (MEMS) device are described. In some embodiments, the method includes forming a sacrificial layer over a substrate, treating at least a portion of the sacrificial layer to form a treated sacrificial portion, forming an overlying layer over at least a part of the treated sacrificial portion, and at least partially removing the treated sacrificial portion to form a cavity situated between the substrate and the overlying layer, the overlying layer being exposed to the cavity. | 2008-12-18 |
20080311691 | Method of Manufacturing Image Sensor - Provided is a method of manufacturing an image sensor. A microlens of inorganic material can be formed on a substrate by forming a seed microlens having a top surface with height differences, and then blanket etching the seed microlens to form a dome shaped microlens having a curvature following the height differences of the seed microlens. The height differences in the top surface of the seed microlens can be created by implanting nitrogen at different depths into an inorganic layer to form ion implantation regions, and removing the ion implantation regions from the inorganic layer. | 2008-12-18 |
20080311692 | Top Emission Organic Light Emitting Diode Display Using Auxiliary Electrode to Prevent Voltage Drop of Upper Electrode and Method of Fabricating the Same - An organic light emitting diode (OLED) display. The OLED display includes: a lower electrode formed on a layer on an insulating substrate having a thin film transistor. The lower electrode is electrically connected to the thin film transistor. An auxiliary electrode is formed on the same layer as the lower electrode, and a pixel defining layer is formed on edges of the lower electrode, thereby defining an opening which exposes a portion of the lower electrode. An organic layer is formed on the portion of the lower electrode exposed by the opening, and an upper electrode is formed on an entire surface of the insulating substrate and electrically connected to the auxiliary electrode. An edge of the auxiliary electrode may have a taper angle of at least 90°. | 2008-12-18 |
20080311693 | Method of Aligning Optical Components With Waveguides - A method of fabricating a photonic device comprises the steps of providing a core pattern of waveguide core material ( | 2008-12-18 |
20080311694 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE | 2008-12-18 |
20080311695 | Method of producing nitride semiconductor light-emitting device - In a method of producing a nitride semiconductor light-emitting device including a nitride semiconductor active layer ( | 2008-12-18 |
20080311696 | Manufacturing prpcess for photodetector - A manufacturing process for a photo-detector is provided. The present manufacturing process for a photo-detector comprises the steps of: (a) providing a thin-film Ge on a cheap substrate including a first processing area and a second processing area; (b) performing a defect-reduction processing to at least one of the first processing area and the second processing area; and (c) forming a photo-detector element on the Ge. | 2008-12-18 |
20080311697 | Method For Simultaneous Recrystallization and Doping of Semiconductor Layers and Semiconductor Layer Systems Produced According to This Method - The invention relates to a method for simultaneous recrystallisation and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. In this method, in a first step a substrate base layer | 2008-12-18 |
20080311698 | Fabrication of self-aligned via holes in polymer thin films - A low-cost and efficient process produces self-aligned vias in dielectric polymer films that provides electrical connection between a top conductor and a bottom conductor. The process is achieved by printing conductive posts on the first patterned conductive layer, followed by the deposition of an unpatterned layer dielectric, followed by the deposition of a second patterned conductive layer. The vias are formed during the flash annealing of the post after the dielectric is deposited, but before the second conductive layer is deposited. In this process, the post material is annealed with a flash of light, resulting in a release of energy which removes the dielectric on the top of the post. | 2008-12-18 |
20080311699 | PHASE-CHANGE MEMORY AND FABRICATION METHOD THEREOF - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 2008-12-18 |
20080311700 | Plastic overmolded packages with mechancially decoupled lid attach attachment - The specification describes a lidded MCM IC plastic overmolded package with a chimney-type heat sink. The lid is mechanically decoupled from the chimneys by a compliant conductive polymer plug. | 2008-12-18 |
20080311701 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor package includes the steps of: forming a material layer containing conductive particles on a semiconductor chip having a plurality of bonding pads on the upper surface thereof, baking the material layers to a non-flowing state; attaching the semiconductor chip in a face down manner to a substrate having connecting pads on the location corresponding to the bonding pads by using the material layers containing conductive particles; applying voltage for a electrical signal exchange to the semiconductor chip and the substrate so that the conductive particles are gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate; and curing the conductive particles of the material layers so that the conductive particles gathered between the bonding pads of the semiconductor chip and the connecting pads of the substrate to an non-flowing state. | 2008-12-18 |
20080311702 | METHODS FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE - An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner. | 2008-12-18 |
20080311703 | LEAD FRAME AND A METHOD OF MANUFACTURING THE SAME - A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased. | 2008-12-18 |
20080311704 | RADIO FREQUENCY IDENTIFICATION (RFID) TAG LAMINATION PROCESS USING LINER - A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set. | 2008-12-18 |
20080311705 | Lead frame and method for fabricating semiconductor package employing the same - A lead frame and a method of fabricating a semiconductor package including the lead frame, where the lead frame includes a die pad, a tie bar supporting the die pad, and a plurality of leads. The leads may include inner and outer leads arranged along an outer periphery of the die pad, with each of the inner and outer leads having tip terminals. The lead frame may include a connecting bar connected to tip terminals of each of the inner leads. In the method, a bonding pad of a semiconductor chip is mounted on the die pad and connected via a conductive wire to the inner leads of the lead frame. The semiconductor chip, wire and inner leads may be subjected to a molding process, and the connecting bar which connects the tip terminals of the inner leads may be cut so as to independently separate each of the inner leads from the die pad. | 2008-12-18 |
20080311706 | Method for manufacturing semiconductor device - To provide a method for manufacturing a highly-reliable semiconductor device, which is not damaged by external local pressure, with a high yield, a semiconductor device is manufactured by forming an element substrate having a semiconductor element formed using a single-crystal semiconductor substrate or an SOI substrate, providing the element substrate with a fibrous body formed from an organic compound or an inorganic compound, applying a composition containing an organic resin to the element substrate and the fibrous body so that the fibrous body is impregnated with the organic resin, and heating to provide the element substrate with a sealing layer in which the fibrous body formed from an organic compound or an inorganic compound is contained. | 2008-12-18 |
20080311707 | Process for producing a functional device-mounted module - The present disclosure provides an optical functional device-mounted module which needs no expensive or special members, can be reduced in size, and provide a producing process thereof. A bank to dam a liquid sealing resin is provided on a substrate around an optical functional device, the substrate being formed with a predetermined wiring pattern and having the optical functional device mounted thereon. The liquid sealing resin is filled between the functional device and the bank by dropping the liquid sealing resin therebetween. A package component member having a light transmission hole corresponding to an optical function part of the optical functional device is brought into contact with the bank such that the light transmission hole is opposed to the function part of the optical functional device, thereby causing the package component member to contact with the liquid sealing resin. The package component member is fixed onto the substrate by curing the liquid sealing resin and the bank is finally cut off and removed. | 2008-12-18 |
20080311708 | HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES - A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation. | 2008-12-18 |
20080311709 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly responsive semiconductor device in which the subthreshold swing (S value) is small and reduction in on-current is suppressed is manufactured. A semiconductor layer in which a thickness of a source region or a drain region is larger than that of a channel formation region is formed. A semiconductor layer having a concavo-convex shape which is included in the semiconductor device is formed by the steps of forming a first semiconductor layer over a substrate; forming a first insulating layer and a conductive layer over the first semiconductor layer; forming a second insulating layer over a side surface of the conductive layer; forming a second semiconductor layer over the first insulating layer, the conductive layer and the second insulating layer; etching the second semiconductor layer using a resist formed partially as a mask; and performing heat treatment to the first semiconductor layer and the second semiconductor layer. | 2008-12-18 |
20080311710 | METHOD TO FORM LOW-DEFECT POLYCRYSTALLINE SEMICONDUCTOR MATERIAL FOR USE IN A TRANSISTOR - A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors. | 2008-12-18 |
20080311711 | Gapfill for metal contacts - A method of making a semiconductor interconnect is disclosed. A semiconductor body on which a transistor comprising a doped region is formed is provided. A dielectric region is formed over the doped region, and a contact hole is formed in the dielectric to expose the doped region. The contact hole is cleaned and a first layer of metal is formed over a bottom and sidewalls of the contact hole. The first layer of metal is thinned so that the thickness of the first layer of metal on the sidewalls is made more uniform. A barrier is formed over the first layer of metal and the contact hole is filled with conductive material. | 2008-12-18 |
20080311712 | Insulated gate silicon nanowire transistor and method of manufacture - An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire. | 2008-12-18 |
20080311713 | MOBILITY ENHANCEMENT BY STRAINED CHANNEL CMOSFET WITH SINGLE WORKFUNCTION METAL-GATE AND FABRICATION METHOD THEREOF - The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate. | 2008-12-18 |
20080311714 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure and etching the metal layer over a pFET region of the CMOS structure. The method further includes etching at the oxide layer over the nFET region and forming gate structures over the nFET region and pFET region. | 2008-12-18 |
20080311715 | Method for forming semiconductor device - A method for forming a semiconductor device is disclosed. A substrate comprising trenches are provided. Dopants are doped into a region of the substrate neighboring a sidewall of the trenches by using an isotropic doping method. A gate dielectric layer is formed on the sidewall of the substrate. A gate electrode is formed in the trenches, wherein the gate electrode protrudes a surface of the substrate. | 2008-12-18 |
20080311716 | METHODS FOR FORMING FIELD EFFECT TRANSISTORS AND EPI-SUBSTRATE - A semiconductor method includes thermally treating at least a portion of a substrate so as to generate a plurality of vacancies in a region at a depth substantially near to a surface of the substrate. The substrate is then quenched so as to substantially maintain the vacancies in the region substantially near to the surface of the substrate. | 2008-12-18 |
20080311717 | Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications - An insulated-gate field-effect transistor ( | 2008-12-18 |
20080311718 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention is to possible to avoid an inconvenience at a coupling portion between a barrier metal film obtained by depositing a titanium nitride film on a titanium film and thus having a film stack structure and a metal film filled, via the barrier metal film, in a connecting hole opened in an insulating film. The manufacturing method of a semiconductor device includes the steps of: forming a contact hole and exposing a nickel silicide layer from the bottom of the contact hole; forming a thermal reaction Ti film by a thermal reaction using a TiCl | 2008-12-18 |
20080311719 | Method Of Forming A Field Effect Transistor - In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated. | 2008-12-18 |
20080311720 | Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions - A method of forming a transistor comprising: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region. | 2008-12-18 |
20080311721 | Semiconductor device manufacture method including process of implanting impurity into gate electrode independently from source/drain and semiconductor device manufactured by the method - A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions. | 2008-12-18 |
20080311722 | METHOD FOR FORMING POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 2008-12-18 |
20080311723 | TUNABLE SEMICONDUCTOR DIODES - A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value. | 2008-12-18 |
20080311724 | TFD LCD PANEL - Active devices in a thin film diode (TFD) liquid crystal display (LCD) panel used to control liquid crystal are formed by a metal layer, a transparent conductive layer, and an insulating layer sequentially on a substrate, wherein the metal layer is used as transmitting signal and the transparent conductive layer is used as bottom metal layer of metal-insulator-metal (MIM) thin film diode. The metal layer, the transparent conductive layer, and the insulating layer are defined with desired patterns. Further, a dielectric layer is formed over the substrate, metal layer, the transparent conductive layer, and the insulating layer, and defined to form the locations of electrode terminal and MIM thin film diode by using lithographic process. Next, another transparent conductive layer is formed on the dielectric layer and defined to form a pixel electrode and top metal layer of the MIM thin film diode by using lithographic process. | 2008-12-18 |
20080311725 | Method For Assembling Substrates By Depositing An Oxide Or Nitride Thin Bonding Layer - A method for assembling by molecular bonding two substrates, at least one of which is made of a semiconductor material characterised in that one of substrates, called a first substrate, includes a surface (A), where at least one portion is flat and provided with an initial surface roughness compatible with the molecular bonding. The inventive method consists in depositing a thin oxide or nitride bonding layer, whose thickness ranges from 10 to 20 nm, on at least one portion of the surface flat part of the first substrate for carrying out a molecular bonding without pre-polishing, in saturating the thin bonding layer with hydroxyl groups, in bringing the thin bonding layer saturated with hydroxyl groups in contact with the second substrate ( | 2008-12-18 |
20080311726 | Manufacturing method of SOI substrate - There is provided a method of manufacturing an SOI substrate which is practicable even when a supporting substrate having a low allowable temperature limit is used. A separation layer is formed in a region at a certain depth from a surface of a semiconductor substrate, and a first heat treatment is conducted when a semiconductor layer on the separation layer is bonded to the supporting substrate and separated. A second heat treatment is conducted to the supporting substrate to which the semiconductor layer is bonded. The second heat treatment is conducted at a temperature which is equal to or higher than the temperature of the first heat treatment and does not exceed a strain point of the supporting substrate. When the first heat treatment and the second heat treatment are conducted at the same temperature, a treatment time of the second heat treatment may be set to be longer. | 2008-12-18 |
20080311727 | METHOD OF CUTTING A WAFER - In a method of cutting a wafer, a supporting member is attached to an upper surface of the wafer on which semiconductor chips are formed. An opening is formed at a lower surface of the wafer along a scribe lane of the wafer. The lower surface of the wafer may be plasma-etched to reduce a thickness of the wafer. A tensile tape may be attached to the lower surface of the wafer. Here, the tensile tape includes sequentially stacked tensile films having different tensile modules. The supporting member is then removed. The tensile tape is cooled to increase the tensile modules between the tensile films. The tensile tape is tensed until the tensile films are cut using the tensile modules difference to separate the tensile tape from the semiconductor chips. Thus, the lower surface of the wafer may be plasma-etched without using an etching mask. | 2008-12-18 |
20080311728 | METHOD FOR RECOVERING DAMAGE OF LOW DIELECTRIC INSULATING FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a damage recovery method capable of recovering electrical characteristics of a low dielectric insulating film sufficiently while suppressing oxidation of buried metal and generation of pattern defaults. | 2008-12-18 |
20080311729 | Atmospheric Pressure Chemical Vapor Deposition - A process for coating a substrate at atmospheric pressure comprises the steps of vaporizing a controlled mass of semiconductor material at substantially atmospheric pressure within a heated inert gas stream, to create a fluid mixture having a temperature above the condensation temperature of the semiconductor material, directing the fluid mixture at substantially atmospheric pressure onto the substrate having a temperature below the condensation temperature of the semiconductor material, and depositing a layer of the semiconductor material onto a surface of the substrate. | 2008-12-18 |
20080311730 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING GATE THEREOF - A method of forming a gate of a semiconductor device includes providing a semiconductor substrate in which an active region is defined by isolation films, forming a gate insulating film on the active region, forming a capping film on the gate insulating film, and performing an annealing process on the resulting surface and then forming a gate in part of the active region. The capping film is formed on the gate insulating film to prevent a reaction between the gate insulating film and subsequent gate materials, thereby preventing a phenomenon in which the work function of a gate changes and also the creation of a gate insulator having a low dielectric constant. The annealing process is performed under fluorine gas ambient to prevent trap sites within the gate insulating film while the gate can be composed of a metal or fully silicided gate to reduce the EOT. | 2008-12-18 |
20080311731 | LOW PRESSURE CHEMICAL VAPOR DEPOSITION OF POLYSILICON ON A WAFER - Low pressure chemical vapor deposition (LPCVD) of polysilicon on a wafer in a manner that reduces the generation of particles during the deposition process. In one example embodiment, a method of LPCVD of polysilicon on a wafer positioned in a process tube includes various steps. First, introducing a particle inhibitor is introduced into the process tube. Next, a silicon source gas is introduced into the process tube. Finally, a doping gas is introduced into the process tube, resulting in the formation of a polysilicon film of a uniform thickness on the wafer. | 2008-12-18 |
20080311732 | Method for Forming Non-Amorphous, Ultra-Thin Semiconductor Devices Using Sacrificial Implantation Layer - A method for forming a semiconductor device includes defining a sacrificial layer ( | 2008-12-18 |
20080311733 | Method for fabricating semiconductor device with gate line of fine line width - A method for fabricating a semiconductor device including forming a gate insulation layer, a conductive layer for a gate electrode, and an insulation layer for a gate hard mask over a substrate, selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a first region of the substrate, thereby forming an initial gate line, forming a first insulation layer for an insulation over a resultant structure where the initial gate line is formed, performing a planarization process until the insulation layer for a gate hard mask is exposed, and selectively etching the insulation layer for a gate hard mask and the conductive layer for a gate electrode to expose a second region of the substrate, the second region being not overlapped with the first region, thereby forming a final gate line having a line width smaller than the initial gate line. | 2008-12-18 |
20080311734 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator. | 2008-12-18 |
20080311735 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device includes forming at least one gate pattern over a substrate, forming a first insulation layer over the gate patterns and the substrate, etching the first insulation layer in a peripheral region to form at least one gate pattern spacer in the peripheral region, forming a second insulation layer over the substrate structure, etching the second insulation layer in a cell region to a given thickness, forming an insulation structure over the substrate structure, and etching the insulation structure, the etched first insulation layer and second insulation layer in the cell region to form a contact hole. | 2008-12-18 |
20080311736 | METHODS OF FORMING OHMIC LAYERS THROUGH ABLATION CAPPING LAYERS - A method of forming an ohmic layer for a semiconductor device includes forming a metal layer on a Silicon Carbide (SiC) layer and forming an ablation capping layer on the metal layer. Laser light is impinged through the ablation capping layer to form a metal-SiC material. | 2008-12-18 |
20080311737 | Manufacturing method for semiconductor device containing stacked semiconductor chips - An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film. | 2008-12-18 |
20080311738 | METHOD OF FORMING AN INTERCONNECT JOINT - A method of forming an interconnect joint includes providing a first metal layer ( | 2008-12-18 |
20080311739 | Method of Forming a Self Aligned Copper Capping Layer - A method of forming a capping layer on a copper interconnect line ( | 2008-12-18 |
20080311740 | Power composite integrated semiconductor device and manufacturing method thereof - A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper electrodes is secured, and also the time-lapse degradation under high temperature which causes diffusion of copper and corrosion of copper is suppressed. Still furthermore, direct bonding connection can be established to current collecting electrodes in the power device portion, and also established to a bonding pad formed on the control circuit portion in the control circuit portion. A pad area at the device peripheral portion which has been hitherto needed is reduced, so that the area of the device is saved, and the manufacturing cost is reduced. | 2008-12-18 |
20080311741 | Selective W-Cvd Method and Method for Forming Multi-Layered Cu Electrical Interconnection - A substrate provided thereon with an electrical insulating film which carries holes or the like filled with a Cu-containing electrical interconnection film is subjected to a pre-treatment in which the surface of the electrical insulating film and that of the Cu-containing electrical interconnection film are treated at a temperature of not more than 300° C. using, in a predetermined state, a gas of a compound containing an atom selected from the group consisting of N, H and Si atoms within the chemical formula thereof, before selectively forming a W-capping film on the electrical interconnection film. After the completion of the pre-treatment, a W-capping film is selectively formed on the electrical interconnection film and then an upper Cu electrical interconnection is further formed. | 2008-12-18 |
20080311742 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region. | 2008-12-18 |
20080311743 | METHOD OF FABRICATING OPENING AND PLUG - A method of fabricating an opening or plug is provided. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome. | 2008-12-18 |
20080311744 | MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS - Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa. | 2008-12-18 |
20080311745 | High Temperature Processing Compatible Metal Gate Electrode For pFETS and Methods For Fabrication - A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO | 2008-12-18 |
20080311746 | NEW METAL PRECURSORS FOR SEMICONDUCTOR APPLICATIONS - Methods and compositions for depositing metal films are disclosed herein. In general, the disclosed methods utilize precursor compounds comprising gold, silver, or copper. More specifically, the disclosed precursor compounds utilize pentadienyl ligands coupled to a metal to increase thermal stability. Furthermore, methods of depositing copper, gold, or silver are disclosed in conjunction with use of other precursors to deposit metal films. The methods and compositions may be used in a variety of deposition processes. | 2008-12-18 |
20080311747 | METAL-GERMANIUM PHYSICAL VAPOR DEPOSITION FOR SEMICONDUCTOR DEVICE DEFECT REDUCTION - The present invention provides a method of manufacturing a metal silicide electrode ( | 2008-12-18 |
20080311748 | Semiconductor integrated circuit, semiconductor device, and manufacturing method of the semiconductor integrated circuit - A chip with increased impact resistance, attractive design and reduced cost, and a manufacturing method thereof are provided. A semiconductor integrated circuit is formed on a large glass substrate, and a part of data of a ROM included therein is determined by an ink jet method or a laser cutting method. Accordingly, the cost can be reduced without requiring a photomask, resulting in an inexpensive ID chip. Further, depending on the application, the semiconductor integrated circuit is transposed to a flexible substrate, thereby an ID chip with improved impact resistance and more attractive design can be achieved. | 2008-12-18 |
20080311749 | DIELECTRIC TRENCHES, NICKEL/TANTALUM OXIDE STRUCTURES, AND CHEMICAL MECHANICAL POLISHING TECHNIQUES - A portion of a conductive layer ( | 2008-12-18 |
20080311750 | Polishing composition for semiconductor wafer and polishing method - The present invention relates to a polishing composition for a semiconductor wafer which is excellent in polishing property, and a polishing method. The polishing composition for a semiconductor wafer comprises colloidal silica consisting of non-spherical silica particles having a ratio of long axis to short axis of 1.5 to 15. The polishing method for a semiconductor wafer uses the polishing composition. The polishing composition can provide a remarkably high polishing rate compared with a polishing composition using spherical colloidal silica, and can provide good mirror-polishing without causing scratches. In addition, small alkali metal content enables reduction of adverse effects on a semiconductor wafer, such as residual abrasives after polishing. | 2008-12-18 |
20080311751 | Method for Etching a Layer on a Substrate - A method for etching a layer that is to be removed on a substrate, in which a Si | 2008-12-18 |
20080311752 | Pore Sealing and Cleaning Porous Low Dielectric Constant Structures - A micellar solution is used to seal pores exposed at the bottom and sidewall surfaces of a structure etched in or through a porous low dielectric constant material. The micellar solution is also effective to clean away etch residues from the etched structure. | 2008-12-18 |
20080311753 | OXYGEN SACVD TO FORM SACRIFICAL OXIDE LINERS IN SUBSTRATE GAPS - A method of forming and removing a sacrificial oxide layer is described. The method includes forming a step on a substrate, where the step has a top and sidewalls. The method may also include forming the sacrificial oxide layer around the step by chemical vapor deposition of molecular oxygen and TEOS, where the oxide layer is formed on the top and sidewalls of the step. The method may also include removing a top portion of the oxide layer and the step; removing a portion of the substrate exposed by the removal of the step to form a etched substrate; and removing the entire sacrificial oxide layer from the etched substrate. | 2008-12-18 |
20080311754 | LOW TEMPERATURE SACVD PROCESSES FOR PATTERN LOADING APPLICATIONS - A method of improving pattern loading in a deposition of a silicon oxide film is described. The method may include providing a deposition substrate to a deposition chamber, and adjusting a temperature of the deposition substrate to about 250° C. to about 325° C. An ozone containing gas may be introduced to the deposition chamber at a first flow rate of about 1.5 slm to about 3 slm, where the ozone concentration in the gas is about 6% to about 12%, by wt. TEOS may also be introduced to the deposition chamber at a second flow rate of about 2500 mgm to about 4500 mgm. The deposition rate of the silicon oxide film is controlled by a reaction rate of a reaction of the ozone and TEOS at a deposition surface of the substrate. | 2008-12-18 |
20080311755 | Method for treating a dielectric film to reduce damage - A method of treating a dielectric layer on a substrate is described. The method comprises forming the dielectric layer on the substrate, wherein the dielectric layer comprises a dielectric constant value less than the dielectric constant of SiO | 2008-12-18 |
20080311756 | Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch. | 2008-12-18 |
20080311757 | SYSTEM AND METHOD FOR CHEMICAL DRY ETCHING SYSTEM - A system and method for chemical dry etching system. The present invention provides a method for performing an etching process for manufacture of integrated circuits. The method includes providing a semiconductor wafer. The method also includes the step of maintaining the semiconductor wafer in a predetermined environment. The method includes subjecting a portion of the layer to a plasma environment. The plasma environment includes one or more plasma species. For example, the plasma species are used to perform etching. The method also includes monitoring a pressure condition within a first transport device using a sensing device. The sensing device is spatially configured between a valve and a pumping device. The valve is coupled to a second exhaust coupled to the plasma chamber. The method additionally includes determining if the pressure condition within the first exhaust is within a predetermined condition. The method includes removing the one or more plasma species through the first exhaust, through the valve, and through the second exhaust if the pressure condition within the first exhaust is within the predetermined condition. | 2008-12-18 |
20080311758 | Methods of and apparatus for protecting a region of process exlusion adjacent to a region of process performance in a process chamber - Apparatus and methods protect a central process exclusion region of a substrate during processing of an edge environ region of process performance. Removal of undesired materials is only from the edge environ region while the central device region is protected from damage. Field strengths are configured to protect the central region from charged particles from plasma in a process chamber and to foster removal of the undesired materials from only the edge environ region. A magnetic field is configured with a peak value adjacent to a border between the central and edge environ regions. A strong field gradient extends from the peak radially away from the border and away from the central region to repel the charged particles from the central region. The strength and location of the field are adjustable by axial relative movement of magnet sections, and flux plates are configured to redirect the field for desired protection. | 2008-12-18 |