| 51st week of 2008 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20080309353 | CAPACITIVE TOUCH SENSOR - A touch sensor that includes sampling the output of a touch sensor circuit supplied with a high level carrier signal at least once, sampling the output of a touch sensor circuit supplied with a low level carrier signal at least once and thereby determining the occurrence of a touch by using at least one of said high level carrier samples and at least one of said low level carrier samples. | 2008-12-18 |
| 20080309354 | METHOD AND APPARATUS FOR TESTING CHARACTERISTIC IMPEDANCE OF TRANSMISSION LINES - An apparatus for testing characteristic impedance of transmission lines includes a variable resistor, a first comparator, a second comparator, and a counter. One terminal of the variable resistor is coupled to a signal source, another terminal of the variable resistor is coupled to one terminal of a transmission line, and another terminal of the transmission line is idle. The one terminal of the transmission line is coupled to the input terminals of the first and second comparators. The output terminals of the first and second comparators are respectively coupled to input terminals of the counter. An output terminal of the counter is coupled to an adjusting terminal of the variable resistor, the counter adjusts the resistance of the variable resistor according to signals output from the first and second comparators. | 2008-12-18 |
| 20080309355 | VOLTAGE CLAMP CIRCUIT AND SEMICONDUCTOR DEVICE, OVERCURRENT PROTECTION CIRCUIT, VOLTAGE MEASUREMENT PROBE, VOLTAGE MEASUREMENT DEVICE AND SEMICONDUCTOR EVALUATION DEVICE RESPECTIVELY USING THE SAME - In a voltage clamp circuit, a normally-on type field-effect transistor having a negative threshold voltage has a drain connected to an input node, a source connected to an output node and grounded via a resistance element, and a gate supplied with an output voltage of a variable direct-current power supply. When a voltage at the output node becomes higher than a clamping voltage because of voltage drop of the resistance element, the field-effect transistor is tuned off. Accordingly, the output voltage is limited to be at most the clamping voltage. Thus, a response speed is higher than those of conventional voltage clamp circuits using diodes or the like. | 2008-12-18 |
| 20080309356 | Differential Measurement Probe Having a Ground Clip System for the Probing Tips - A differential measurement probe has a ground clip system for electrically coupling outer shielding conductors of differential probing tips together. In one embodiment, the probing tips independently move vertically relative to each other with the ground clip system secured to each of the outer shielding conductors of the probing tips. In a further embodiment, the probing tips move both vertically and horizontally and the ground clip system has a spring wire member that is secured to the probe. The spring wire member is formed with various sections having various angles to each other that allows one section to slidably engage one of the outer shielding conductors on one of the probing tips and another section to slidably engage the outer shielding conductor of the other probing tip. | 2008-12-18 |
| 20080309357 | Differential Measurement Probe Having a Ground Clip System for the Probing Tips - A differential measurement probe has a ground clip system for electrically coupling outer shielding conductors of differential probing tips together. In one embodiment, the probing tips independently move vertically relative to each other with the ground clip system secured to each of the outer shielding conductors of the probing tips. In a further embodiment, the probing tips move both vertically and horizontally and the ground clip system has a spring wire member that is secured to the probe. The spring wire member is formed with various sections having various angles to each other that allows one section to slidably engage one of the outer shielding conductors on one of the probing tips and another section to slidably engage the outer shielding conductor of the other probing tip. | 2008-12-18 |
| 20080309358 | Active wafer probe - A probe suitable for probing a semiconductor wafer that includes an active circuit. The probe may include a flexible interconnection between the active circuit and a support structure. The probe may impose a relatively low capacitance on the device under test. | 2008-12-18 |
| 20080309359 | SUSPENSION SYSTEM AND ADJUSTMENT MECHANISM FOR AN INTEGRATED CHIP AND METHOD - Disclosed herein is a suspension system and adjustment mechanism for an integrated chip held in a clamping or similar assembly and a related method for same. The suspension system Includes a pressure plate member adapted to fit compatibly within the clamp assembly. A hinge assembly applies and releases pressure through the pressure plate member. The hinge assembly has a first open position where pressure is released and a second closed position where pressure is applied. A spring member between the pressure plate member and the hinge assembly has predetermined travel limits controlling the amount of pressure to be applied. In an exemplary embodiment of the invention disclosed herein the suspension system includes an adjustment mechanism which adjusts to the pressure to a fine degree. The adjustment mechanism includes a housing which applies and releases pressures in response to the turning of a control knob. The control knob is connected to a gear apparatus within the housing which responds to the movement of the control knob by moving the housing. | 2008-12-18 |
| 20080309360 | Testing apparatus for surface mounted connectors - This invention describes a device for testing a surface mounted connector using a test probe assembly that utilizes a vacuum to force the test wires and the test probe's wire array into intimate contact with the connector to be tested. | 2008-12-18 |
| 20080309361 | Method of Monitoring Burn-In Apparatus - A method of monitoring a burn-in apparatus, which brings a heater and a temperature sensor into contact with various devices under test during a burn-in test and controls power consumption of the heater to adjust levels of temperature of the devices under test, wherein the temperature sensor detects temperature of a temperature control block in which the heater and the temperature sensor are arranged and with which a cooling liquid is in contact while the devices under test are not in contact with the heater and the temperature sensor, and the temperature sensor is diagnosed to be normal or not based on a result of detection. | 2008-12-18 |
| 20080309362 | PROBE ASSEMBLY WITH PROBES FOR ELECTRICAL TESTING - Disclosed is a probe assembly for use in electrical testing of an object, a probe, and a method of making the probe assembly. The probe assembly has a probe supporter body elongated in a first direction and comprising a first side surface, a second side surface, a first facing surface and a second facing surface, wherein the first and second facing surfaces are configured to face a testing object, wherein the first and second facing surfaces are substantially nonparallel to each other. The assembly further has a plurality of first slots formed on the first side surface and the first facing surface and a plurality of second slots formed on the second side surface and the second facing surface. Each slot is configured to receive a portion of a probe. | 2008-12-18 |
| 20080309363 | PROBE ASSEMBLY WITH WIRE PROBES - Disclosed is a probe assembly for use in electrical testing of a testing object and a method of the probe assembly. The probe assembly has a probe supporter body having a first side surface and a first facing surface and a plurality of wire probes. One of the plurality of wire probes has a first arm generally extending in a first direction, a second arm electrically and physically connected to the first arm and generally extending in a second direction other than the first direction, a first terminal portion formed at a distal end of the first arm and comprising a first tip, and a second terminal portion formed at a distal end of the second arm and comprising a second tip. The assembly further has a securing film placed over a portion of the second arm and keeping the portion of the second arm from moving. | 2008-12-18 |
| 20080309364 | METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT - A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence. | 2008-12-18 |
| 20080309365 | Method for Determining Time Dependent Dielectric Breakdown - The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage. | 2008-12-18 |
| 20080309366 | System and method for bearing fault detection using stator current noise cancellation - A system and method for detecting incipient mechanical motor faults by way of current noise cancellation is disclosed. The system includes a controller configured to detect indicia of incipient mechanical motor faults. The controller further includes a processor programmed to receive a baseline set of current data from an operating motor and define a noise component in the baseline set of current data. The processor is also programmed to repeatedly receive real-time operating current data from the operating motor and remove the noise component from the operating current data in real-time to isolate any fault components present in the operating current data. The processor is then programmed to generate a fault index for the operating current data based on any isolated fault components. | 2008-12-18 |
| 20080309367 | SEMICONDUCTOR INTEGRATED DEVICE - A semiconductor integrated device includes an internal oscillation circuit that oscillates to output a clock signal, a logic circuit, and a control circuit. In a normal operation mode, the logic circuit loads a target data signal in synchronization with the clock signal, and in a test mode, the logic circuit outputs a stop signal for stopping supply of the clock signal at a predetermined time, and allows the target data signal to be transferred to and from the outside after the stop signal is outputted. The control circuit controls such that, in the normal operation mode, the clock signal is supplied to the logic circuit, and in the test mode, the clock signal is not supplied to the logic circuit after the stop signal is outputted. | 2008-12-18 |
| 20080309368 | CIRCUIT FOR GENERATING ON-DIE TERMINATION CONTROL SIGNAL - A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform a second on-die termination control at an initial stage of operation, and a signal output block configured to generate the on-die termination control signal by combining the first and second signals. | 2008-12-18 |
| 20080309369 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 2008-12-18 |
| 20080309370 | Reprogrammable Integrated Circuit - A reprogrammable integrated circuit, including one or more logic dies including circuit components; and one or more reprogrammable interconnect dies including reprogrammable interconnect components electrically connected to the circuit components to define signal routing paths between the circuit components to allow a user to develop an integrated circuit. | 2008-12-18 |
| 20080309371 | FACE-TO-FACE BONDED I/O CIRCUIT DIE AND FUNCTIONAL LOGIC CIRCUIT DIE SYSTEM - An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to-face bonding pads of each member of the other set. | 2008-12-18 |
| 20080309372 | Semiconductor memory device - The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command of the chip enable signal; a standard chip enable pad which receives the output command; a first extension pad which supplies a first extension chip enable signal (/CEm+1) to the chip enable buffer circuit; a second extension pad which supplies a second extension chip enable signal (CEm+1) to the chip enable buffer circuit; a first option pad which receives a first option signal; and a second option pad which receives a second option signal, is constituted. | 2008-12-18 |
| 20080309373 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT - An integrated circuit device includes a clock signal supply control circuit that controls a timing when a master clock signal output from an oscillation circuit is supplied to an internal circuit of the integrated circuit device. The clock signal supply control circuit stops supplying the master clock signal to an internal circuit until a count circuit counts clock pulses of the master clock signal up to a predetermined number. The count circuit performs the count operation asynchronously with the master clock signal. The integrated circuit device may include a divided clock signal supply circuit that supplies a divided clock signal obtained by dividing the frequency of a clock signal output from the clock signal supply control circuit to the internal circuit. A clock signal divider circuit generates the divided clock signal asynchronously with the master clock signal. | 2008-12-18 |
| 20080309374 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 2008-12-18 |
| 20080309375 | High accuracy current mode duty cycle and phase placement sampling circuit - A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases. | 2008-12-18 |
| 20080309376 | Mains Phase Detection Apparatus - The present invention relates to an apparatus for accurately detecting a mains phase. The apparatus is constructed with a zero-crossing detector, a digital phase detector, a digital loop filter, and a digital controlled oscillator (DCO) of a direct digital synthesized (DDS) manner. The present apparatus employs an all-digital loop architecture and a high sampling clock to recover a signal with a phase orthogonal with the mains signal and a frequency the same as the mains signal. And jitters in the recovered signal are less than 10 us. The present apparatus is capable of implementing signal tracking of a zero frequency error and a zero phase in a wide range, and can provide a detection result of excellent performance for the power line carrier communication, mains frequency detection, etc. | 2008-12-18 |
| 20080309377 | BALANCED PHASE DETECTOR - Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection. | 2008-12-18 |
| 20080309378 | SEMICONDUCTOR DEVICE - A semiconductor device | 2008-12-18 |
| 20080309379 | Zero crossing circuit - An improved zero crossing circuit includes a signal output circuit element for registering a sharply defined signal, and in one embodiment an isolation circuit element cooperating with the signal output element, and a delay-inducing circuit element cooperating with the signal output element for applying a substantially constant time delay to the signal. In particular, the delay-inducing element includes a switch circuit and a delay circuit. The switch circuit commences the time delay by the delay circuit upon a triggering voltage being reached. The time delay circuit is adapted so that the time delay equates to a time period required for the triggering voltage to change to zero so as to cross zero voltage substantially as the time delay expires. | 2008-12-18 |
| 20080309380 | METHOD AND APPARATUS FOR DETECTING SWITCHING CURRENT OF MAGNETIC DEVICE OPERATED IN CONTINUOUS CURRENT MODE - The present invention provides a method and apparatus for detecting a continuous current of a switching current. A current signal is produced in response to a switching current of the magnetic device. By sampling the waveform of the current signal in response to the enabling of a switching signal, a first current signal and a second current signal are generated. A continuous current signal is produced according to the first current signal and the second current signal. The continuous current signal is corrected to the continuous current of the switching current. | 2008-12-18 |
| 20080309381 | Device for Controlling a High-Voltage Transistor, in Particular a Mos Transistor of a High-Voltage Radio-Frequency Generator for the Spark Ignition of an Internal Combustion Engine - A control device including: an input terminal for receiving a logic control signal; an output terminal for delivering an output control signal from the high-voltage MOS transistor; a first NMOS control transistor with low internal impedance, which is connected between ground and the output terminal and the gate of which is connected to the input terminal; and a second PMOS control transistor, which is connected between a supply terminal and the output terminal and the gate of which is connected to the input terminal by a bipolar transistor mounted to a common base, and which is current controlled at the emitter thereof by a capacitive connecting circuit. | 2008-12-18 |
| 20080309382 | MOSFET for synchronous rectification - This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry. | 2008-12-18 |
| 20080309383 | Semiconductor Integrated Circuit - A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal. | 2008-12-18 |
| 20080309384 | Initialization Circuitry Having Fuse Leakage Current Tolerance - A system for initializing circuitry is presented. The system employs a power-on reset circuit having a threshold voltage and a programmable switch circuit. The power-on reset circuit has a detector circuit for detecting a reference voltage, and a one-sided latch for generating an output voltage reflective of the reference voltage. The detector circuit has a threshold after which the one-sided latch is activated. The programmable switch circuit receives the output voltage of the power-on reset circuit and generates an enable signal arid its complement based on the status of an internal fuse. The switch point of the power-on reset circuit provides for a rapid increase in output voltage, offsetting parasitic leakage current in the programmable switch circuit that can result in improper enable signal output. | 2008-12-18 |
| 20080309385 | ELECTRONIC DEVICE AND METHOD FOR ON CHIP SKEW MEASUREMENT - The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value. | 2008-12-18 |
| 20080309386 | BIAS GENERATOR PROVIDING FOR LOW POWER, SELF-BIASED DELAY ELEMENT AND DELAY LINE - An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, careful selection of parameters for providing the reference voltage and/or providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation. | 2008-12-18 |
| 20080309387 | DLL CIRCUIT - A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units being equal to the delay time of each of the first delay units; and a blocking control circuit configured to control the blocking circuit whether to pass or block the delayed signal that is input in the blocking circuit. | 2008-12-18 |
| 20080309388 | METHOD FOR ADJUSTING PHASE RELATIONSHIP BETWEEN SIGNALS IN A MEASURING APPARATUS, AND A MEASURING APPARATUS - A measuring apparatus having a frequency-swept heterodyne-type frequency converter equipped with a frequency-swept signal source and a multiplier includes means for detecting the timing of reference burst signals that have been subjected to frequency conversion by the frequency converter, with the frequency of the output signals of the frequency-swept signal source locked; means for generating periodic pulse signals; and means for adjusting the phase relationship between the pulse signals and the reference burst signals using the detected timing; and means for sweeping the frequency of the output signals of the frequency-swept signal source using pulse signals that have been subjected to a phase relationship adjustment. | 2008-12-18 |
| 20080309389 | SYSTEM FOR PREVENTING SHOPPING CART PUSH-OUT THEFT - A system and method for preventing push-out theft includes a network of electronic devices that are collectively operable in either a “safe restart” mode” or in an “operational” mode. The network is installed in a shopping area and prevents shopping cart removal from the area when in the “operational” mode. It does this by initially issuing egress permits to every shopping cart. The network then selectively removes egress permits when a shopping cart enters a selected section of the shopping area. Another egress permit is issued when the shopping cart successfully passes a cashier location. Otherwise, a sentry beacon will disable a shopping cart with no egress permit, before it can leave the shopping area. The network defaults to a permit issuing mode whenever a component of the system becomes inoperable. | 2008-12-18 |
| 20080309390 | Multi-Mode Digital-to-Analog Converter - Various apparatuses, methods and systems for a multi-mode DAC with selectable output range, granularity and offset and controlled slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus for supplying a reference signal, including a digital-to-analog converter, a counter and a clock. The digital-to-analog converter has a digital input and an analog output that supplies a reference signal based on the digital input. The counter has a digital control word input, a clock input, a clock enable output and a count output connected to the digital input of the digital-to-analog converter. The counter is adapted to assert the clock enable output when the digital control word input requests an output count that is different from an actual count at the count output of the counter. The clock has an enable input connected to the clock enable output of the counter and a clock output connected to the clock input of the counter. The clock is adapted to produce clock pulses on the clock output while the enable input is asserted. | 2008-12-18 |
| 20080309391 | DELAY CIRCUIT AND RELATED METHOD THEREOF - Disclosed is a delay circuit, which comprises: a map delay module, for delaying an input data signal to generate an output data signal according to a mapped delay selection signal; and a delay mapping unit, coupled to the map delay module, for generating the mapped delay selection signal according to an input selection signal and at least a mapping value. | 2008-12-18 |
| 20080309392 | Programmable Digital Delay - A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the first logic state to introduce a second selectable time period, wherein the control signals for the delay elements in the sequence not in the second number are set to the second logic state; whereby the reconfiguration time between the first and second input signals is less than the maximum delay introduced by the sequence of delay elements. | 2008-12-18 |
| 20080309393 | CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP - A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock. | 2008-12-18 |
| 20080309394 | GUARDRINGED SCR ESD PROTECTION - Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less. | 2008-12-18 |
| 20080309395 | Systems and Methods for Level Shifting using AC Coupling - Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value. | 2008-12-18 |
| 20080309396 | Hacking Detector Circuit For Semiconductor Integrated Circuit and Detecting Method Thereof - Disclosed is a semiconductor integrated circuit which includes a pre-charge capacitor connected to a check node pre-charged. A sense capacitor is configured to discharge the check node. A detector is configured to detect whether the sense capacitor is exposed, based upon a voltage of the check node after a predetermined length of time has elapses. | 2008-12-18 |
| 20080309397 | Semiconductor device including a bias voltage generator - A semiconductor device including a bias voltage generator formed from a junction field effect transistor (JFET). The JFET includes a control gate terminal and a first and a second source/drain terminal. The first and second source/drain terminals can form a first terminal of a p-n junction and the control gate terminal can form a second terminal of the p-n junction. The first terminal of the p-n junction can be provided with a first potential. The second terminal can be left essentially floating to provide a bias voltage. A bias receiving circuit can receive the bias voltage. The bias receiving circuit can be in close proximity on the semiconductor device to the bias voltage generator. | 2008-12-18 |
| 20080309398 | MULTIPLIER CIRCUIT - A multiplier circuit includes a bias circuit which outputs a reference voltage and a bias signal, a first delay circuit which inputs a input signal and outputs a first delayed signal according to the reference voltage and the bias signal, a second delay circuit which inputs an inversed input signal and outputs a second delay signal according to the reference voltage and the bias signal and an OR circuit which outputs a OR logic result generated with the first and second delayed signals. | 2008-12-18 |
| 20080309399 | Two-phase charge pump circuit without body effect - A two-phase charge pump circuit without the body effect includes a voltage boost stage, an input stage connected to the voltage boost stage, and a high-voltage generator connected to the input stage. Each of the circuits can consist of NMOS or PMOS transistors. The body of each NMOS transistor is connected to an NMOS switch. The body of each PMOS transistor is connected to a PMOS switch. By providing an appropriate driving signal to each NMOS or PMOS switch, the body of each NMOS transistor can be switched to a lower voltage level and the body of each PMOS transistor is switched to a higher voltage level. This can prevent the body effect from occurring. | 2008-12-18 |
| 20080309400 | SWITCHES WITH PASSIVE BOOTSTRAP - Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor. | 2008-12-18 |
| 20080309401 | Random Number Generating Circuit - Provided is a random number generating circuit having a simple circuit structure, for generating a physical random number based on a noise. The random number generating circuit includes a reference voltage section, an inverting amplifier section having a threshold voltage equal to a reference voltage level, and a semiconductor switch provided between an output terminal of the reference voltage section and an input terminal of the inverting amplifier section. A thermal noise produced from the reference voltage section is held by the semiconductor switch and a capacitor and amplified by the inverting amplifier section to generate the physical random number. | 2008-12-18 |
| 20080309402 | EXTINCTION OF PLASMA ARCS - A circuit configuration reduces electrical energy stored in a lead inductance formed by a plurality of leads that connect a power supply unit with a load. The circuit configuration includes a switching device in operative connection with at least one of the leads for enabling or interrupting power to the load. The circuit configuration also includes a first electrical nonlinear device arranged in parallel with the switching device; an energy storing device arranged in parallel with the switching device and in series with the first electrical nonlinear device; and a pre-charging circuit in operative connection with the energy storing device for charging the energy storing device to a pre-determined voltage level while power to the load is enabled. | 2008-12-18 |
| 20080309403 | Modulation Method with Insertion of Semi-Pilot Symbols - Method and device for modulating a signal comprising data symbols and reference symbols, characterized in that it comprises at least one step ( | 2008-12-18 |
| 20080309404 | Single-Ended Amplifier - In an amplifier arrangement comprising an amplifier (A | 2008-12-18 |
| 20080309405 | Power Amplifier Pre-Distortion - The present invention is directed to systems and methods for reducing the distortion of power amplifiers. In particular, methods and systems are described that enable a determination of a pre-distortion correction signal to be determined, which when added to the nominal signal, a reduction in the distortion of the power amplifier results. In addition, methods and systems are described that enable calibration of individual power amplifiers to be accomplished for use with the above described approach. More specifically, the methods and systems are described for use in a MIMO application. These approaches may be applied to on-chip power amplifiers, off-chip power amplifiers, or any combination thereof. | 2008-12-18 |
| 20080309406 | Full-Bridge Class-D Power Amplifier - The present invention relates to a full bridge class-D amplifier where one of the output terminals ( | 2008-12-18 |
| 20080309407 | Transimpedance Amplifier - A gain switching determination circuit ( | 2008-12-18 |
| 20080309408 | SYMMETRICAL DIFFERENTIAL AMPLIFIER - A differential amplifier has improved power efficiency, reduced offset penalty and a symmetrical output differential signal. Such a differential amplifier may include: (a) a bias circuit that has a first input device and a second input device; (b) a first load device and a second load device, each biased by a bias voltage from the bias circuit; and (c) a third input device and a fourth input device that are connected in series with the first load device and the second load device, respectively. In that differential amplifier, the differential input signal is applied across the first and second input devices, as well as across the third and the fourth input devices. The first, second, third and fourth input devices are sized such that a total current in the first and second input devices bears a predetermined ratio to a total current in the third and fourth input devices. | 2008-12-18 |
| 20080309409 | Balanced differential cross-coupled transconductance amplifier for a multiplexor - A balanced, differential, cross-coupled amplifier including an input stage for receiving a differential input and including an input transconductance differential pair and a feedback transconductance differential pair; and an output stage responsive to the input stage for providing a differential output; the differential input being connected to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair, the differential output being fed back to one input of the input transconductance differential pair and one input of the feedback transconductance differential pair for balancing the currents in the transconductance differential pairs over the input range. | 2008-12-18 |
| 20080309410 | OFFSET FIXING OPERATIONAL AMPLIFIER CIRCUIT - In an offset fixing operational amplifier circuit, an operational amplifier circuit includes an input stage containing a first constant current source, a second constant current source, a first differential pair and a second differential pair. A bias circuit supplies a bias voltage to the operational amplifier circuit. An offset fixing circuit controls the input stage in accordance with an input voltage of the operational amplifier circuit. | 2008-12-18 |
| 20080309411 | RADIO FREQUENCY SIGNAL AMPLIFYING DEVICE - There is provided a radio frequency (RF) signal amplifying device consuming less power and operable at a high voltage in a PA driving amplifying apparatus applicable to a PA amplifying circuit which amplifies power of an RF signal. The RF signal amplifying device includes: a balun converting an unbalanced radio frequency signal into a balanced radio frequency signal; a primary amplifier differentially amplifying the balanced radio frequency signal from the balun; and at least one secondary amplifier secondarily and differentially amplifying the balanced radio frequency signal amplified from the primary amplifier. | 2008-12-18 |
| 20080309412 | ORGANIC FIELD EFFECT TRANSISTOR SYSTEMS AND METHODS - An OFET includes a ferroelectric gate dielectric permitting electrical reprogramming, such as to implement an electrically re-programmable array logic (PAL) or a field-programmable gate array (FPGA). Methods of constructing such an OFET, PAL, or FPGA, can including roll printing. An OFET on a piezoelectric substrate provides local amplification in an active matrix. Methods of constructing such an OFET on a piezoelectric substrate can including rolling printing. Techniques permit direct measurement of trap distribution, such as across the channel length of an OFET device. Techniques permit direct measurement of the size and location of an electrically active grain structure in OFET devices. Techniques permit confirmation of the mechanism of operation of a number of OFET techniques, including use of silanes or thiols, or OFET operation or aging. Techniques provide an internal circuit probe, such as for a ferroelectric gate dielectric OFET or a piezoelectric substrate OFET, for example. | 2008-12-18 |
| 20080309413 | GAIN SWITCHING LOW-NOISE AMPLIFIER CIRCUIT - In a gain switching LNA including a first transistor, a first transistor group (for example, second to ninth transistors) and a second transistor group (for example, tenth to seventeenth transistors), a first resistor connected between an emitter of the tenth transistor and a collector of the first transistor and a second resistor connected to emitters of eleventh to seventeenth transistors and the collector of the first transistor and having a resistance one seventh as high as that of the first resistor are provided. In a high-gain mode, since isolation of the tenth to seventeenth transistors which are turned OFF and the first and second to ninth transistors is secured by the first resistor and the second resistor, there is no deterioration in the noise factor. | 2008-12-18 |
| 20080309414 | VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP CIRCUIT INCORPORATING THE SAME - A voltage controlled oscillator includes a ring oscillator configured by connecting invertors, each of the invertors including a first and a second transistors, an operational amplifier to obtain an amplified signal, third transistors inserted between the first transistors and a first power supply, and is gate-controlled by the amplified signal, fourth transistors inserted between the second transistors and a second power supply, and is gate-controlled by the control signal, a inverter including a fifth and a sixth transistor, gate terminals and drain terminals of the fifth and sixth transistor being connected in common to a first input terminal of the operational amplifier, a seventh transistor inserted between the fifth transistor and the first power supply, and gate-controlled by the amplified signal, and an eighth transistor inserted between the sixth transistor and the second power supply, and gate-controlled by the control signal. | 2008-12-18 |
| 20080309415 | HIGH-FREQUENCY OSCILLATOR AND ELECTRONIC APPARATUS - In a high-frequency oscillator, a first resonance circuit and a second resonance circuit are respectively connected to a first amplifier circuit and a second amplifier circuit. A selection circuit includes a first switch circuit and a second switch circuit which selectively operate one of the first amplifier circuit and the second amplifier circuit. A grounded capacitor is connected to output sides of the first amplifier circuit and the second amplifier circuit. The grounded capacitor is commonly used by both the first amplifier circuit and the second amplifier circuit. An auxiliary grounded capacitor is connected between the first switch circuit and the first amplifier circuit. Accordingly, the grounded capacitor and the auxiliary grounded capacitor are connected to each other in parallel only when the first amplifier circuit is activated. | 2008-12-18 |
| 20080309416 | Wide Range Interpolative Voltage Controlled Oscillator - Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters. | 2008-12-18 |
| 20080309417 | RING OSCILLATOR - A ring oscillator comprises a first logic block having a first input connected to a specific point along a delay path, a first output and a second output and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path and a first output connected to the beginning of the delay path. The first logic block is arranged to, in use, alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to, in use, alternately select its first input and its second input every time a rising edge is input into its third input. The pulse width of the signal output from the first output of the second logic block is indicative of the time necessary for one of a rising edge or a falling edge to propagate from the beginning of the delay path to the specific point along the delay path and the inverse pulse width of the signal output from the first output of the second logic block is indicative of the time necessary for the one of the rising edge or the falling edge respectively to propagate from specific point along the delay path to the end of the delay path. | 2008-12-18 |
| 20080309418 | Bonding-type surface-mount crystal oscillator - A crystal oscillator has: a crystal unit having a container body in which a crystal blank is housed and hermetically sealed; and a mounting substrate that houses an IC chip having at least an integrated oscillating circuit that uses the crystal unit. External terminals are formed as protrusions at four corners of the outer bottom surface of the container body, and depressions corresponding to the external terminals are formed at four corners of the top surface of the mounting substrate. Bonding terminals are formed at the inner bottom surface of the depressions. The mounting substrate is electrically and mechanically bonded to the outer bottom surface of the crystal unit by fitting the external terminals into the depressions and bonding the external terminals to the corresponding bonding terminals by soldering. | 2008-12-18 |
| 20080309419 | Voltage Controlled Oscillator Capable of Tuning Negative Resistance - Provided is a voltage controlled oscillator having a new type of a resonator and a negative resistance part capable of finely tuning negative resistance. Thus, the voltage controlled oscillator has an excellent quality factor characteristic and can finely tune the negative resistance even after its fabrication is completed. The voltage controlled oscillator having an active element includes: a resonating unit for generating an oscillation frequency according to a resonance capacitance; a frequency tuning unit, connected to a source terminal of the active element, for tuning the oscillation frequency; and a negative resistance adjusting unit, connected to the frequency tuning unit, for generating a negative resistance to adjust the oscillation frequency, the negative resistance adjusting unit including a varactor diode for finely adjusting the negative resistance. | 2008-12-18 |
| 20080309420 | FRACTIONAL DIVIDER - A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate. | 2008-12-18 |
| 20080309421 | PHASE LOCKED LOOP WITH TWO-STEP CONTROL - A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (f | 2008-12-18 |
| 20080309422 | Oscillator - An oscillator according to the present invention includes: an active element that oscillates at a predetermined frequency to output a signal of the predetermined frequency; and an impedance element having an impedance that is lower at a frequency lower than the predetermined frequency than at the predetermined frequency, the active element having signal terminals at least one of which is grounded through a series circuit composed of the impedance element and a capacitor. | 2008-12-18 |
| 20080309423 | VOLTAGE CONTROL OSCILLATOR AND OSCILLATION CONTROL SYSTEM - A voltage control oscillator has a first MOS transistor having one end connected to a first potential; a second MOS transistor having one end connected to the first potential, a gate connected to an other end of the first MOS transistor, and an other end connected to a gate of the first MOS transistor; a first varactor having one end connected to the other end of the first MOS transistor, an other end connected to the other end of the second MOS transistor, and a capacitance changing with a first control voltage; a first inductor having one end connected to the one end of the first varactor; a second inductor having one end connected to the other end of the first varactor; a second varactor having one end connected to an other end of the first inductor, an other end connected to an other end of the second inductor, and a capacitance changing with a second control voltage; a third inductor connected between the one end of the second varactor and a second potential; and a fourth inductor connected between the other end of the second varactor and the second potential. | 2008-12-18 |
| 20080309424 | Digital Tuning of Crystal Oscillators - Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator. | 2008-12-18 |
| 20080309425 | Liquid ejecting apparatus and signal transmission channel - A liquid ejecting apparatus is provided with: a first cable that includes a ground line group in which ground lines are lined up continuously in a plurality of transmission lines lined up in a predetermined direction; and a second cable that is arranged so as to be in opposition to the first cable and in which a plurality of transmission lines are lined up in the predetermined direction, a transmission line, in which voltage varies, being arranged so as to be in opposition to a region that covers the ground line group. | 2008-12-18 |
| 20080309426 | IRREVERSIBLE CIRCUIT ELEMENT - An irreversible circuit element is configured by including a magnetic substance, a plurality of central conductors L | 2008-12-18 |
| 20080309427 | Transit Structure of Standard Waveguide and Dielectric Waveguide - A transit structure of a standard waveguide and a dielectric waveguide is related to connecting the dielectric dielectric waveguide to the standard waveguide. The transit structure includes: a cavity to match the dielectric waveguide and the standard waveguide, wherein the dielectric waveguide and the standard waveguide are orthogonal to each other to connect. The transit structure drastically reduces a design time by simply implementing a transit structure by using only a dielectric waveguide, a cavity and a standard waveguide on a dielectric substrate and remarkably reduces a size thereof in comparison with a conventional transit structure since all designs are finished in the size of a metal waveguide. | 2008-12-18 |
| 20080309428 | Antenna with High Isolation - Provided is an antenna with high isolation. The high-isolation antenna has transmission ports of a transmission radiating body and reception ports of a reception radiating body highly isolated from each other by using a quadrature hybrid coupler. The antenna includes: a transmission radiating body having two feed points for transmitting signals; a reception radiating body having two feed points for receiving signals; a transmission hybrid coupler which is connected to the two feed points of the transmission radiating body and transmits transmission signals which have a phase difference of 90° with each other; and a reception hybrid coupler which is connected to the two feed points of the reception radiating body and receives reception signals which have a phase difference of 90° with each other. The signals leaking from the two feed points of the transmission radiating body to the two feed points of the reception radiating body are offset. | 2008-12-18 |
| 20080309429 | MONOLITHIC INTEGRATED INDUCTOR - A monolithic integrated inductor and a method for configuring the monolithic integrated inductor are provided. The monolithic integrated inductor includes a first coil having a first inductance value, at least one second coil connected in parallel to the first coil and having a second inductance value to form a total inductance, and lines to the first coil and to the second coil. The first coil has at least two first loops spaced at a distance with a path width. The second coil has at least two second loops spaced at the distance with the path width. The first loops form a magnetic coupling, and the second loops form a magnetic coupling. | 2008-12-18 |
| 20080309430 | LOW-LOSS TUNABLE RADIO FREQUENCY FILTER - A tunable RF filter comprises a signal transmission path having an input and output, a plurality of resonant elements disposed along the signal transmission path between the input and output, and a set of non-resonant elements coupling the resonant elements together to form a stop band having a plurality of transmission zeroes corresponding to respective frequencies of the resonant elements, and at least one sub-band between the transmission zeroes. The set of non-resonant elements comprises a first plurality of non-resonant elements respectively coupled in parallel with the resonant elements, and a second plurality of non-resonant elements respectively coupled in series with the resonant elements. The first plurality of non-resonant elements comprises at least one variable non-resonant element for selectively introducing at least one reflection zero within the stop band to create a pass band in one of the one sub-band(s) without varying any of the second plurality of non-resonant elements. | 2008-12-18 |
| 20080309431 | PLANAR EMI FILTER - An EMI filter for use between a power source and an electronic product is formed of at least one planar element including a pair of opposed coreless spiral planar windings, and a planar capacitor. This enables the integration of common mode and differential mode filters into integrated planar structures. | 2008-12-18 |
| 20080309432 | Piezoelectric Resonator Structure and Method for Manufacturing a Coupled Resonator Device - A method for manufacturing a coupled resonator device includes forming a first part of a plurality of layers, trimming an exposed layer of the first part and forming a remaining part of the plurality of layers. The coupled resonator device includes a stack of the plurality of layers, the plurality of layers including a first piezo-layer with a first and a second electrode layer sandwiching the first piezo-layer, a second piezo-layer with a first and a second electrode layer sandwiching the second piezo-layer, the first and second piezo-layers being acoustically coupled to each other. | 2008-12-18 |
| 20080309433 | Elastic Wave Filter and Communication Device Equipped With the Elastic Wave Filter - An elastic wave filter includes two longitudinally coupled resonator type elastic wave filter elements that are cascade connected with each other, each longitudinally coupled resonator type elastic wave filter element including three IDTs (interdigital transducers) arranged on a piezoelectric substrate in a transmitting direction of an elastic wave. In at least one of the longitudinally coupled resonator type elastic wave filter elements, electrode fingers of the IDTs that are cascade connected are arranged at a pitch that is smaller than a pitch of electrode fingers of the remaining IDT. The adverse effect of a parasitic capacitance in cascade connected wires disposed between the longitudinally coupled resonator type elastic wave filter elements is reduced so as to improve impedance matching of a cascade connected portion and to improve the VSWR characteristics of input-output terminals of the elastic wave filter. | 2008-12-18 |
| 20080309434 | Ceramic monoblock filter with metallization pattern providing increased power load handling - A ceramic monoblock filter incorporating a top face input/output port metallization pattern defining an input/output transmission line, a power load distribution bar, and a ground plate. The transmission line, power load distribution bar, and ground plate are all positioned and oriented relative to each other and two of the resonators defining the filter to define load splitting capacitors providing increased power load handling characteristics. | 2008-12-18 |
| 20080309435 | NOISE FILTER - A noise filter connected to an LC oscillator is provided. The noise filter comprises a transmission line, a DC bias circuit, and a capacitor. The transmission line is connected to the LC oscillator. The DC bias circuit is connected to the transmission line and provides a bias current. The capacitor has one end connected between the transmission line and the DC bias circuit and the other end AC grounded and provides a path to AC ground to the transmission line. A length of the transmission line is odd times that of a quarter-wavelength of a secondary harmonic wave of the LC oscillator. | 2008-12-18 |
| 20080309436 | MULTI-INPUT MULTI-OUTPUT AMPLIFIER, AN ACTIVE INDUCTOR, A FILTER AND A RADIO COMMUNICATION DEVICE - A non-inverting amplifier includes n external input terminals which receive n (n≧3) input voltage signals having a constant sum of voltages, respectively, n amplification units each including n−1 internal input terminals connected to n−1 terminals of the n external input terminals in a different combination for each of the amplification units, n−1 voltage-to-current converters which convert input voltage signals from the internal input terminals into current signals, and a load which converts an added current signal obtained by adding up the current signals into an output voltage signal, and n external output terminals which output n output voltage signals from the n amplification units. | 2008-12-18 |
| 20080309437 | Fault Interrupting and Reclosing Device - A fault interrupting and reclosing device includes a circuit interrupter coupled to an actuator. The actuator includes at least one force generating element for generating an opening force for opening the circuit interrupter and for generating a restoring force to close the circuit interrupter. The device further includes a latch to engage the actuator to hold the contacts open once opened. In a preferred arrangement, the device is provided with an automatic mode of operation including a reclose process and a non-reclosing mode of operation. The device also preferably includes a method of determining the end-of-life of a vacuum interrupter monitors characteristics and/or parameters of a fault current or vacuum interrupter operation to predict a percent of life consumed with each fault current interruption operation. A cumulative percent of life consumed may also be determined, and an end-of-life may be predicted based upon the cumulative percent of life consumed. | 2008-12-18 |
| 20080309438 | MICRO-ELECTROMECHANICAL SYSTEM BASED SWITCHING - A current control device is disclosed. The current control device includes control circuitry and a current path integrally arranged with the control circuitry. The current path includes a set of conduction interfaces and a micro electromechanical system (MEMS) switch disposed between the set of conduction interfaces. The set of conduction interfaces have geometry of a defined fuse terminal geometry and include a first interface disposed at one end of the current path and a second interface disposed at an opposite end of the current path. The MEMS switch is responsive to the control circuitry to facilitate the interruption of an electrical current passing through the current path. | 2008-12-18 |
| 20080309439 | Hazard free screened switch using magnetic flux and glass - During the service for last more than 22 years in WAPDA the inventor experienced several fatal/non-fatal accidents due to electrocution. The victims were from WAPDA and Public as well of severe nature resulting into amputation of hands, arms and limbs of the body and indeed in many cases of electrocution resulting into death. Such accidents are indeed very shocking, painful for me to alarming degree. | 2008-12-18 |
| 20080309440 | ELECTROACOUSTIC TRANSDUCER AND MAGNETIC CIRCUIT UNIT - An electroacoustic transducer has a magnetic circuit unit including a plate-shaped yoke, first and second magnets juxtaposed on the yoke, and first and second top plates mounted on the respective tops of the first and second magnets. One end of the first magnet is magnetized to one of north and south poles. The other end of the first magnet is opposite in polarity to the one end. The second magnet is magnetized to polarities opposite to those of the first magnet. A magnetic gap is formed between the first and second top plates. | 2008-12-18 |
| 20080309441 | Spraying Device - A spraying device for spraying fragrance, pest control composition and/or a sanitising composition held within a pressurised container, the spraying device comprising a container receiving section ( | 2008-12-18 |
| 20080309442 | Semiconductor power device having a stacked discrete inductor structure - A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto. | 2008-12-18 |
| 20080309443 | INDUCTOR AND METHOD FOR PRODUCING IT - An inductor includes a coil formed by winding a metallic wire, terminal electrodes connected to the coil, a first resin which is configured to cover at least one portion of a peripheral side surface of the coil and contains a magnetic powder, and a second resin which does not contain the magnetic powder and is configured to seal the coil covered by the first resin. Thereby, it is possible to provide an inductor having a stable characteristic with an unchanging L value even when there is contact during mounting of the inductor or impact during use of an electronic device in which the inductor is installed. | 2008-12-18 |
| 20080309444 | Electrical Winding - An electrical winding contains a metallic winding conductor forming individual windings. The metallic winding conductor contains a metallic conductor and an electrically insulating material surrounding the metallic conductor. An insulation inside the electrical winding can be ensured in a targeted manner by combining an electrically insulating material with a metal oxide layer surrounding the metallic winding conductor, according to the maximum electric strength required inside the electrical winding. In this way, a reduced-size electrical winding can be produced with improved heat properties. An electrical insulation of a metallic electric conductor is further described. | 2008-12-18 |
| 20080309445 | TRANSFORMER - A transformer is provided with first and second windings that constitute a primary winding, third and fourth windings that constitute a secondary winding, and a magnetic core on which the first through fourth windings are wound. A first distance in a radial direction of a wire between the first winding and the third winding, a second distance in the radial direction of the wire between the first winding and the fourth winding, a third distance in the radial direction of the wire between the second winding and the third winding, and a fourth distance in the radial direction of the wire between the second winding and the fourth winding are substantially equal in the same turn. | 2008-12-18 |
| 20080309446 | Arrangement Comprising an Inductive Component - An arrangement has an inductive component with at least one insulating support ( | 2008-12-18 |
| 20080309447 | ELECTROMAGNETIC COIL - The electromagnetic coil according to the invention has a coil core, a winding of coil wire and two contact pins, the contact pins being secured to at least one resilient holding member and being movable relative to the coil core. The holding member is formed in a unitary manner with the coil core, and the ends of the coil wire are secured to the movable/resilient contact pins. | 2008-12-18 |
| 20080309448 | STACKED PTC THERMISTOR AND PROCESS FOR ITS PRODUCTION - A stacked PTC thermistor | 2008-12-18 |
| 20080309449 | Alarm system with two-way voice - Techniques are described for establishing a two-way voice communication session with an alarm system. The alarm system may establish a two-way voice communication session with an operator associated with a monitoring service that provides monitoring services for alarm events detected by the alarm system. The alarm system also may establish a two-way voice communication session with a notification recipient that is interested in receiving notifications associated with events detected by the alarm system. | 2008-12-18 |
| 20080309450 | Alarm system with two-way voice - Techniques are described for establishing a two-way voice communication session with an alarm system. The alarm system may establish a two-way voice communication session with an operator associated with a monitoring service that provides monitoring services for alarm events detected by the alarm system. The alarm system also may establish a two-way voice communication session with a notification recipient that is interested in receiving notifications associated with events detected by the alarm system. | 2008-12-18 |
| 20080309451 | Portable Electronic Device for Controlling and Managing Functions and/or Data of a Vehicle - The portable electronic device ( | 2008-12-18 |
| 20080309452 | Wireless power transmission system - The wireless power transmission is a system for providing wireless charging and/or primary power to electronic/electrical devices via microwave energy. The microwave energy is focused onto a device to be charged by a power transmitter having one or more adaptively-phased microwave array emitters. Rectennas within the device to be charged receive and rectify the microwave energy and use it for battery charging and/or for primary power. A communications channel is opened between the wireless power source and the device to be charged. The device to be charged reports to the power source via the channel a received beam signal strength at the rectennas. This information is used by the system to adjust the transmitting phases of the microwave array emitters until a maximum microwave energy is reported by the device to be charged. Backscatter is minimized by physically configuring the microwave array emitters in a substantially non-uniform, non-coplanar manner. | 2008-12-18 |
