51st week of 2008 patent applcation highlights part 14 |
Patent application number | Title | Published |
20080308853 | Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same - A MISFET the channel region of which is a ferromagnetic semi-conductor has a feature that the drain current can be controlled by the gate voltage and a feature that the transfer conductance can be controlled by the relative directions of magnetization in the ferromagnetic channel region and the ferromagnetic source (or the ferromagnetic drain, or both the ferromagnetic source and ferromagnetic drain). As a result, binary information can be stored in the form of the relative magnetization directions, and the relative magnetization directions are electrically detected. If the magnetism is controlled by the electric field effect of the channel region of a ferromagnetic semiconductor, the current needed to rewrite the information can be greatly reduced. Thus, the MISFET can constitute a high-performance non-volatile memory cell suited to high-density integration. | 2008-12-18 |
20080308854 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - A semiconductor memory device including a cylinder hole extended in a thickness direction of an insulating film; a capacitor configured from a lower electrode, which is formed on an inner surface of the cylinder hole, and an upper electrode, which is formed on a surface of the lower electrode via a capacitance insulating film; and a capacitance contact plug which is embedded in the insulating film and a portion thereof is exposed inside the cylinder hole so as to be electrically connected with the lower electrode due to the lower electrode covering a surface of this exposed portion, wherein the capacitance contact plug is provided by the portion, which is exposed inside the cylinder hole, being extended from a bottom portion side towards an upper portion side of the cylinder hole. | 2008-12-18 |
20080308855 | Memory devices with isolation structures and methods of forming and programming the same - Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures. | 2008-12-18 |
20080308856 | Integrated Circuit Having a Fin Structure - Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure. | 2008-12-18 |
20080308857 | Systems and Methods for Self Convergence During Erase of a Non-Volatile Memory Device - A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle. | 2008-12-18 |
20080308858 | SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS COMPRISING FLOATING GATE TRANSISTORS AND METHODS OF FORMING THE SAME - Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions. | 2008-12-18 |
20080308859 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate, and a memory cell and a peripheral circuit provided on the semiconductor substrate, the memory cell having a first insulating film, a first electrode layer, a second insulating film, and a second electrode layer provided on the semiconductor substrate in order, and the peripheral circuit having the first insulating film, the first electrode layer, the second insulating film having an opening for the peripheral circuit, and the second electrode layer electrically connected to the first electrode layer through the opening for the peripheral circuit, wherein a thickness of the first electrode layer under the second insulating film of the peripheral circuit is thicker than a thickness of the first electrode layer of the memory cell. | 2008-12-18 |
20080308860 | Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same - A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate. | 2008-12-18 |
20080308861 | DUAL GATE FINFET - A circuit has a fin supported by a substrate. A source is formed at a first end of the fin and a drain is formed at a second end of the fin. A pair of independently accessible gates are laterally spaced along the fin between the source and the drain. Each gate is formed around approximately three sides of the fin. | 2008-12-18 |
20080308862 | Mos Transistor and Method of Manufacturing a Mos Transistor - The MOS transistor ( | 2008-12-18 |
20080308863 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate. | 2008-12-18 |
20080308864 | ASYMMETRICAL MOS TRANSISTOR AND FABRICATION METHOD THEREOF AND DEVICES USING THE SAME - An asymmetrical MOS transistor having characteristics of a variable resistor and a transistor is provided. The asymmetrical MOS transistor comprises a substrate, a gate structure, a pair of spacers, a pair of offset spacers, a source region, a drain region, and an extension region. Herein, the extension region is disposed in the substrate under apportion of the gate structure and one of the pair of spacers. And, the extension region connects one of the source region or the drain region. The extension region is a heavily doping region. | 2008-12-18 |
20080308865 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a structure of a gate electrode/a high-k dielectric insulating film containing aluminum and having a dielectric constant greater than that of a silicon oxide film/the silicon oxide film/a silicon substrate, and is provided with a diffusion layer formed by diffusing an aluminum atom or an aluminum ion to the silicon oxide film or an interface between the silicon oxide film and the silicon substrate by a heat treatment. A laminated film or a mixed film of hafnium oxide and aluminum oxide having a ratio of hafnium and aluminum ranging from about 2:8 to 8:2 is used as the high-k dielectric film. The heat treatment is performed at any temperature from about 500 to 1000° C. for any period of time from about 1 to 100 seconds. | 2008-12-18 |
20080308866 | Semiconductor Device and Method for Manufacturing the Same - To provide a semiconductor device having lower junction capacitance, which can be manufactured with lower power consumption through a simpler process as compared with conventional, a semiconductor device includes a base substrate; a semiconductor film formed over the base substrate; a gate insulating film formed over the semiconductor film; and an electrode formed over the gate insulating film. The semiconductor film has a channel formation region which overlaps with the electrode with the gate insulating film interposed therebetween, a cavity is formed between a recess included in the semiconductor film and the base substrate, and the channel formation region is in contact with the cavity on the recess. | 2008-12-18 |
20080308867 | PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION - Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET. | 2008-12-18 |
20080308868 | HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF - A high voltage metal oxide semiconductor includes a doped substrate, two first isolation structures, a gate structure, a source region, a drain region, two second isolation structures, and two drift regions. The two first isolation structures are respectively disposed in the doped substrate. The gate structure is disposed between parts of the two first isolation structures on the doped substrate. The source region and the drain region are respectively disposed beside one side of each of the two first isolation structures in the doped substrate. The top surface of the second isolation structure is smaller than the bottom surface of the first isolation structure. The two drift regions are respectively disposed in the doped substrate, enclosing the source region and the drain region, the two first isolation structures and the second isolation structures. | 2008-12-18 |
20080308869 | SEMICONDUCTOR DEVICE WHICH HAS MOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. | 2008-12-18 |
20080308870 | INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE - An integrated circuit is disclosed. One embodiment provides a field-effect transistor including a gate electrode, a channel region and a first source/drain region. The gate electrode may include a main section determining a first flat band voltage between the gate electrode and the channel region and a first lateral section that is in contact with the main section and that determines a second flat band voltage between the gate electrode and the first source/drain region. The first and second flat band voltages differ by at least 0.1 eV. | 2008-12-18 |
20080308871 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region. | 2008-12-18 |
20080308872 | CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS - An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention. | 2008-12-18 |
20080308873 | Semiconductor device with discontinuous CESL structure - A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode. | 2008-12-18 |
20080308874 | Complementary Asymmetric High Voltage Devices and Method of Fabrication - An asymmetric semiconductor device ( | 2008-12-18 |
20080308875 | MASK ROM DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE MASK ROM DEVICE, AND METHODS OF FABRICATING MASK ROM DEVICE AND SEMICONDUCTOR DEVICE - A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off -cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity. | 2008-12-18 |
20080308876 | Semiconductor device and method of manufacturing the same - A semiconductor device includes a first gate structure on a first region of a substrate, the first gate structure including sequentially formed a first insulating layer pattern, a first conductive layer pattern, and a first polysilicon layer pattern doped with first impurities of a first conductivity type, a first source/drain in the first region of the substrate doped with second impurities of a second conductivity type, a second gate structure on a second region of the substrate, the second gate structure including sequentially formed a second insulating layer pattern, a second conductive layer pattern, and a second polysilicon layer pattern doped with third impurities with the first conductivity type, and a second source/drain in the second region of the substrate doped with fourth impurities having a conductivity type opposite the second conductivity. | 2008-12-18 |
20080308877 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate; a first gate insulation film formed on the semiconductor substrate; a second gate insulation film formed on the semiconductor substrate; a first gate electrode formed on the first gate insulation film and fully silicided; and a second gate electrode formed on the second gate insulation film and fully silicided, a gate length or a gate width of the second gate electrode being larger than that of the first gate electrode, and a thickness of the second gate electrode being smaller than that of the first gate electrode. | 2008-12-18 |
20080308878 | Semiconductor architecture having field-effect transistors especially suitable for analog applications - An insulated-gate field-effect transistor ( | 2008-12-18 |
20080308879 | MOS STRUCTURES WITH CONTACT PROJECTIONS FOR LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection. | 2008-12-18 |
20080308880 | SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device, may include a fin formed of a semiconductor layer protruding straight from a semiconductor substrate, the fin includes straight portion which extends in a direction in a plan view and a bent portion which extends in a direction different from the direction, the straight portion and the bent portion being continuously connected, a gate insulating film provided on side surfaces of the straight portion of the fin, a gate electrode provided on the gate insulating film, source and drain regions provided in the straight portion of the fin so as to sandwich the gate electrode, a contact region provided on the straight portion of the fin and the bent portion of the fin, the contact region being electrically connected to one of the source and drain regions, and a contact member provided on the contact region of the fin so as to in contact with both of the straight portion and the bent portion of the contact region. | 2008-12-18 |
20080308881 | Method for Controlled Formation of a Gate Dielectric Stack - The present disclosure relates to methods for forming a gate stack in a MOSFET device and to MOSFET devices obtainable through such methods. In exemplary methods described herein, a rare-earth-containing layer is deposited on a layer of a silicon-containing dielectric material. Before these layers are annealed, a gate electrode material is deposited on the rare-earth-containing layer. Annealing is performed after the deposition of the gate electrode material, such that a rare earth silicate layer is formed. | 2008-12-18 |
20080308882 | APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW - A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products. | 2008-12-18 |
20080308883 | MONITORING PATTERN FOR SILICIDE - Provided is a monitoring pattern for a silicide that may include a plurality of poly pads, a plurality of N-well regions and P-well regions, active regions, and a poly gate line. The plurality of poly pads are disposed on a semiconductor substrate. The plurality of N-well regions and P-well regions are disposed in a single line between the poly pads. The active regions are disposed on the N-well and the P-well regions. The poly gate line electrically connects the active regions to the poly pads and has a configuration permitting it to pass through the active regions a plurality of times. | 2008-12-18 |
20080308884 | Fabrication of Inlet and Outlet Connections for Microfluidic Chips - A method of making a fluid communication channel between a micro mechanical structure provided on a front side of a device and the back side of said device is described. It includes making the required structural components by lithographic and etching processes on said front side. Holes are then drilled from the back side of said device in precise alignment with the structures on said front side, to provide inlets and/or outlets to and/or from the micromechanical structure. | 2008-12-18 |
20080308885 | MAGNETIC RANDOM ACCESS MEMORY AND FABRICATING METHOD THEREOF - A magnetic random access memory including a substrate, a first conductor layer, a magnetic layer, an insulating layer, a dielectric layer, two contacts and a second conductor layer is provided. The first conductor layer is disposed on the substrate. The magnetic layer is disposed on the first conductor layer. The insulating layer is disposed between the first conductor layer and the magnetic layer, and the thickness of the insulating layer is less than or equal to 1000 angstroms. The dielectric layer is disposed on the substrate and covers the magnetic layer, the insulating layer and the first conductor layer. The contacts are disposed in the dielectric layer and electrically connected to the first conductor layer and the magnetic layer respectively. The second conductor layer is disposed on the dielectric layer and includes two conductor patterns electrically connected to the corresponding contacts respectively. | 2008-12-18 |
20080308886 | Semiconductor Sensor - This application relates to a semiconductor sensor comprising a carrier that comprises a first surface and a second surface; a sensor chip attached to the first surface; attachment means on the second surface; and mould material applied over the sensor chip and the attachment means. | 2008-12-18 |
20080308887 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction, first and second selection transistors formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer, a first magnetoresistive element having one terminal electrically connected to a drain region of the first selection transistor, and the other terminal electrically connected to the first wiring layer, and a second magnetoresistive element having one terminal electrically connected to a drain region of the second selection transistor, and the other terminal electrically connected to the third wiring layer. | 2008-12-18 |
20080308888 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THEREOF - An image sensor includes a semiconductor substrate having a pixel region and a peripheral circuit region. An interlayer dielectric layer has metal wirings and a pad formed over the semiconductor substrate. A lower electrode is selectively formed over the metal wirings. A photo diode is formed over the interlayer dielectric layer of the pixel region. An upper electrode formed over the photo diode. Therefore, a vertical integration of the transistor and the photodiode may approach a fill factor to 100%, and provide higher sensitivity, implement more complicated circuitry without reducing sensitivity in each unit pixel, improve the reliability of the image sensor by preventing crosstalk, etc., between the pixels, and improve light sensitivity by increasing the surface area of the photo diode in the unit pixel. | 2008-12-18 |
20080308889 | Image sensing module and method for packaging the same - An image sensing module and a method for packaging the same are disclosed. Meanwhile, the packaging method includes the steps of a) providing a substrate; b) forming plural passive devices on the substrate; c) adhering a chip on the substrate and bonding thereon; d) providing a ring frame, wherein the ring frame includes an opening window and plural pillars for contacting with the substrate; e) adhering a glass piece on the opening window to form a lid assembly; f) covering the lid assembly on the substrate, wherein the plural pillars contacting with the substrate, the plural passive devices and the chip are covered by the lid assembly, and plural gaps are formed between the ring frame and edges of the substrate; and g) filling a filler into the plural gaps to seal the plural passive devices and the chip in the lid assembly and the substrate. | 2008-12-18 |
20080308890 | BACK-ILLUMINATED TYPE IMAGING DEVICE AND FABRICATION METHOD THEREOF - Light is illuminated from a back-surface side of a silicon substrate | 2008-12-18 |
20080308891 | ULTRA LOW DARK CURRENT PIN PHOTODETECTOR - A photodetector and a method for fabricating a photodetector. The photodetector may include a substrate, a buffer layer formed on the substrate, and an absorption layer formed on the buffer layer for receiving incident photons and generating charged carriers. An N-doped interface layer may be formed on the absorption layer, an N-doped cap layer may be formed on the N-doped interface layer, and a dielectric passivation layer may be formed above the cap layer. A P | 2008-12-18 |
20080308892 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A METAL-SEMICONDUCTOR CONTACT - A semiconductor component including a first layer ( | 2008-12-18 |
20080308893 | IMAGERS WITH CONTACT PLUGS EXTENDING THROUGH THE SUBSTRATES THEREOF AND IMAGER FABRICATION METHODS - Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors, and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Imagers with image sensing elements and transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such imagers. | 2008-12-18 |
20080308894 | Electro-Optical Apparatus and a Circuit Bonding Detection Device and Detection Method Thereof - This invention provides a circuit bonding detection device, a detection method thereof and an electro-optical apparatus incorporating the circuit bonding detection device. The circuit bonding detection device includes a substrate, a circuit module, a set of sensors, and a detection unit. A plurality of contact pads is disposed on the substrate. The circuit module includes a plurality of conductive bumps corresponding to the contact pads. The sensors are disposed on two sides of at least one of contact pads or of the corresponding conductive bumps. The detection unit is electrically coupled with the set of sensors and transmits a fault signal when at least one of the contact pads and the corresponding conductive bumps deforms and contacts the sensors. | 2008-12-18 |
20080308895 | Semiconductor device - A semiconductor device and fabricating method thereof are provided. A dual gate oxide layer is formed by thermal oxidation after carrying out a prescribed pre-processing on an STI edge, which results in a high quality oxide layer by thermal oxidation and a uniformly maintained gate oxide layer thickness of a high voltage device area. The present invention includes a semiconductor substrate divided into an active area and an inactive area, the active area including a high voltage device area and a low voltage device area; a device isolation layer on the inactive area of the semiconductor substrate; and a gate oxide layer on the high voltage device area of the semiconductor substrate, the gate oxide layer having a uniform thickness. | 2008-12-18 |
20080308896 | Integrated circuit device comprising a gate electrode structure and corresponding method of fabrication - The present invention provides an integrated circuit device comprising a semiconductor substrate and a gate electrode structure on the semiconductor substrate having at least one insulating layer of dielectric material on said semiconductor substrate and a metal layer on said at least one insulating layer, said metal layer containing niobium (Nb), vanadium (V), chromium (Cr), tungsten (W) and/or molybdenum (Mo). | 2008-12-18 |
20080308897 | Substrate for manufacturing semiconductor device and manufacturing method thereof - A substrate with which a semiconductor device with excellent electric characteristics and high reliability can be manufactured is provided. An aspect of the invention is a method for manufacturing a substrate for manufacturing a semiconductor device: a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are stacked in this order over a surface of a semiconductor substrate by a thermal CVD method, and then a weakened layer is formed at a given depth of the semiconductor substrate; the semiconductor substrate and a substrate having an insulating surface are arranged to face each other, and the second silicon oxide film provided for the semiconductor substrate and a supporting substrate are bonded to each other; and the semiconductor substrate is separated at the weakened layer by heat treatment, whereby a semiconductor film separated from the semiconductor substrate is left over the substrate having the insulating surface. | 2008-12-18 |
20080308898 | Plasma Excited Chemical Vapor Deposition Method Silicon/Oxygen/Nitrogen-Containing-Material and Layered Assembly - A method for producing a layer arrangement is disclosed. A layer of oxygen material and nitrogen material is formed over a substrate that has a plurality of electrically conductive structures and/or over a part of a surface of the electrically conductive structures. The layer is formed using a plasma-enhanced chemical vapor deposition process with nitrogen material being supplied during the supply of silicon material and oxygen material by means of an organic silicon precursor material. The layer of oxygen material and nitrogen material is formed in such a manner that an area free of material remains between the electrically conductive structures. An intermediate layer including an electrically insulating material is formed over the layer of oxygen material and nitrogen material. A covering layer is selectively formed over the intermediate layer such that the area free of material between the electrically conductive structures is sealed from the environment and forms a cavity. | 2008-12-18 |
20080308899 | TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16. | 2008-12-18 |
20080308900 | ELECTRICAL FUSE WITH SUBLITHOGRAPHIC DIMENSION - A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool and the widths of the two neck portions are sublithographic dimensions. The image on a photoresist is subsequently transferred into an underlying semiconductor layer to form an electrical fuse. The fuselink contains a constructive interference portion having a first width which is substantially the same as the critical dimension of the lithography tool and two neck portions having sublithographic widths. The inventive electrical fuse may be programmed with less voltage bias, current, and energy compared to prior art electrical fuses. | 2008-12-18 |
20080308901 | Integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof - An integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof. In an embodiment, the integrated circuit includes a metal layer that has at least one fuse. A passivation layer is deposited over the metal layer. The passivation layer has a thickness that is less than 4,500 angstroms in order to enable laser programming of the at least one fuse without having to etch the passivation layer in the area of the at least one fuse prior to laser programming. In embodiments, the passivation layer has a thickness that is in a range of about 2,000 angstroms to about 4,000 angstroms, and the metal layer includes copper metal conductors that are protected by a barrier metal such as, for example, titanium nitride (TiN) or silicon nitride (SiN). | 2008-12-18 |
20080308902 | SEMICONDUCTOR DEVICE - This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connecting between the contact plug and the switching transistor; a trench formed around the ferroelectric capacitor; and a barrier film filling in the trench and provided on a side surface of the ferroelectric capacitor and on an upper surface of the interlayer dielectric film, the barrier film suppressing percolation of hydrogen, wherein a thickness of the barrier film on the side surface of the ferroelectric capacitor is larger than a thickness of the barrier film on the upper surface of the interlayer dielectric film. | 2008-12-18 |
20080308903 | POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 2008-12-18 |
20080308904 | P-DOPED REGION WITH IMPROVED ABRUPTNESS - A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region. | 2008-12-18 |
20080308905 | SEMI-CONDUCTOR DEVICE, AND METHOD OF MAKING THE SAME - A semiconductor device and a method for manufacturing the device are disclosed. The device, and the method for making the device, includes the steps of forming a gate oxide film on a semiconductor substrate; forming a gate poly silicon layer on the gate oxide film; and implanting deuterium ions over the semiconductor substrate including the gate poly silicon layer. | 2008-12-18 |
20080308906 | GaN SUBSTRATE, SUBSTRATE WITH EPITAXIAL LAYER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING GaN SUBSTRATE - A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface. | 2008-12-18 |
20080308907 | PLANAR NONPOLAR m-PLANE GROUP III NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction. | 2008-12-18 |
20080308908 | Nitride semiconductor device and method for producing nitride semiconductor device - A nitride semiconductor device of the present invention includes: a nitride semiconductor laminated structure comprising an n type first layer, a second layer containing a p type dopant laminated on the first layer, and an n type third layer laminated on the second layer, each layer of the nitride semiconductor laminated structure made of a group III nitride semiconductor, and the nitride semiconductor laminated structure formed with a first trench and a second trench, the first trench penetrating the second layer from the third layer and reaching at least the first layer, and the second trench having a side wall extending from the first, second, to third layers and being different from the first trench; a surface insulating film containing at least silicon nitride formed such that the surface insulating film covers the surface of the first trench; a gate insulating film formed on the side wall of the second trench such that the gate insulating film extends over the first, second, and third layers; and a gate electrode formed such that the gate electrode is opposed to the side wall of the second trench with the gate insulating film sandwiched between the gate electrode and the side wall. | 2008-12-18 |
20080308909 | EPITAXIAL WAFERS, METHOD FOR MANUFACTURING OF EPITAXIAL WAFERS, METHOD OF SUPPRESSING BOWING OF THESE EPITAXIAL WAFERS AND SEMICONDUCTOR MULTILAYER STRUCTURES USING THESE EPITAXIAL WAFERS - A technique for suppressing the bowing of an epitaxial wafer is provided. The epitaxial wafer is prepared by successively epitaxially growing a target group III-nitride layer, an interlayer and another group III-nitride layer on a substrate with a buffer layer. The interlayer is mainly composed of a mixed crystal of GaN and InN expressed in a general formula (Ga | 2008-12-18 |
20080308910 | SEMINCONDUCTOR DEVICE INCLUDING THROUGH-WAFER INTERCONNECT STRUCTURE - Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may comprise a substrate having a first surface and a second, opposing surface, and a through-wafer interconnect extending into the first surface of the substrate. The through-wafer interconnect may include an electrically conductive material extending from the first surface of the substrate to the second, opposing surface of the substrate. The through-wafer interconnect may also include a first dielectric material disposed between the electrically conductive material and the substrate and extending from the second, opposing surface of the substrate to the first portion of the conductive material. Additionally, the through-wafer interconnect may include a second dielectric material disposed over a portion of the electrically conductive material and exhibiting a surface that defines a blind aperture extending from the first surface toward the second, opposing surface. | 2008-12-18 |
20080308911 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device with improved reliability in which a defect stemming from an end portion of a semiconductor layer provided in an island shape is prevented, and a manufacturing method thereof. Over a substrate having an insulating surface, an island-shaped semiconductor layer is formed, a first alteration treatment is performed, a first insulating film is formed on a surface of the island-shaped semiconductor layer, the first insulating film is removed, a second alteration treatment is performed on the island-shaped semiconductor from which the first insulating film is removed, a second insulating film is formed on a surface of the island-shaped semiconductor layer, and a conductive layer is formed over the second insulating film. An upper end portion of the island-shaped semiconductor layer has curvature by the first alteration treatment and the second alteration treatment. | 2008-12-18 |
20080308912 | EMI SHIELDED SEMICONDUCTOR PACKAGE - An EMI shielded semiconductor package is provided. The package includes a substrate and a chip disposed on the substrate. The chip is electrically connected to the substrate by a plurality of bonding wires. At least one shielding conductive block is formed on the substrate and electrically connected to the ground trace of the substrate. A sealant is formed on the substrate and covers the chip, bonding wires and the shielding conductive block. The sealant has a side surface to expose a surface of the shielding conductive block. A layer of conductive film is formed on the outer surface of the sealant and covers the exposed surface of the shielding conductive block thereby shielding the chip from electromagnetic interference. | 2008-12-18 |
20080308913 | STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove. | 2008-12-18 |
20080308914 | CHIP PACKAGE - A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip is flipped on and electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first chip, and each first bonding wire passes through the opening. The component is disposed over the first rear surface. The first adhesive layer adhered between the first rear surface and the component includes a first B-staged adhesive layer adhered on the first rear surface and the component and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. The molding compound is disposed on the circuit substrate. | 2008-12-18 |
20080308915 | CHIP PACKAGE - A chip package including a circuit substrate, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface, a first rear surface and first bonding pads, the first rear surface is adhered on the circuit substrate and the first chip is electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first bonding pads of the first chip. The component is disposed over the first active surface of the first chip. The first adhesive layer adhered between the first active surface and the component without covering the first bonding pads and includes a first B-staged adhesive layer adhered on a portion of the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. | 2008-12-18 |
20080308916 | CHIP PACKAGE - A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier. | 2008-12-18 |
20080308917 | EMBEDDED CHIP PACKAGE - An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure. | 2008-12-18 |
20080308918 | SEMICONDUCTOR PACKAGE WITH PASSIVE ELEMENTS - The semiconductor package includes a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect at least one first via patterns to at least one second via patterns; a plurality of passive elements formed on the top surface of the plate having a connection wiring formed thereon; a semiconductor chip having a plurality of bonding pads attached to a bottom surface of the plate and electrically connected to the first via patterns; and a plurality of external connection terminals each of which being attached to each of the second via pattern on the bottom surface of the plate. | 2008-12-18 |
20080308919 | HOLLOW SEALING STRUCTURE AND MANUFACTURING METHOD FOR HOLLOW SEALING STRUCTURE - A manufacturing method for a hollow sealing structure, includes, a process for filling a recessed portion in a principal surface of a substrate with a first sacrificial layer, a process for forming a functional element portion on the principal surface of the substrate, a process for forming a second sacrificial layer on the functional element portion so as to be connected to a part of the first sacrificial layer, a process for forming a covering portion over respective surfaces of the first and second sacrificial layers, a process for circulating a fluid for sacrificial layer removal through an opening in the covering portion in contact with the first sacrificial layer, thereby removing the first and second sacrificial layers, and a process for closing the opening. | 2008-12-18 |
20080308920 | SYSTEM AND METHOD OF FABRICATING MICRO CAVITIES - A system and method for manufacturing micro cavity packaging enclosure at the wafer level using MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed from epoxy-bonded single-crystalline silicon wafer as its cap, epoxy and deposited metal or insulator as at least part of its sidewall, on substrate wafers. | 2008-12-18 |
20080308921 | MOLDED RECONFIGURED WAFER, STACK PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE STACK PACKAGE - A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other. | 2008-12-18 |
20080308922 | METHOD FOR PACKAGING SEMICONDUCTORS AT A WAFER LEVEL - A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming in a material disposed on the surface portion of the semiconductor wafer device-exposing openings to exposed the devices and electrical contacts pads openings to expose electrical contact pads for devices; mounting a rigid dielectric layer over the formed material, such rigid material being suspended over the device exposing openings in the material and over the electrical contacts pads openings in the material; and forming electrical contact pad openings in portions of the rigid dielectric layer disposed over electrical contact pads of the devices with other portions of the rigid dielectric layer remaining suspended over the device exposing openings in the material. | 2008-12-18 |
20080308923 | HIGH PERFORMANCE CHIP CARRIER SUBSTRATE - A multilayer chip carrier with increased space for power distribution PTHs and reduced power-related noise. In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from near-edge signal pads at the first fanout layer, remaining signal pads are moved closer to the edge of the chip footprint. At the voltage layer below the first fanout layer, the remaining signal pads are moved again, closer to the edge of the chip footprint. In the second fanout layer, below the voltage layer, the remaining signal pads escape. The region where signal pads are moved provides increased space for power PTHs. | 2008-12-18 |
20080308924 | Circuit Module Having Force Resistant Construction - Impact resistant circuit modules are disclosed for enclosing a die having a sensor area. Preferred modules include a flexible circuit and a die coupled thereto. The flexible circuit is preferably folded over compressible material to help absorb applied forces. A gap may be provided between sides of the die and the compressible material to help prevent peeling. A metal reinforcing layer may be bonded to the back of the die. A low modulus material including a patterned gap underneath the die may be used to absorb forces. A dry film adhesive may be placed between at least part of the upper surface of the die and the flexible circuit, preferably to provide further point impact resistance and protection. High and low modulus material may be combined in ruggedizing structures. Consumer devices employing such circuit modules are also taught, as well as module construction methods. | 2008-12-18 |
20080308925 | FABRICATING PROCESS AND STRUCTURE OF THERMAL ENHANCED SUBSTRATE - A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. First, a metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks. | 2008-12-18 |
20080308926 | Heat dissipation package structure and method for fabricating the same - A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome. | 2008-12-18 |
20080308927 | Semiconductor device with heat sink plate - A semiconductor chip is mounted on an upper surface of the heat sink plate that is provided with a plurality of heat releasing terminals on a lower surface of the heat releasing. A plurality of electric signal terminals are regularly disposed in a lattice-like manner around the heat sink plate. Lower end surfaces of the electric signal terminals and the heat releasing terminals are exposed from and sealed with a sealing resin. The heat sink plate is formed as an integrated body including a protruding portion that protrudes from a central portion of an upper surface and supports the semiconductor chip, a plurality of supporting portions that are positioned around a rear surface of the protruding portion so as to support the protruding portion and that are exposed at a rear surface of the sealing resin, the plurality of heat releasing terminals, and a thin-walled portion that is recessed from lower end surfaces of the supporting portions and the heat releasing terminals. Lower surfaces of the protruding portion and the thin-walled portion are covered with the sealing resin. The plurality of supporting portions are disposed so that they are continuous with the protruding portion and symmetrical to each other around the protruding portion. A degree of freedom is improved in board wiring below the heat sink plate in a land grid array type package. | 2008-12-18 |
20080308928 | Image sensor module with a three-dimensional die-stacking structure - This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module. | 2008-12-18 |
20080308929 | SEMICONDUCTOR DEVICE, CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed. | 2008-12-18 |
20080308930 | SEMICONDUCTOR DEVICE MOUNTING STRUCTURE, MANUFACTURING METHOD, AND REMOVAL METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device mounting structure includes a semiconductor device whose electrodes are aligned on its one main face; a circuit board having board electrodes electrically connected to the electrodes of the semiconductor device by solder bumps; and curable resin applied between at least the side face of the semiconductor device and the circuit board. Multiple types of thermally expandable particles with different expansion temperatures are mixed in this curable resin. This structure offers the semiconductor device mounting structure that is highly resistant to impact and suited for mass production, its manufacturing method, and a removal method of the semiconductor device. In addition, this structure facilitates repair and reworking, leaving almost no adhesive residue on the circuit board after repair. Stress applied to the circuit board during repair can also be minimized. | 2008-12-18 |
20080308931 | Electronic Structures Including Barrier Layers Defining Lips - Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask. | 2008-12-18 |
20080308932 | SEMICONDUCTOR PACKAGE STRUCTURES - A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. | 2008-12-18 |
20080308933 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT CONNECTION STRUCTURES - An integrated circuit package system is provided including forming an external interconnect having a tip without a die-attach paddle; mounting a first integrated circuit device structure having a conductive ball over the tip; connecting a first wire between the first integrated circuit device structure and under the tip; and encapsulating the first integrated circuit device structure, the first wire, and the external interconnect with the external interconnect partially exposed. | 2008-12-18 |
20080308934 | SOLDER BUMP INTERCONNECT FOR IMPROVED MECHANICAL AND THERMO-MECHANICAL PERFORMANCE - An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.5:1 to 0.95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.80:1. | 2008-12-18 |
20080308935 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter. | 2008-12-18 |
20080308936 | METHOD AND STURCTURE FOR SELF-ALIGNED DEVICE CONTACTS - Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 2008-12-18 |
20080308937 | COPPER-FREE SEMICONDUCTOR DEVICE INTERFACE AND METHODS OF FABRICATION AND USE THEREOF - Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature. | 2008-12-18 |
20080308938 | Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure - An under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure are provided. The under bump metallurgy structure includes an adhesion layer, a barrier layer and a wetting layer. The adhesion layer is disposed on a bonding pad of a wafer. The barrier layer is disposed on the adhesion layer. The wetting layer is disposed on the barrier layer. The adhesion layer, the barrier layer and the wetting layer are respectively made of nickel with boron, cobalt and gold. | 2008-12-18 |
20080308939 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first group wiring layers laminated on a substrate, and each of the first group wiring layers having a wire formed with a first minimum wire width and a main dielectric film portion; and a plurality of second group wiring layers laminated on a top layer of the plurality of first group wiring layers and each of the second group wiring layers having a wire formed with a second minimum wire width greater than the first minimum wire width and a main dielectric film portion, wherein a main dielectric film portion in a bottom layer of the plurality of second group wiring layers has a relative dielectric constant which is substantially identical to a relative dielectric constant of main dielectric film portions of the other second group wiring layers, and Young's modulus of the main dielectric film portion in the bottom layer of the plurality of second group wiring layers is smaller than those of the main dielectric film portions of the other second group wiring layers and larger than those of main dielectric film portions of the first group wiring layers. | 2008-12-18 |
20080308940 | LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES - A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface. | 2008-12-18 |
20080308941 | HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING - An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal. | 2008-12-18 |
20080308942 | SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER - Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased. | 2008-12-18 |
20080308943 | WIRING STRUCTURE AND SEMICONDUCTOR DEVICE, AND THEIR FABRICATION METHODS - A fabrication method for a wiring structure of the present invention includes: a process of forming a conductive wiring layer; a process of forming a wiring pattern on the wiring layer; a process of forming an insulative wiring interlayer film between wires of the wiring pattern; and a process of forming a plurality of longitudinal hole-shaped fine pores in the wiring interlayer film in a thickness direction of the wiring interlayer film by etching with a mask including one of nano-particles and material including nano-particles. | 2008-12-18 |
20080308944 | Method for eliminating duo loading effect using a via plug - Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug. | 2008-12-18 |
20080308945 | Semiconductor Integrated Circuit - A semiconductor integrated circuit according to an example of the present invention includes a first interconnect extending in a first direction, a second interconnect arranged over the first interconnect and extending in a second direction intersecting the first direction, a first via for connecting a first contact part of the first interconnect and a second contact part of the second interconnect, and a second via for connecting a third contact part of the first interconnect and a fourth contact part of the second interconnect. The first and third contact parts are arranged by being aligned in the first direction, and the second and fourth contact parts are arranged by being aligned in the second direction. | 2008-12-18 |
20080308946 | SEMICONDUCTOR ASSEMBLIES, STACKED SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES AND STACKED SEMICONDUCTOR DEVICES - Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns. | 2008-12-18 |
20080308947 | Die offset die to die bonding - A semiconductor die is provided on a spacer, the die having first and second opposite edges which extend beyond respective first and second opposite edges of the spacer, the first edge of the die extending beyond the first edge of the spacer to a lesser extent than the second edge of the die extends beyond the second edge of the spacer. Furthermore, a first semiconductor die has a plurality of bond pads thereon, a second semiconductor die has a plurality of bond pads thereon, and a substrate has a plurality of bond pads thereon. Each of a first plurality of wires connects a bond pad on the first semiconductor die with a bond pad on the second semiconductor die, and each of a second plurality of wires connects a bond pad on the second semiconductor die with a bond pad on the substrate. | 2008-12-18 |
20080308948 | WAFER-TO-WAFER ALIGNMENTS - Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10 | 2008-12-18 |
20080308949 | FLIP CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip. | 2008-12-18 |
20080308950 | Semiconductor package and method for manufacturing thereof - A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration. | 2008-12-18 |
20080308951 | Semiconductor package and fabrication method thereof - A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes providing a carrier board; forming a plurality of metal bumps on the carrier board; covering on the carrier board a resist layer having openings for exposure of the metal bumps, the openings being smaller than the metal bumps in width such that a metal layer is formed in the openings, the metal layer having extension circuits and extension pads and bonding pads formed on respective ends of the extension circuits; removing the resist layer; electrically connecting at least one semiconductor chip to the bonding pads; forming an encapsulant on the carrier board to encapsulate the semiconductor chip; and removing the carrier board and the metal bumps to expose the metal layer. Therefore, the extension pads of the exposed metal layer can be electrically connected to an external device through a conductive material in subsequent processes, and the extension circuits can be disposed flexibly in accordance with the degree of integration of the chip, so as to reduce the electrical connection path between the chip and the extension circuits. | 2008-12-18 |
20080308952 | Method for Reliably Positioning Solder on a Die Pad for Attaching a Semiconductor Chip to the Die Pad and Molding Die for Solder Dispensing Apparatus - The rotational orientation of a die pad about its longitudinal axis is determined. The desired rotational orientation of a semiconductor chip to be attached to the die pad is determined. A molding die is provided which comprises a body with a cavity disposed in a bottom surface. The rotational orientation of the body of the molding die about its longitudinal axis is determined. The cavity is positioned in the body of the molding die with a rotational orientation such that the cavity is rotated with respect to the molding die by an angle corresponding to the desired rotational orientation of the semiconductor chip with respect to the die pad. | 2008-12-18 |