50th week of 2010 patent applcation highlights part 26 |
Patent application number | Title | Published |
20100315823 | LIGHT-EMITTING DEVICE PRESSURE RING STRUCTURE - A light-emitting device pressure ring structure includes a mounting base for mounting, a circuit board accommodated in the mounting base and having electrode pins connectable to an external power source, a holder member insertable in the mounting base, a light-emitting unit fixedly mounted in the holder member with a bottom heat sink thereof suspending outside the holder member and tubular electrodes thereof connectable to the electrode pins of the circuit board for power input, and a pressure ring cap detachably threaded onto the mounting base to hold down the holder member and to keep the heat sink of the light-emitting unit outside the mounting base for quick dissipation of waste heat from the light-emitting devices of the light-emitting unit. | 2010-12-16 |
20100315824 | DIVIDED LED LAMP - A divided LED lamp includes an LED assembly, a casing assembly, LED electronics, power and signal cables, a control panel including a display screen and operation buttons, and a bracket for mounting the lamp. The casing assembly includes a first casing member and a second casing member. At least one cable tube is formed between the first casing member and the second casing member. The power and signal cables that connect the LED assembly received in the first casing member and the LED electronics received in the second casing member are received through the cable tube. This arrangement allows the LED assembly and the LED electronics to be received in individual and independent casing members and are associated with respective individual heat dissipation fins or heat radiators, so as to realize high efficiency of heat dissipation, stabilized operation, and extended lifespan. | 2010-12-16 |
20100315825 | LIGHT PROJECTION APPARATUS AND LIGHTING APPARATUS - A light projection apparatus that projects light onto an arbitrary space and an object set in the space, comprising: projection light data generating means for generating projection light data for specifying the projection light; projection range setting means for setting a projection range onto which the light is projected and a non-projection range onto which the light is not projected in accordance with an operation of a user; projection data correcting means for correcting the projection light data so as to project the light onto the projection range set by the projection range setting means; projection light correction data drawing means for performing drawing processing for projection light correction data obtained by correcting the projection light data by the projection data correcting means; and light projecting means for projecting the light by using projection light drawing data generated by the projection light data drawing means. Accordingly, by a simple operation, the light can be projected with the shape desired by the user. | 2010-12-16 |
20100315826 | DISTRIBUTED LIGHTING ASSEMBLY - The lighting assembly ( | 2010-12-16 |
20100315827 | VEHICLE LIGHT - The invention relates to a motor vehicle lighting fixture which comprises at least: a light source comprising at least one LED; a light-transmitting part that is arranged such that it receives light from the light source; and a reflector that is arranged such that it reflects that portion of the light from the light source that passes through the light-transmitting part and couples it out to the front of the lighting fixture, a reflection portion and a refraction portion being provided within the light-transmitting part, wherein said reflection portion deflects the light issuing from the light source through total reflection in one direction that is substantially perpendicular to the optical axis of the reflector, whereas the refraction portion couples out the light in the direction of the reflector. | 2010-12-16 |
20100315828 | LIGHT SOURCE AND VEHICLE LAMP - A light source apparatus for vehicle lamps and particularly vehicle headlights can include a plurality of LED elements can be mounted in a cavity located on a base surface or on a base. Each of the LED elements can be arranged in such a manner as to form an emission shape and a brightness distribution that is suited for a light distribution pattern, and especially a light distribution pattern for a vehicle headlight. | 2010-12-16 |
20100315829 | LIGHT EMITTING MODULE AND AUTOMOTIVE HEADLAMP - A light emitting module includes: a semiconductor light emitting element; a plate-shaped light wavelength conversion ceramic that is provided so as to face the light emitting surface of the semiconductor light emitting element and that is configured to convert the wavelength of the light, which has been emitted by the semiconductor light emitting element; and a reflective film that is formed on the surface of the light wavelength conversion ceramic and that is configured to shield part of the light, which has been transmitted through the light wavelength conversion ceramic. The light wavelength conversion ceramic is composed on an inorganic material. | 2010-12-16 |
20100315830 | HEAT DISSIPATION DEVICE OF VEHICLE LAMP AND INTERPOSING ELEMENT THEREOF - A heat dissipation device of a vehicle lamp and an interposing element thereof are provided. The heat dissipation device is installed in a lamp room which is divided by the interposing element into a front partition and a rear partition. A heat sink is installed in the interposing elements. An air feeding fan is disposed in an air feeding channel of the interposing element, for drawing air in the front partition to the rear partition through the air feeding channel. Further, a back flow fan is disposed in the rear partition, for drawing air in the rear partition to the front partition through a back flow channel. Whereby, the air in the front partition is cooled down through an external air flow passing through the lamp cover. Then, the heat sink dissipates heat of the air flow with the relatively low temperature in the front partition to the rear partition. | 2010-12-16 |
20100315831 | LIGHTED OR SOUND TIP FOR MOBILITY DEVICES AND METHOD OF USING - A tip for a mobility device which is capable of providing light and/or sound to aid in the safety of the user of the mobility device. | 2010-12-16 |
20100315832 | ILLUMINATION SYSTEM AND DISPLAY DEVICE - The invention relates to an illumination system ( | 2010-12-16 |
20100315833 | THIN ILLUMINATION SYSTEM - The present invention introduces a new class of thin doubly collimating light distributing engines for use in a variety of general lighting applications, especially those benefiting from thinness. Output illumination from these slim-profile illumination systems whether square, rectangular or circular in physical aperture shape is directional, square, rectangular or circular in beam cross-section, and spatially uniform and sharply cutoff outside the system's adjustable far-field angular cone. Field coverage extends from +/−5- to +/−60-degrees and more in each meridian, including all asymmetric combinations in between, both by internal design, by addition of angle spreading film sheets, and angular tilts. Engine brightness is held to safe levels by expanding the size of the engine's output-aperture without sacrifice in the directionality of illumination. One form of the present invention has a single input light emitter, a square output aperture and the capacity to supply hundreds of lumens per engine. A second multi-segment form of the invention deploys one light emitter in each engine segment, so that total output lumens is determined by the number of segments. Both types of thin light distributing engines provide input light collimated in one meridian and a light distributing element that maintains input collimation while collimating output light in the un-collimated orthogonal meridian, in such a manner that the system's far-field output light is collimated in both its orthogonal output meridians. The present invention also includes especially structured optical films that process the engine's doubly collimated output illumination so as to increase its angular extent one or both output meridians without changing beam shape or uniformity. | 2010-12-16 |
20100315834 | LIGHT EMITTING DIODE PACKAGE, AND BACKLIGHT UNIT AND DISPLAY DEVICE USING THE SAME - A light emitting diode package may be provided that includes a light emitting diode chip and a heat sink. Heat generated from the light emitting diode chip may be radiated to the outside using the heat sink. | 2010-12-16 |
20100315835 | LEAD FRAME, LIGHT EMITTING DIODE HAVING THE LEAD FRAME, AND BACKLIGHT UNIT HAVING THE LIGHT EMITTING DIODE - An LED includes a light-emitting chip, a metal member, and a housing. The light-emitting chip generates light. The light-emitting chip is arranged on the metal member. The housing is combined with the metal member to fix the metal member. The housing has an opening portion exposing at least a portion of the light-emitting chip and the metal member. The metal member includes a base metal layer, a light-reflecting layer arranged on the base metal layer, and a protection layer arranged on the light-reflecting layer and including a metal. | 2010-12-16 |
20100315836 | Flat panel optical display system with highly controlled output - A brightness enhancing reflector to accurately control the light exiting the guide achieves accurate control of the reflected light by extracting light from a limited area of the light guide. The configuration of the reflectors used for the selective extraction determines the nature of the output light. The reflectors are preferably located on a side of the light guide opposite to an output side of the light guide and in conjunction with an electronic display. | 2010-12-16 |
20100315837 | METHOD FOR OPERATING A SWITCHING-MODE POWER SUPPLY - A method for operating a switching power supply is provided. A switching element is switched on and off by a switching signal with a variable switching frequency. A frequency bandwidth is predefined for determining average levels of a frequency spectrum of the switching signal. The switching frequency is modulated by a modulation frequency greater than a frequency bandwidth. | 2010-12-16 |
20100315838 | System and Method for Emissions Suppression in a Switch-Mode Power Supply - In one embodiment, a method of operating a switched-mode power supply that has a switch coupled to a drive signal is disclosed. The method includes deactivating the drive signal at a first instance of time, and comparing a power supply signal to a threshold after deactivating the drive signal. The method further includes activating the drive signal a variable period of time after the power supply signal crosses the threshold. | 2010-12-16 |
20100315839 | ENERGY RECOVERY SNUBBER CIRCUIT FOR POWER CONVERTERS - An energy recovery snubber circuit for use in switching power converters. The power converters may include a switch network coupled to a primary winding of an isolation transformer, and rectification circuitry coupled to a secondary winding of the isolation transformer. The energy recovery snubber circuit may include clamping circuitry that is operative to clamp voltage spikes and/or ringing at the rectification circuitry. The clamped voltages may be captured by an energy capture module, such as a capacitor. Further, the energy recovery snubber circuitry may include control circuitry operative to return the energy captured by the energy capture module to the input of the power converter. To maintain electrical isolation between a primary side and a secondary side of the isolation transformer, a second isolation transformer may be provided to return the captured energy back to the input of the power converter. | 2010-12-16 |
20100315840 | SYSTEM AND METHOD FOR INDIRECT CONTROL OF A CONVERTER OUTPUT - One embodiment of the invention relates to a power apparatus. The power apparatus includes a power converter configured to convert an input voltage to an output voltage for providing power at an output thereof to which a load is connectable. The converter can include an isolation barrier configured to electrically isolate the output and the load from an input source that provides the input voltage. The system also includes a control loop that includes indirect sense circuitry configured to indirectly derive an indication of at least one of output current and output power of the converter. The control loop is configured to control output current or output power based on the indirectly derived indication of output current or output power, respectively. | 2010-12-16 |
20100315841 | SEMICONDUCTOR DEVICE AND SWITCHING POWER SUPPLY APPARATUS - A switching power supply apparatus includes: a turn-on control circuit which generates a turn-on signal; a feedback control circuit which generates a reference voltage V | 2010-12-16 |
20100315842 | DRIVE CIRCUIT FOR SEMICONDUCTOR SWITCHING ELEMENT - A drive circuit of first and second switches includes a first series circuit having a capacitor and a primary winding of a transformer and connected to both ends of a pulse signal generator, a first secondary winding of the transformer to apply a voltage to a control terminal of the first semiconductor switch based on the pulse signal, the first secondary winding being wound in a direction opposite to the primary winding, a second secondary winding of the transformer to apply a voltage to a control terminal of the second semiconductor switch based on the pulse signal, the second secondary winding being wound in the same direction to the primary winding, and a third semiconductor switch that turns on when the pulse signal is stopped, to shorten an ON period of the first semiconductor switch. | 2010-12-16 |
20100315843 | METHOD OF DETECTION FOR OUTPUT SHORT CIRCUIT OF A FLYBACK POWER SUPPLY - Disclosed are methods of detection for output short circuit of a flyback power supply, which detect the current sense signal provided by a current sense resistor serially connected to a power switch of the flyback power supply, and thus quickly identify whether or not the flyback power supply suffers output short circuit. | 2010-12-16 |
20100315844 | Method for Operating a DC-DC Converter - A method of operating a DC-DC converter according to the current mode control is provided. A current measuring signal for determining a turn-off time of a converter switching element is supplied to a PWM controller and a voltage that is proportional to the current measuring signal is compared by a comparator to a reference voltage. When the reference voltage is exceeded, the converter switching element is turned off. | 2010-12-16 |
20100315845 | POWER SOURCE CIRCUIT AND PROJECTION DISPLAY DEVICE - A power source circuit includes a DC voltage generating section which rectifies and smoothes an input AC voltage to generate a DC voltage; a switching regulator which converts the DC voltage into an AC voltage; a transformer which lowers the AC voltage; a first switch connected between a secondary winding of the transformer, and a load; and a control section which controls on/off of the switch. The control section controls the first switch to turn off the first switch at a time of a waiting mode. | 2010-12-16 |
20100315846 | SWITCHING POWER SUPPLY AND OVER-TEMPERATURE PROTECTION METHOD - A switching power supply includes an energy-storing device, a power switch, a driving circuit and a thermal sensing device. The energy-storing device is coupled to an input power source and controlled by the power switch to increase or decrease the power therein. The power switch has a control terminal connected to the driving circuit for switching. The thermal sensing device is connected to the control terminal of the power switch and powered by the driving circuit. When sensing an operation temperature exceeding a predetermined range, the thermal sensing device disables the driving circuit. | 2010-12-16 |
20100315847 | COMPONENT FAULT DETECTION FOR USE WITH A MULTI-PHASE DC-DC CONVERTER - Provided herein are circuits, systems and methods that monitor for a fault within a multi-phase DC-DC converter. This can include monitoring the channels of the DC-DC converter for way out of balance (WOB) conditions, and monitoring for a component fault in dependence on detected WOB conditions. A fault can be detected if, during a predetermined period of time, one of the WOB conditions occurs at least a specified amount of times more than another one of the WOB conditions. The DC-DC converter and/or another circuit can be shut-down in response to a fault being detected. Additionally, or alternatively, a component fault detection signal can be output in response to a fault being detected. | 2010-12-16 |
20100315848 | Time Domain Voltage Step Down Capacitor Based Circuit - A time domain voltage step down capacitor based circuit has an oscillating circuit for generating a clock signal. The circuit also has a capacitor based charge pump circuit for receiving the clock signal and an input voltage signal having an input current and generates an output voltage signal, less than the input voltage signal and an output current greater than the input current. The circuit further comprises a comparator circuit for receiving the output voltage signal, as a first input signal thereto, and a reference voltage signal as a second input signal thereto and compares the first input signal to the second input signal and generates a control signal in response thereto. Finally the control signal is supplied to the oscillating circuit to control the generating of the clock signal | 2010-12-16 |
20100315849 | POWER SUPPLY CONTROL - Systems and methods for operating an uninterruptable power supply are provided. The uninterruptable power supply may include a rectifier that has a transistor and an inductor. The uninterruptable power supply may also include a controller. A current sensor can be configured to detect inductor current and to provide a detected inductor current value to the controller to generate a current error value based and to generate a pulse width modulation control signal based in part on the current error value. The controller can apply the pulse width modulation control signal to the transistor to adjust a switching frequency of the transistor. | 2010-12-16 |
20100315850 | POWER INVERTER - A power inverter is provided for converting DC power into AC power. The inverter may be operable to couple to two or more transformer modules each operable to convert at least a portion of the DC power to at least a portion of the AC power. In one embodiment, two or more transformer modules are removably coupled to the inverter. In an alternative embodiment, the inverter is capable of electrically coupling to an externally-housed transformer module. In an alternative embodiment, the inverter may include two or more transformer modules hard-wired into the device. The inverter may include an AC safety plug for releasably connecting to an AC power network and outputting AC power. The inverter may include one or more sensors configured to detect one or more properties of the AC power network for the purposes of determining whether a connection to the power network should be established. | 2010-12-16 |
20100315851 | CIRCUIT ARRANGEMENT AND METHOD FOR SUPPLYING A CAPACITIVE LOAD - A circuit arrangement (S) for supplying a load (P), whose essential electric property is capacitance, from a DC voltage source (U | 2010-12-16 |
20100315852 | MEMORY AND STORAGE DEVICE UTILIZING THE SAME - A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory. | 2010-12-16 |
20100315853 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit including a memory macro, such as a DRAM, an SRAM, a ROM, a flash memory, or the like, and a logic circuit, memory macro test-dedicated pads are provided on the memory macro, whereby an increase in the number of normal pads is reduced or prevented to reduce or prevent an increase in the chip area. Moreover, by fixing arrangement (positions) of the pads provided on the memory macro between memory macros of a plurality of memory macro-including semiconductor integrated circuits, a single common probe card for a single chip can be used for the memory macro-including semiconductor integrated circuits, thereby providing low-cost testing. | 2010-12-16 |
20100315854 | MAGNETIC RANDOM ACCESS MEMORY AND INITIALIZING METHOD FOR THE SAME - A domain wall motion type MRAM has: a magnetic recording layer | 2010-12-16 |
20100315855 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 2010-12-16 |
20100315856 | HIGH-DENSITY NON-VOLATILE READ-ONLY MEMORY ARRAYS AND RELATED METHODS - In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values. | 2010-12-16 |
20100315857 | RESISTANCE CHANGE MEMORY - A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectifying element connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a voltage to change a resistance of the memory element between first and second values reversibly. The rectifying element is a diode including an anode layer, a cathode layer and an insulating layer therebetween. | 2010-12-16 |
20100315858 | MEMORY ARCHITECTURE WITH A CURRENT CONTROLLER AND REDUCED POWER REQUIREMENTS - Disclosed is a memory architecture comprising at least one memory bit cell and at least one read bit line whose voltage is controlled and changed by a current from a current controller. Each memory bit cell has a storage mechanism, a controlled current source, and a read switch. The controlled current source in each memory bit cell is electrically connected to the read bit line through the read switch. The current from the current controller that controls and changes the read bit line voltage flows through the controlled current source in the memory bit cell. The value of this current is determined by a function of a difference between the voltage on the storage mechanism in the memory bit cell and a reference voltage from a reference voltage input to the current controller. In some versions an indicator is provided for indicating when to stop the current in the controlled current source that controls a voltage change on one of the read bit lines. The indicator has an on and an off condition and a switch is provided for stopping the current in the controlled current source when the indicator is activated in the on condition. The current in the controlled current source is stopped when the voltage change on the read bit line is greater than a predetermined threshold. | 2010-12-16 |
20100315859 | Eight-Transistor SRAM Memory with Shared Bit-Lines - An integrated circuit structure includes a first static random access memory (SRAM) cell including a first read-port and a first write-port; and a second SRAM cell including a second read-port and a second write-port. The first SRAM cell and the second SRAM cell are in a same row and arranged along a row direction. A first word-line is coupled to the first SRAM cell. A second word-line is coupled to the second SRAM cell. A read bit-line is coupled to the first SRAM cell and the second SRAM cell, wherein the read bit-line extends in a column direction perpendicular to the row direction. A write bit-line is coupled to the first SRAM cell and the second SRAM cell. | 2010-12-16 |
20100315860 | INTEGRATED CIRCUIT WITH A MEMORY MATRIX WITH A DELAY MONITORING COLUMN - An integrated circuit has a matrix of rows and columns of cells ( | 2010-12-16 |
20100315861 | SRAM CELL AND SRAM DEVICE - In an SRAM cell including a first to a fourth semiconductor thin plates which stand on a substrate and are arranged in parallel to each other, on each of the four semiconductor thin plates being formed a first four-terminal double-gate FET with a first conductivity type; a second and a third four-terminal double-gate FETs which are connected in series with each other and have a second conductivity type; a fourth and a fifth four-terminal double-gate FETs which are connected in series with each other and have the second conductivity type; a sixth four-terminal double-gate FET with the first conductivity type, wherein the third and the fourth four-terminal double-gate FETs form select transistors, and the first, the second, the fifth and the sixth four-terminal double-gate FETs form a CMOS inverter, logic signal input gates of the first and the sixth four-terminal double-gate FETs are arranged on the side facing the second and the third semiconductor thin plates, respectively, while threshold voltage control gates of the second to the fifth four-terminal double-gate FETs are arranged on the sides facing each other and are commonly connected to a first bias line. Threshold voltage control gates of the first and the sixth four-terminal double-gate FETs are commonly connected to a second bias line. A word line, the first bias line and the second bias line are arranged orthogonally to the direction of arrangement of the first to the fourth semiconductor thin plates. | 2010-12-16 |
20100315862 | Stable SRAM Cell - SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor. | 2010-12-16 |
20100315863 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 2010-12-16 |
20100315864 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element includes: a magnetization free layer having a first plane and a second plane located on the opposite side from the first plane, and having a variable magnetization direction; a magnetization pinned layer provided on the first plane side of the magnetization free layer, and having a pinned magnetization direction; a first tunnel barrier layer provided between the magnetization free layer and the magnetization pinned layer; a second tunnel barrier layer provided on the second plane of the magnetization free layer; and a non-magnetic layer provided on a plane on the opposite side of the second tunnel barrier layer from the magnetization free layer. The magnetization direction of the magnetization free layer is variable by applying current between the magnetization pinned layer and the non-magnetic layer, and a resistance ratio between the first tunnel barrier layer and the second tunnel barrier layer is in a range of 1:0.25 to 1:4. | 2010-12-16 |
20100315865 | DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT - A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching. | 2010-12-16 |
20100315866 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 2010-12-16 |
20100315867 | SOLID-STATE MEMORY DEVICE, DATA PROCESSING SYSTEM, AND DATA PROCESSING DEVICE - A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result. | 2010-12-16 |
20100315868 | SEMICONDUCTOR DEVICE INCLUDING STORAGE DEVICE AND METHOD FOR DRIVING THE SAME - A structure of a storage device which can operate memory elements utilizing silicide reaction using the same voltage value for writing and for reading, and a method for driving the same are proposed. The present invention relates to a storage device including a memory element and a circuit which changes a polarity of applying voltage to the memory element for writing (or reading) into a different polarity of that for reading (or writing). The memory element includes at least a first conductive layer, a film including silicon formed over the first conductive layer, and a second conductive layer formed over the silicon film. The first conductive layer and the second conductive layer of the memory element are formed using different materials. | 2010-12-16 |
20100315869 | Spin torque transfer MRAM design with low switching current - The invention discloses a method to store digital information through use of spin torque transfer in a device that has a very low critical current. This is achieved by adding a spin filtering layer whose direction of magnetization is fixed to be parallel to the device's pinned layer. | 2010-12-16 |
20100315870 | METHOD AND APPARATUS FOR INCREASING THE RELIABILITY OF AN ACCESS TRANSITOR COUPLED TO A MAGNETIC TUNNEL JUNCTION (MTJ) - A method of writing to a magnetic tunnel junction (MTJ) of a magnetic memory array includes an access transistor coupled to the MTJ for reading of and writing to the MTJ, where when the MTJ is written to, at times, by switching its magnetic orientation from an anti-parallel to a parallel magnetic orientation, a bit line that is coupled to one end of the MTJ is raised to Vcc and a voltage that is the sum of Vcc and Vx is applied to the gate of the access transistor, with Vx being approximately the voltage at an opposite end of the MTJ. Further, the voltage of a Source Line (SL), which is coupled to the MTJ using a first transistor of a write driver that is also coupled to the SL, is regulated such that SL remains sufficiently above 0 volts to avoid violation of Vgs exceeding Vcc where Vgs is the gate to source voltage of the access transistor. | 2010-12-16 |
20100315871 | DYNAMIC DATA RESTORE IN THYRISTOR-BASED MEMORY DEVICE - A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element. | 2010-12-16 |
20100315872 | Multilevel Cell Memory Devices Having Reference Point Cells - Embodiments of the disclosure include multilevel memory cell devices that utilize reference point cells to determine the states of other cells. Embodiments of the disclosure also include methods of storing data to and retrieving data from multilevel memory cell devices utilizing reference point cells. In one embodiment, a multilevel memory cell device includes user data cells, a reference point cell, and a controller. The user data cells each has one of a plurality of states. The reference point cell has a first state. The controller determines the states of the user data cells based at least in part on the first state of the reference point cell. | 2010-12-16 |
20100315873 | NONVOLATILE MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A method of programming a nonvolatile memory device comprises receiving program data, detecting logic states of the received program data, identifying adjusted margins to be applied to programmed memory cells based on the absence of one or more logic states in the detected logic states, and programming the program data in selected memory cells using the adjusted margins. | 2010-12-16 |
20100315874 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 2010-12-16 |
20100315875 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings. | 2010-12-16 |
20100315876 | MEMORY DEVICES AND OPERATIONS THEREOF USING PROGRAM STATE DETERMINATION BASED ON DATA VALUE DISTRIBUTION - In a memory device, a proportion of at least one cell state in a unit of the memory is determined. A program state of the unit of the memory is determined based on the determined proportion of the at least one cell state. Determining a proportion of at least one cell state in a unit of the memory may be preceded by processing data to be stored in the unit of the memory according to a data value distribution function to produce transformed data having data values conforming to a predetermined distribution and storing the transformed data in the unit of the memory. The distribution function may be configured, for example, to provide a uniform distribution of data values in the unit of the memory. | 2010-12-16 |
20100315877 | DATA SENSING MODULE AND SENSING CIRCUIT FOR FLASH MEMORY - A sensing circuit for a flash memory is provided. The sensing circuit includes a first transistor, a detector, and a charge circuit. A drain of the first transistor is coupled to a bias, a gate thereof receives an inverted signal, and a source thereof receives a data. In addition, the drain of the first transistor is further coupled to the detector. Therefore, the detector detects a voltage of the drain of the first transistor. When the voltage of the drain is lower than a threshold voltage, the detector enables a control signal. The charge circuit charges the source of the first transistor when the control signal is enabled, until the voltage of the drain of the first transistor reaches the threshold voltage. | 2010-12-16 |
20100315878 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY CELL WITH CHARGE ACCUMULATION LAYER - According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a first MOS transistor, and a current source circuit. The bit line transfers data read from the memory cell and/or data to be written to the memory cell. The sense amplifier charges the bit line during a data read and a data write. The first MOS transistor connects the bit line and the sense amplifier together. The current source circuit supplies a constant current to a gate of the first MOS transistor to charge the gate during a data write and/or a data read. | 2010-12-16 |
20100315879 | PAGE BUFFER OF NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING PROGRAM VERIFICATION OPERATION USING THE SAME - A page buffer of a nonvolatile memory device comprises a sense unit coupled between the sense node and the bit lines of a memory cell array, comprising a number of memory cells, and configured to precharge the bit lines to different voltage levels in response to a page buffer sense signal of a first or second voltage level, a MUX unit configured to output the page buffer sense signal of the first or second voltage level in response to a control signal according to a value of program data, a flag latch configured to temporarily store the program data and to output the control signal to the MUX unit, and a main latch configured to sense the voltage levels of the bit lines via the sense node and to perform a program verification operation. | 2010-12-16 |
20100315880 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A nonvolatile memory device is operated by, inter alia, performing a program operation on memory cells belonging to a page selected from among a plurality of pages, performing a verification operation on the programmed memory cells, loading a start loop value of a fail bit count set to the selected page, from among start loop values of fail bit counts set to the respective pages, and if a loop value of the program operation is greater than or equal to the start loop value, counting a number of fail bits included in data of the programmed memory cells detected in the verification operation. | 2010-12-16 |
20100315881 | NON-VOLATILE MEMORY DEVICE AND METHOD OF READING DATA IN A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a row decoder and a memory cell array. The row decoder generates a read voltage, and first, second and third drive voltages. The memory cell array includes a selected word line receiving the read voltage, a first neighboring word line of the selected word line receiving the second word line drive voltage, a second neighboring word line of the selected word line receiving the third word line drive voltage, and a non-neighboring word line of the selected word line receiving the first word line drive voltage. | 2010-12-16 |
20100315882 | NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A nonvolatile memory device includes a memory cell array including a number of memory cells coupled to a selected bit line, a bit line selection unit configured to select and precharge the selected bit line, and a potential control unit configured to control a voltage level of the precharged bit line in response to a voltage level corresponding to a value of program data. | 2010-12-16 |
20100315883 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device comprises a memory cell array including a number of bit lines commonly coupled to a source line and each coupled to a number of memory cells, a delay unit configured to delay a sense signal in response to a voltage level of the source line and to output a delayed sense signal, and a page buffer unit configured to sense voltage levels of the bit lines in response to the delayed sense signal. | 2010-12-16 |
20100315884 | Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof - A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices. | 2010-12-16 |
20100315885 | CIRCUITS, DEVICES, SYSTEMS, AND METHODS OF OPERATION FOR CAPTURING DATA SIGNALS - Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled to the data bus. The data capture circuit receives a data signal relative to a write strobe signal and captures a first data digit of the data signal responsive to a first edge of the write strobe signal and at least a second data digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each of the data digits of the data signal in substantially the same manner as the data capture circuit, and also generates a latch control signal indicative of when each data bits is latched. The latch control signal is provided to a write control circuit coupled to the feedback capture circuit and the data capture circuit. The write control circuit determines which of the data digits was latched first relative to an external timing, and generate a select control signal to drive the captured data digits onto the data bus in the order in which the data digits were received. | 2010-12-16 |
20100315886 | DATA TRANSFER APPARATUS, AND METHOD, AND SEMICONDUCTOR CIRCUIT - Provided is a data transfer apparatus and method that enables fast data transfer, and has a simple circuit configuration and a small area; and a semiconductor circuit. The data transfer apparatus includes: a data pair generation circuit ( | 2010-12-16 |
20100315887 | SEMICONDUCTOR MEMORY DEVICE HAVING PHYSICALLY SHARED DATA PATH AND TEST DEVICE FOR THE SAME - A semiconductor memory device includes a plurality of chips, a data path that is physically shared by the plurality of chips, a data input/output pad, and a data output driver. The data output driver is configured to receive merged data that includes data merged from a set of chip data read from the plurality of chips, compare the merged data to first reference data in a test mode, compare the merged data to second reference data in a test mode, and based on the comparisons, apply an output voltage at a data input/output pad. | 2010-12-16 |
20100315888 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling the substrate bias voltage of the transistor, high-speed equalization is performed, and an increase in leak current at times of standby and activation is prevented. | 2010-12-16 |
20100315889 | SRAM MEMORY CELL WITH DOUBLE GATE TRANSISTORS PROVIDED WITH MEANS TO IMPROVE THE WRITE MARGIN - A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary. | 2010-12-16 |
20100315890 | MEMORY ARRAY WITH CORRESPONDING ROW AND COLUMN CONTROL SIGNALS - Some embodiments regard a method comprising: controlling a row of cells of a memory array with a first signal; controlling a column of cells of the memory array with a second signal; transferring data from a cell activated by both the first signal and the second signal to a pair of bit lines associated with the cell; and using the data from the pair of bit lines as read data and as data written back to the cell to ensure the cell stores valid data. | 2010-12-16 |
20100315891 | MEMORY CONTROLLER WITH SKEW CONTROL AND METHOD - A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories. | 2010-12-16 |
20100315892 | METHOD AND APPARATUS FOR TIMING ADJUSTMENT - A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section. | 2010-12-16 |
20100315893 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level. | 2010-12-16 |
20100315894 | Low Power Sensing In a Multi-Port Sram Using Pre-Discharged Bit Lines - A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first voltage potential different than the zero voltage potential during an access of the memory cell; and sensing the memory cell contents when the associated bit line has reached the first voltage potential. | 2010-12-16 |
20100315895 | SEMICONDUCTOR DEVICE - A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR | 2010-12-16 |
20100315896 | TEMPERATURE DETECTION CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A temperature detection circuit of a semiconductor memory apparatus includes a fixed period oscillator, a temperature variable signal generating unit and a counting unit. The oscillator is configured to generate a fixed period oscillator signal when an enable signal is enabled. The temperature variable signal generating unit is configured to generate a temperature variable signal whose enable interval varies based on temperature variations, when the enable signal is enabled. The counting unit is configured to count the oscillator signal during the enable interval of the temperature variable signal to generate a temperature information signal. | 2010-12-16 |
20100315897 | DISPOSABLE SHAKER - A disposable shaker ( | 2010-12-16 |
20100315898 | FEED MIXER - A feed mixer ( | 2010-12-16 |
20100315899 | SELF-STABILIZING DYNAMIC DIAPHRAGM FOR BROAD BANDWIDTH ACOUSTIC ENERGY SOURCE - An apparatus for estimating a property in a borehole penetrating the earth, the apparatus having: a carrier configured to be disposed in the borehole; and an acoustic transducer disposed at the carrier and configured to at least one of transmit and receive an acoustic wave used to estimate the property, the acoustic transducer comprising an acoustic diaphragm; wherein the acoustic diaphragm includes a surface in communication with a plurality of structural members configured to increase the rigidity of the surface, the surface being configured to interface with a medium that propagates the acoustic wave. | 2010-12-16 |
20100315900 | METHOD AND APPARATUS FOR HIGH RESOLUTION SOUND SPEED MEASUREMENTS - An apparatus for estimating an influx of a formation fluid into a borehole fluid, the apparatus having: a carrier; an acoustic transducer disposed at the carrier; a first reflector disposed a first distance from the acoustic transducer and defining a first round trip distance; a second reflector disposed a second distance from the acoustic transducer and defining a second round trip distance; and a processor in communication with the acoustic transducer and configured to measure a difference between a first travel time for the acoustic signal traveling the first round trip distance and a second travel time for the acoustic signal traveling the second round trip distance to estimate the influx of the formation fluid; wherein the acoustic transducer, the first reflector, and the second reflector are disposed in the borehole fluid that is in the borehole. | 2010-12-16 |
20100315901 | Sending a Seismic Trace to Surface After a Vertical Seismic Profiling While Drilling Measurement - A system, method and computer-readable medium for acquiring seismic data, which includes activating a seismic source at a surface location; defining a seismic trace of a seismic wave received at a downhole location on a bottomhole assembly in a borehole in response to the activation of the seismic source; compressing the seismic trace; and recording the compressed seismic trace to a storage medium. | 2010-12-16 |
20100315902 | METHOD FOR IMAGING THE EARTHS SUBSURFACE USING PASSIVE SEISMIC INTERFEROMETRY AND ADAPTIVE VELOCITY FILTERING - A method of imaging the Earth's subsurface using passive seismic interferometry tomography includes detecting seismic signals from within the Earth's subsurface over a time period using an array of seismic sensors, the seismic signals being generated by seismic events within the Earth's subsurface. The method further includes adaptively velocity filtering the detected signals. The method further includes cross-correlating the velocity filtered seismic signals to obtain a reflectivity series at a position of each of the seismic sensors. | 2010-12-16 |
20100315903 | METHOD FOR PASSIVE SEISMIC EMISSION TOMOGRAPHY USING ADAPTIVE VELOCITY FILTER - A method for seismic event mapping includes adaptively velocity filtering seismic signals recorded at selected positions. The velocity filtered signals are transformed into a domain of possible spatial positions of a source of seismic events. An origin in spatial position and time of at least one seismic event is determined from space and time distribution of at least one attribute of the transformed seismic data. | 2010-12-16 |
20100315904 | DIRECTION-FINDING METHOD AND INSTALLATION FOR DETECTION AND TRACKING OF SUCCESSIVE BEARING ANGLES - A direction-finding method and apparatus for detection and tracking of successive bearing angles of sound-emitting targets, wherein intensity plots of successive clock cycles in a waterfall plot show bearing traces of successive bearing angles, and preferred bearing traces are marked by a tracker. In order to automate the setting and deletion of trackers, starting from trace state vectors, which are determined at the time t=k−1, are each associated with one bearing trace and each have a bearing angle as well as its time derivative, which is referred to as the bearing rate, and possibly an intensity and its time derivative, which is referred to as the intensity rate, and trace errors associated with the trace state vectors for the time t=k, predicted state vectors are predicted together with predicted estimation errors. Bearing traces are displayed as a function of a trace quality | 2010-12-16 |
20100315905 | MULTIMODAL OBJECT LOCALIZATION - Various embodiments of the present invention are directed to systems and methods for multimodal object localization using one or more depth sensors and two or more microphones. In one aspect, a method comprises capturing three-dimensional images of a region of space wherein the object is located. The images comprise three-dimensional depth sensor observations. The method collects ambient audio generated by the object, providing acoustic observation regarding the ambient audio time difference of arrival at the audio sensors. The method determines a coordinate location of the object corresponding to the maximum of a joint probability distribution characterizing the probability of the acoustic observations emanating from each coordinate location in the region of space and the probability of each coordinate location in the region of space given depth sensor observations. | 2010-12-16 |
20100315906 | HAND-HELD ACOUSTIC CAMERA - An acoustic camera includes an acoustic transmitter disposed at one longitudinal end of a housing. The transmitter has a convex radiating surface. A diameter of the transmitter is about four times a wavelength of acoustic energy emitted by the transmitter. A plurality of acoustic receivers is disposed at spaced locations in a pattern extending laterally from the housing. A signal processor is in signal communication with the acoustic receivers. The signal processor is configured to cause the acoustic receivers to be sensitive along steered beams. The signal processor is configured to cause an end of the steered beams to move through a selected pattern within a beam width of the acoustic energy emitted by the acoustic transmitter. The signal processor is configured to operate a visual display device to generate a visual representation corresponding to acoustic energy detected by the acoustic receivers. A visual display device is in signal communication with the signal processor. | 2010-12-16 |
20100315907 | Electronic Device And Control Method Therefor - An electronic device that receives a radio signal according to specific conditions and displays specific information, including a reception unit that receives the radio signal; an electrophoretic display unit that displays the specific information; a display drive unit that supplies a drive signal corresponding to content of the specific information to be displayed to the electrophoretic display unit; and a control unit that instructs the reception unit to receive the radio signal and instructs the display drive unit to supply the drive signal to the electrophoretic display unit, instructs the display drive unit to supply a drive signal for displaying an indication that the reception unit is receiving the radio signal to the electrophoretic display unit before instructing the reception unit to receive the radio signal, and controls the display drive unit to stop supplying the drive signal while the reception unit is receiving the radio signal. | 2010-12-16 |
20100315908 | DIFFERENTIAL GEAR FOR WATCH MOVEMENT - A differential gear for watch movement may include a central shaft whereon first and second wheels are rotatably mounted, each of which is provided with a toothing arranged to mesh with a toothing of at least one satellite borne by a satellite carrier also mounted on the central shaft. The first and second wheels may be configured to engage first and second mobiles of the watch movement, the central shaft including a toothing configured to engage a third mobile of the watch movement. Further, the satellite carrier may be secured in rotation with the central shaft by a friction device comprising a tube having a first portion arranged bearing against the central shaft and at least one second portion arranged bearing against the satellite carrier. The tube may include a substantially cylindrical skirt, wherein at least one first tab is formed in such a way that it exerts a force having a radial component on the satellite carrier. | 2010-12-16 |
20100315909 | PROCESS AND DEVICE FOR FASTENING A GLASS TO A BEZEL - Method of fastening a glass ( | 2010-12-16 |
20100315910 | ENCODER CAPABLE OF COMPENSATING FOR TILT, HARD DISK DRIVE USING THE SAME, AND SERVO TRACK WRITING SYSTEM FOR THE HARD DISK DRIVE - An encoder is capable of being used to compensate for the tilting of a movable object in an apparatus. The encoder includes a fixed scale, and a movable scale integrated with an object that moves during an operation of the apparatus and having a plurality of patterns that are out of phase from each other with respect to the direction of movement of the object. The encoder may be employed by a hard disk drive (HDD) and a servo track recording apparatus. The movable scale is integrated with an actuator arm of the HDD for positioning a read/write head of the HDD, and the fixed scale is fixed to the housing of the HDD. The servo track recording apparatus can use the encoder to record servo track information precisely on a disk. | 2010-12-16 |
20100315911 | Optical Disk Apparatus - An optical disk apparatus to record data on an optical disk on which a wobble is formed, the optical disk apparatus including; a detection unit including a BPF which a signal obtained from a reflected light from an optical disk passes, the detection unit to detect a wobble signal from a wobble based on the signal passing the BPF; and a register to store an adjustment value for adjusting the BPF as a register value, so as to adjust the BPF based on each of register values obtained by changing the register value 1 LSB by 1 LSB; acquire an amplitude of the signal passing the BPF, the amplitude corresponding to each of the register values; identify one of the register values for the largest acquired amplitude; and adjust the BPF based on a value obtained by adding 1 LSB to the identified register value when data is recorded. | 2010-12-16 |
20100315912 | OPTICAL DISC DEVICE - An optical disc device includes: a first searching part which searches a condition where amplitude level of a TE signal is made maximum by changing either one of position of a movable lens and a focus balance value in a state where a focus servo control is performed based on a FE signal; an adjusting line setting part which sets an adjusting line that has an inclination α which is preliminarily stored in a memory portion and that passes the position of the movable lens and the focus balance value both of which are searched by the first searching part; and a second searching part which changes the position of the movable lens and the focus balance value to plural values on the adjusting line in a state where the focus servo control is performed consecutively to search a condition where the amplitude level of the tracking error signal is made maximum. | 2010-12-16 |
20100315913 | Method for Controlling Layer Changes for an Optical Disk Drive - A method for controlling layer changes for an optical disk drive is provided, where a focus of a laserbeam emitted by a pickup head of the optical disk drive is moved from a current data layer of a disk to a target data layer of the disk. First, a position of a collimator lens of the pickup head is adjusted for spherical aberration correction. The objective lens is then lowered to a low position to move the focus of the laserbeam off the surface of the disk. The objective lens is then raised towards the disk. A focusing error signal is generated while the objective lens is being raised. Whether a target S-curve corresponding to the target data layer is present in the focusing error signal is then started to be detected. If the target S-curve is detected, the focus on operation on the target data layer of the disk is successful. | 2010-12-16 |
20100315914 | LIGHT IRRADIATION POWER ADJUSTING METHOD AND OPTICAL INFORMATION RECORDING/REPRODUCING APPARATUS - A light irradiation power adjusting method includes a first recording step, a first reproducing step, a first measuring step, a bias power determining step and a recording power determining step. In the first recording step, an adjustment pattern is recorded to an optical information recording medium while fixing a recording power to a predetermined first power value and while changing a bias power among a plurality of second power values within a predetermined range. In the first reproducing step, the recorded adjustment pattern is reproduced so as to generate a reproduction signal. In the first measuring step, asymmetry values corresponding to the plurality of second power values are measured. In the bias power determining step, an optimum bias power value is determined based on the asymmetry values. In the recording power determining step, an optimum recording power value is determined based on the optimum bias power value. | 2010-12-16 |
20100315915 | Input Signal Processing System - An input signal processing system is described. It comprises a first transconductance device having a first input, second input, and an output, wherein the first input is coupled to receive the input signal; a first resistor coupled to a first input of the first transconductance device, wherein the first resistor converts the input current signal to an input voltage signal; a first voltage-current converter coupled to the output, the second input, the resistor, and a low voltage supply, wherein the first voltage-current converter is operative for converting the input voltage signal to a input current signal; and a low pass filter having an input coupled to the voltage converter for filtering noise from the input current signal. | 2010-12-16 |
20100315916 | INFORMATION RECORDING MEDIUM, INFORMATION RECORDING METHOD, INFORMATION RECORDING APPARATUS, INFORMATION REPRODUCING METHOD AND INFORMATION REPRODUCING APPARATUS - If a defective cluster in a spare area is managed with a defect entry, the size of a DFL will increase as the size of the spare area increases with an increase in the number of recording layers stacked in a disc. An information recording medium according to the present invention has pointer information indicating the location of the next available cluster in each spare area, and restricts the direction in which the spare area is used. Also, a defect entry indicating a defective cluster in the spare area is registered with the DFL. Thus, even if the size of the spare area | 2010-12-16 |
20100315917 | INPUT CURRENT CHANNEL DEVICE - An input current channel device is described. This device comprises a first terminal for receiving a reference signal; a second terminal for receiving a first target signal; a pass through device coupled to the first terminal, the pass through device operative for transmitting a delayed reference signal in response to receiving the reference signal; a first combination logic device coupled to the first terminal and the second terminal, the first combination logic device operative for transmitting a first combination logic signal in response to receiving the reference signal and the first target signal; a selection device coupled for receiving the delayed reference signal, the first combination logic signal, and a first synchronization signal, the selection device operative for selectively transmitting a second synchronization signal, and wherein selectively transmitting the second synchronization signal reduces skew between the reference channel and the first target channel. | 2010-12-16 |
20100315918 | LASER DIODE DRIVER WITH WAVE-SHAPE CONTROL - An optical disk drive system associated with a laser diode is described. The optical disk drive system comprises a current generator for receiving input signals; a current switch coupled to receive timing signals; a current driver coupled to receive output signals from the current switch and the current generator, the current driver further comprising a driver with wave shape control selected from the group consisting of a laser diode read driver and a laser diode write driver, wherein the driver with shape control is operative for transmitting at least one output signal that is a scaled version of at least one of the output signals received from the current generator, wherein the current driver is operative for transmitting at least one output signal driving the laser diode. | 2010-12-16 |
20100315919 | CURRENT GAIN CONTROL SYSTEM - A current gain control system is described and comprises first and second gain blocks respectively associated with the first and second input channels, wherein first and second gain blocks transmit first and second gain signals in response to receiving first and second input signals; first and second converters adapted to be respectively coupled to the first and second gain blocks, the first and second converters operative for setting gains associated with the first and second input channel and for transmitting first and second converted signals in response to receiving the first and second gain signals; and first and second switches for selectively coupling the first and second converters to first and second channel drivers, respectively, wherein the first and second channel drivers transmit channel gain signals in response to receiving the first converted signal, and the channel gain signal allows control of the gain associated with the input channel. | 2010-12-16 |
20100315920 | EXTERNAL OPTICAL DISC DRIVE AND METHOD OF CONTROLLING THE SAME - An external optical disc drive, connected to a bus from which a supplying voltage and a supplying current are outputted, includes: a voltage detector connected to the bus for receiving and detecting the supplying voltage; a digital signal processor connected to the voltage detector; a motor driver connected to the digital signal processor; and a spindle motor connected to the motor driver; wherein a speed-control signal, for informing the digital signal processor to lower the speed of the spindle motor via the motor driver, is outputted to the digital signal processor from the voltage detector while the supplying voltage is detected lower than a threshold voltage. | 2010-12-16 |
20100315921 | OPTICAL RECORDING METHOD AND OPTICAL RECORDING DEVICE - In a recording method for recording information on an optical recording medium ( | 2010-12-16 |
20100315922 | ROTATION-ACTIVATED ELECTRONIC COMPONENT - A rotation-activated electronic component, preferably a RFID tag mounted on or incorporated in a support that is rotated when read, e.g. a CD or DVD. The RFID tag comprises an antenna, a rotational switch and a component, advantageously a processor. The antenna is adapted to transform received RFID signals to electric energy that powers the component. In a preferred embodiment, the rotational switch is adapted to cut the circuit unless the support does not rotate at or above a certain rotational speed. Supports equipped with the RFID tag of the invention will thus respond only if they rotate sufficiently. This can avoid collisions in case more than one such RFID tag is within communication range of an antenna of a reader. In a preferred embodiment, the information returned by the component is needed for full use of the content on the support. | 2010-12-16 |