50th week of 2011 patent applcation highlights part 13 |
Patent application number | Title | Published |
20110303886 | DRIVE ASSEMBLY AND APPARATUS FOR HOIST - An assembly is provided that can include a motor; a planetary transmission coupled to the motor; and a spool coupled to the transmission, and the motor is disposed or disposable partially within the spool. | 2011-12-15 |
20110303887 | MEMORY STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells. | 2011-12-15 |
20110303888 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The memory cell includes a plurality of layers. The plurality of layers includes a carbon-containing memory layer sandwiched between a first electrode film and a second electrode film and a carbon-containing barrier layer provided at least one of between the first electrode film and the memory layer and between the second electrode film and the memory layer. The barrier layer has lower electrical resistivity than the memory layer. | 2011-12-15 |
20110303889 | VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME - A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit. | 2011-12-15 |
20110303890 | Electrically Actuated Device - An electrically actuated device includes a first electrode and a second electrode crossing the first electrode at a non-zero angle, thereby forming a junction therebetween. A material is established on the first electrode and at the junction. At least a portion of the material is a matrix region. A current conduction channel extends substantially vertically between the first and second electrodes, and is defined in at least a portion of the material positioned at the junction. The current conduction channel has a controlled profile of dopants therein. | 2011-12-15 |
20110303891 | Mixed Alloy Defect Redirection Region and Devices Including Same - An optical semiconductor device such as a light emitting diode is formed on a transparent substrate having formed thereon a template layer, such as AlN, which is transparent to the wavelength of emission of the optical device. A mixed alloy defect redirection region is provided over the template layer such that the composition of the defect redirection region approaches or matches the composition of the regions contiguous thereto. For example, the Al content of the defect redirection region may be tailored to provide a stepped or gradual Aluminum content from template to active layer. Strain-induced cracking and defect density are reduced or eliminated. | 2011-12-15 |
20110303892 | LIGHT-EMITTING DEVICE AND PROJECTOR - A light-emitting device includes a first layer, a second layer, and a semiconductor body interposed between the first and second layers, wherein the semiconductor body has a first fine-wall-shape member, a second fine-wall-shape member, and a semiconductor member interposed between the first and second fine-wall-shape members, the first and second fine-wall-shape members have a third layer, a fourth layer, and a fifth layer interposed between the third and fourth layers, the fifth layer is a layer that generates light and guides the light, the third and fourth layers are layers that guide the light generated in the fifth layer, and the first and second layers are layers that suppress leakage of the light generated in the fifth layer. | 2011-12-15 |
20110303893 | Electrically Pixelated Luminescent Device Incorporating Optical Elements - Electrically pixelated luminescent devices incorporating optical elements, methods for forming electrically pixelated luminescent devices incorporating optical elements, and systems including electrically pixelated luminescent devices incorporating optical elements. | 2011-12-15 |
20110303894 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND FABRICATING METHOD - A method of forming a semiconductor light emitting element. The method can include forming a seed layer on a semiconductor layer assembly including at least one nitride semiconductor layer. An insulating mask can be formed on the seed layer. The insulating mask can include a plurality of element areas separated by cross spaces. Each element area of the plurality of element areas can be connected to at least one of the other element areas of the plurality of element areas. The seed layer can be plated such that a plating substrate is formed in each of the plurality of element areas. | 2011-12-15 |
20110303895 | VERTICAL LIGHT-EMITTING DIODE - A vertical light-emitting diode with a short circuit protection function includes a heat dissipation substrate, a second electrode, a welding metal layer and a third electrode; a semiconductor light-emitting layer formed on the third electrode; a barrier for the semiconductor light-emitting layer with an isolation trench, so that the barrier for the semiconductor light-emitting layer surrounds the semiconductor light-emitting layer on a central region of the third electrode, with the isolation trench therebetween. The barrier for the semiconductor light-emitting layer has a structure the same as the semiconductor light-emitting layer, and the isolation trench exposes the third electrode. A fourth electrode is formed on the semiconductor light-emitting layer. The barrier prevents the metal particles in chip dicing and the conductive adhesive in packaging from reaching the semiconductor light-emitting layer, thereby providing short circuit protection and improving the reliability of the vertical light-emitting diode. | 2011-12-15 |
20110303896 | BROADBAND LIGHT EMITTING DEVICE LAMPS FOR PROVIDING WHITE LIGHT OUTPUT - A light emitting device (LED) includes a broadband LED chip having a multi-quantum well active region including alternating active and barrier layers. The active layers respectively include different thicknesses and/or different relative concentrations of at least two elements of a semiconductor compound, and are respectively configured to emit light of different emission wavelengths that define an asymmetric spectral distribution over a wavelength range within a visible spectrum. Related devices are also discussed. | 2011-12-15 |
20110303897 | MATERIALS, SYSTEMS AND METHODS FOR OPTOELECTRONIC DEVICES - A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer. | 2011-12-15 |
20110303898 | MATERIALS, SYSTEMS AND METHODS FOR OPTOELECTRONIC DEVICES - A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer. | 2011-12-15 |
20110303899 | GRAPHENE DEPOSITION - Embodiments of the invention are directed toward the deposition of Graphene on a semiconductor substrate. In some embodiments, these processes can occur at low temperature levels during a back end of the line process. For example, Graphene can be deposited in a CVD reactor at a processing temperature that is below 600° C. to protect previously deposited layers that may be susceptible to sustained higher temperatures. Graphene deposition can include the deposition of an underlayer (e.g., cobalt) followed by the flow of a carbon precursor (e.g., acetylene) at the processing temperature. Graphene can then be synthesized with during cooling, an RTP cure, and/or a UV cure. | 2011-12-15 |
20110303900 | LIGHTING EMITTING DIODE DEVICE WITH DIRECTIVITY AND COHERENCY AND MANUFATURING METHOD FOR PROVIDING LIGHT WITH DIRECTIVITY AND COHERENCY - The present invention discloses a lighting emitting diode device with directivity and coherency and a manufacturing method for providing a light with directivity and coherency. The light emitting diode device comprises a substrate, a light emitting diode module and a masking layer. The light emitting diode module is disposed on the substrate, and is provided for emitting a light, and the masking layer is disposed on the light emitting diode module. The masking layer has an opening, and an aperture of the opening is matching with the wavelength of the light. The light with directivity and coherency is generated by the diffraction effect when the light passes through the opening. | 2011-12-15 |
20110303901 | 6H-INDOLO[2,3-b]QUINOXALINE DERIVATIVES AND ORGANIC LIGHT EMITTING DIODE USING THE SAME - A 6H-indolo[2,3-b]quinoxaline derivative has a structure of formula (I). R | 2011-12-15 |
20110303902 | ORGANIC LIGHT-EMITTING DIODE WITH HIGH COLOR RENDERING - An organic light-emitting diode with high color rendering is provided, which includes: a substrate; a first electrode disposed over the substrate; a light-emitting region disposed over the first electrode, in which the light-emitting region includes a plurality of light-emitting layers and at least one spacer, the spacer being disposed between any two of the light-emitting layers and each of the light-emitting layers individually including a dye; and a second electrode disposed over the light-emitting region. Accordingly, the organic light-emitting diode according to the present invention can exhibit high color rendering and high illumination efficiency. | 2011-12-15 |
20110303903 | ORGANIC ELECTROLUMINESCENCE ELEMENT AND DISPLAY DEVICE - A red light emitting organic electroluminescence device ( | 2011-12-15 |
20110303904 | PHOTOVOLTAIC DEVICE AND METHOD OF MAKING SAME - A photovoltaic device and method of manufacturing is disclosed. In one embodiment, the device includes a silicon layer and first and second organic layers. The silicon layer has a first face and a second face. First and second electrodes electrically are coupled to the first and second organic layers. A first heterojunction is formed at a junction between the one of the faces of the silicon layer and the first organic layer. A second heterojunction is formed at a junction between one of the faces of the silicon layer and the second organic layer. The silicon layer may be formed without a p-n junction. At least one organic layer may be configured as an electron-blocking layer or a hole-blocking layer. At least one organic layer may be comprised of phenanthrenequinone (PQ). A passivating layer may be disposed between at least one of the organic layers and the silicon layer. The passivating layer may be organic. At least one of the organic layers may passivate a surface of the silicon layer. The device may also include at least one transparent electrode layer coupled to at least one of the electrodes. | 2011-12-15 |
20110303905 | Organic Light-Emitting Diode Having Optical Resonator in Addition to Production Method - The invention relates to an organic light-emitting diode, known under the abbreviation OLED, and to a method for the production of such an organic light-emitting diode. According to the invention, an OLED or organic light-emitting diode having an emitter layer ( | 2011-12-15 |
20110303906 | TRANSPARENT ORGANIC LIGHT EMITTING DIODE - The invention relates to a transparent organic light emitting diode (OLED) ( | 2011-12-15 |
20110303907 | ORGANIC ELECTROLUMINESCENT ELEMENT MATERIAL AND ORGANIC ELECTROLUMINESCENT ELEMENT COMPRISING SAME - A material for organic electroluminescent devices including a 2,7-disubstituted naphthalene ring in its molecule and an organic electroluminescent device including an organic thin film layer having one or more layers between a cathode and an anode. An organic electroluminescence device having the organic thin film layer which includes the material for organic electroluminescent devices and at least one kind of phosphorescent emitting materials has long lifetime and high current efficiency. | 2011-12-15 |
20110303908 | POLYMER, ORGANIC PHOTOELECTRIC DEVICE, AND DISPLAY INCLUDING THE SAME - A polymer, an organic photoelectric device, and a display device, the polymer including a repeating unit represented by the following Chemical Formula 1: | 2011-12-15 |
20110303909 | PLANAR CONJUGATED COMPOUNDS AND THEIR APPLICATIONS FOR ORGANIC ELECTRONICS - The invention relates to organic semiconducting materials, methods for their preparation and organic electronic devices incorporating the said organic semiconducting materials. The organic semiconductors contain a compound of formula (I) | 2011-12-15 |
20110303910 | Field Effect Transistor - A heterocyclic compound represented by formula (1) and a field effect transistor having a semiconductor layer comprising the compound. (In the formula, X | 2011-12-15 |
20110303911 | METHOD FOR FORMING PATTERN, METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE - Oxidation treatment is performed to the surface of a substrate provided with a photocatalytic conductive film and an insulating film; treatment with a silane coupling agent is performed, so that a silane coupling agent film is formed and the surface of the substrate is modified to be liquid-repellent; and the surface of the substrate is irradiated with light of a wavelength (less than to equal to 390 nm) which has energy of greater than or equal to a band gap of a material for forming the photocatalytic conductive film, so that only the silane coupling agent film over the surface of the photocatalytic conductive film is decomposed and the surface of the photocatalytic conductive film can be modified to be lyophilic. | 2011-12-15 |
20110303912 | Methods Of Manufacturing P-Type Zn Oxide Nanowires And Electronic Devices Including P-Type Zn Oxide Nanowires - Example embodiments relate to methods of manufacturing p-type Zn oxide nanowires and electronic devices including the p-type Zn oxide nanowires. The method may include forming Zn oxide nanowires in an aqueous solution by using a hydrothermal synthesis method and annealing the Zn oxide nanowires to form p-type Zn oxide nanowires. | 2011-12-15 |
20110303913 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object of an embodiment of the present invention is to manufacture a highly-reliable semiconductor device comprising a transistor including an oxide semiconductor, in which change of electrical characteristics is small. In the transistor including an oxide semiconductor, oxygen-excess silicon oxide (SiO | 2011-12-15 |
20110303914 | Semiconductor Device - One object is to provide a semiconductor device including an oxide semiconductor with improved electrical characteristics. The semiconductor device includes a first insulating film including an element of Group 13 and oxygen; an oxide semiconductor film partly in contact with the first insulating film; a source electrode and a drain electrode electrically connected to the oxide semiconductor film; a gate electrode overlapping with the oxide semiconductor film; and a second insulating film partly in contact with the oxide semiconductor film, between the oxide semiconductor film and the gate electrode. Further, the first insulating film including an element of Group 13 and oxygen includes a region where an amount of oxygen is greater than that in a stoichiometric composition ratio. | 2011-12-15 |
20110303915 | Compressively Stressed FET Device Structures - Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins. | 2011-12-15 |
20110303916 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: a lower electrode ( | 2011-12-15 |
20110303917 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF FABRICATING THE SAME AND FLAT DISPLAY HAVING THE SAME - A thin film transistor substrate and a method for fabricating the same are disclosed. A thin film transistor substrate includes a substrate comprising a plurality of grooves having different depths, respectively, to have a multi-step structure; gate and data lines alternatively crossed in the grooves to form a plurality of pixel areas; thin film transistors formed in the grooves of the substrate to be formed in cross portion of the gate and data lines, wherein active layers of the thin transistors are formed along the gate lines and gate electrodes, the active layers separated from active layers of neighboring pixel areas with the data line located there between. | 2011-12-15 |
20110303918 | ORGANIC LIGHT-EMITTING DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display and a method of manufacturing the display are disclosed. In one embodiment, the organic light-emitting display includes a thin film transistor comprising: i) a gate electrode, ii) an active layer electrically insulated from the gate electrode, iii) a source electrode and a drain electrode electrically insulated from the gate electrode, and contacting the active layer and iv) an insulating layer formed between i) the source and drain electrodes and ii) the active layer. The display further includes an organic light-emitting device electrically connected to the thin film transistor. In one embodiment, the source electrode comprises a first source electrode and a second source electrode that are separated from each other, and a third source electrode electrically connecting the first and second source electrodes. Moreover, the drain electrode comprises a first drain electrode and a second drain electrode that are separated from each other, and a third drain electrode electrically connecting the first and second drain electrodes. | 2011-12-15 |
20110303919 | DISPLAY DEVICE AND ELECTRONIC DEVICE HAVING THE DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THEREOF - To provide a display device including a thin film transistor in which high electric characteristics and reduction in off-current can be achieved. The display device having a thin film transistor includes a substrate, a gate electrode provided over the substrate, a gate insulating film provided over the gate electrode, a microcrystalline semiconductor film provided over the gate electrode with the gate insulating film interposed therebetween, a channel protection layer which is provided over and in contact with the microcrystalline semiconductor film, an amorphous semiconductor film provided over the gate insulating film and on a side surface of the microcrystalline semiconductor film and the channel protection layer, an impurity semiconductor layer provided over the amorphous semiconductor film, and a source electrode and a drain electrode provided over and in contact with the impurity semiconductor layer. The thickness of the amorphous semiconductor film is larger than that of the microcrystalline semiconductor film. | 2011-12-15 |
20110303920 | THIN FILM TRANSISTOR HAVING A COPPER SIGNAL LINE AND METHOD OF MANUFACTURING THE SAME - An array substrate for a liquid crystal display device includes a substrate, a thin film transistor having a signal line of dual layered structure of a copper compound and copper, and a pixel electrode connected to the thin film transistor. | 2011-12-15 |
20110303921 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a substrate, a first conductive film pattern including a gate electrode and a first capacitor electrode on the substrate, a gate insulating layer pattern on the first conductive film pattern, a polycrystalline silicon film pattern including an active layer and a second capacitor electrode on the gate insulating layer pattern, an interlayer insulating layer on the polycrystalline silicon film pattern, a plurality of first contact holes through the gate insulating layer pattern and the interlayer insulating layer to expose a portion of the first conductive film pattern, a plurality of second contact holes through the interlayer insulating layer to expose a portion of the polycrystalline silicon film pattern, and a second conductive film pattern including a source electrode, a drain electrode, and a pixel electrode on the interlayer insulating layer. | 2011-12-15 |
20110303922 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device and a manufacturing method thereof are provided. The display device includes a substrate, a semiconductor layer formed on the substrate, an organic insulating layer formed on the semiconductor layer, a plurality of conductive wires formed on the organic insulating layer. The organic insulating layer has an open groove that is formed between the conductive wires. | 2011-12-15 |
20110303923 | TFT, ARRAY SUBSTRATE FOR DISPLAY APPARATUS INCLUDING TFT, AND METHODS OF MANUFACTURING TFT AND ARRAY SUBSTRATE - A thin film transistor (TFT), an array substrate including the TFT, and methods of manufacturing the TFT and the array substrate. The TFT includes an active layer, and a metal member that corresponds to a portion of each of the source region and the drain region of the active layer, and is arranged on the active layer, a portion of the metal member contacts the source and drain regions of the active layer and the source and drain electrodes, and portions of the active layer that corresponds to portions below the metal member of the active layer are not doped. | 2011-12-15 |
20110303924 | LIGHT-EMITTING DEVICE AND PROJECTOR - A light-emitting device includes a first layer, a second layer, and a semiconductor body interposed between the first and second layers, wherein the semiconductor body has a first fine-wall-shape member, a second fine-wall-shape member, and a semiconductor member interposed between the first and second fine-wall-shape members, the first and second fine-wall-shape members have a third layer, a fourth layer, and a fifth layer interposed between the third and fourth layers, the fifth layer is a layer that generates light and guides the light, the third and fourth layers are layers that guide the light generated in the fifth layer, and the first and second layers are layers that suppress leakage of the light generated in the fifth layer. | 2011-12-15 |
20110303925 | Semiconductor device and the method of manufacturing the same - A semiconductor device according to the invention includes p-type well region 3 and n | 2011-12-15 |
20110303926 | LIGHT EMITTING DIODE SYSTEMS INCLUDING OPTICAL DISPLAY SYSTEMS HAVING A MICRODISPLAY - Light emitting diode systems are disclosed. | 2011-12-15 |
20110303927 | LIGHT EMITTING MODULE AND ILLUMINATION APPARATUS - A light emitting module ( | 2011-12-15 |
20110303928 | LED LAMP - An LED lamp A includes a plurality of LED modules | 2011-12-15 |
20110303929 | MULTI-DIMENSIONAL LED ARRAY SYSTEM AND ASSOCIATED METHODS AND STRUCTURES - A formed, multi-dimensional light-emitting diode (LED) array is disclosed. A substrate is bent into a trapezoidal shape having different sections facing in different directions. Each section has one or more mounted LEDs that emit light with an azimuthally non-circular, monotonic angular distribution. A converter material is placed in an optical path of the LEDs to alter characteristics of the light from the LEDs. | 2011-12-15 |
20110303930 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is disclosed. The organic light emitting diode (OLED) display includes an organic light emitter that has a first electrode, an organic emission layer, and a second electrode. The OLED also has an encapsulation substrate covering the organic light emitter and an assistance electrode disposed between the encapsulation substrate and the second electrode. The assistance electrode can be disposed in a non-light-emitting region between the organic light emitter and the second electrode, and can have a lower resistance than a resistance of the second electrode. | 2011-12-15 |
20110303931 | SEMICONDUCTOR LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - Disclosed are a semiconductor light emitting diode and a method for fabricating the same. The method comprises forming a crystalline nitride semiconductor layer on a substrate, forming an amorphous layer and a crystalline nitride semiconductor layer on the nitride semiconductor layer, forming an n-type nitride semiconductor layer on the crystalline nitride semiconductor layer, forming an active layer on the n-type nitride semiconductor layer, and forming a p-type nitride semiconductor layer on the active layer. | 2011-12-15 |
20110303932 | Organic, Radiation-Emitting Component and Method for Producing the Same - A method for producing an organic, radiation-emitting component is specified, wherein at least one layer ( | 2011-12-15 |
20110303933 | DIODE HAVING VERTICAL STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A light emitting diode includes a conductive layer, an n-GaN layer on the conductive layer, an active layer on the n-GaN layer, a p-GaN layer on the active layer, and a p-electrode on the p-GaN layer. The conductive layer is an n-electrode. | 2011-12-15 |
20110303934 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device comprises a reflective layer comprising an alloy of at least one of an Ag-based alloy, an Al-based alloy, Ag, Al, Rh, or Sn, and at least one of Pd, Cu, C, Sn, In or Cr, and a light emitting semiconductor layer comprising a second conductive semiconductor layer, an active layer and a first conductive semiconductor layer on the reflective layer. | 2011-12-15 |
20110303935 | LIGHT SOURCE MODULE WITH LUMINESCENCE IN LENS - The disclosure relates to a light source module comprising a substrate having circuits, at least one light emitting diode (LED) die positioned on the substrate, and at least one luminescence containing lens over the LED die with a light-converting portion having an inverted truncated pyramid-shaped structure with a spherical top. The light-converting portion scatters light generated by the LED die and converts the light into a different color. The light-converting portion has a small bottom end conformably located on the LED die and a large top end which is a portion of an outer contour of the lens. | 2011-12-15 |
20110303936 | LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A light emitting device package structure is described. The light emitting device package structure includes a carrier substrate with a top surface and a bottom surface, having at least two through holes. A dielectric mirror structure is formed on the top surface of the carrier substrate, wherein the dielectric mirror structure includes laminating at least five dielectric layer groups, wherein each of the dielectric layer group includes an upper first dielectric layer having a first reflective index and an lower second dielectric layer having a second reflective index smaller than the first reflective index. A first conductive trace and a second conductive trace isolated from each other are formed on the dielectric mirror structure, respectively extending from the top surface to the bottom surface of the carrier substrate along sides of the different through holes. A light emitting device chip is mounted on the top surface of the carrier substrate. | 2011-12-15 |
20110303937 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a heat conductive substrate and a light emitting structure formed on the substrate. A transparent conductive layer is formed on the light emitting structure and an electrode pad is deposited on the transparent conductive layer. The light emitting diode further comprises a metal layer and a buffer layer set between the light emitting structure and the transparent conductive layer. The metal layer is set on the central portion of the top surface of the light emitting structure away from the substrate and forms a Schottky connection with the light emitting structure. The buffer layer surrounds the metal layer and forms an ohmic connection with the light emitting structure. | 2011-12-15 |
20110303938 | Group III nitride semiconductor light-emitting element - A group III nitride semiconductor light-emitting element having improved light extraction efficiency is provided. The light-emitting element has a plurality of dot-like grooves formed on a surface at the side joining to a p-electrode of a p-type layer. The groove has a depth reaching an n-type layer. Side surface of the groove is slanted such that a cross-section in an element surface direction is decreased toward the n-type layer from the p-type layer. Fine irregularities are formed on the surface at the side joining to an n-electrode of the n-type layer, except for a region on which the n-electrode is formed, and a translucent insulating film having a refractive index of from 1.5 to 2.3 is formed on the fine irregularities. Light extraction efficiency is improved by reflection of light to the n-type layer side by the groove and prevention of reflection to the n-type layer side by the insulating film. | 2011-12-15 |
20110303939 | WIRE-PIERCING LIGHT-EMITTING DIODE LAMPS - A wire-piercing light-emitting diode (LED) a lead frame having a first lead and a second lead. The first lead has a first transition portion and a first bottom portion with a first cutting member, and the second lead having a second transition portion and a second bottom portion with a second cutting member. | 2011-12-15 |
20110303940 | LIGHT EMITTING DEVICE PACKAGE USING QUANTUM DOT, ILLUMINATION APPARATUS AND DISPLAY APPARATUS - There is provided a light emitting device package using a quantum dot, an illumination apparatus and a display apparatus. The light emitting device package includes a light emitting device; a sealing part disposed in a path of light emitted from the light emitting device and having a lens shape; and a wavelength conversion part sealed within the sealing part and including a quantum dot. The light emitting device package uses the quantum dot as the wavelength conversion part to thereby achieve superior color reproducibility and light emission efficiency, and facilitates the control of color coordinates by adjusting the particle size and concentration of the quantum dot. | 2011-12-15 |
20110303941 | LIGHT EMITTING DEVICE AND LIGHTING SYSTEM - Provided are a light emitting device and a lighting system having the same. The light emitting device includes: a plurality of metal layers spaced to each other; a first insulation film disposed on an outer part of a top surface area of the plurality of metal layers and having an open area where a portion of top side of the plurality of metal layers is opened; a light emitting chip disposed on at least one of the plurality of metal layers and electrically connected to other metal layers; and a resin layer on the plurality of metal layers and the light emitting chip. | 2011-12-15 |
20110303942 | LED Structure - A light emitting device, a wafer for making the same, and method for fabricating the same are disclosed. The device and wafer include a first layer of a first conductivity type, an active layer, and a layer of a second conductivity type. The active layer overlies the first layer, the active layer generating light. The second layer overlies the active layer, the second layer having a first surface in contact adjacent to the active layer and a second surface having a surface that includes features that scatter light striking the second surface. A layer of transparent electrically conducing material is adjacent to the second surface and covered by a first layer of a dielectric material that is transparent to the light generated by the active layer. A mirror layer that has a reflectivity greater than 90 percent is deposited on the first layer of dielectric material. | 2011-12-15 |
20110303943 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An Organic light-emitting display apparatus capable of preventing permeation of external impurities such as oxygen or water vapor and enhancing impact resistance, and a method of manufacturing the organic light-emitting display apparatus. The organic light-emitting display apparatus includes a first substrate; a display unit disposed on the first substrate; a second substrate disposed over the display unit; and a sealing member by which the first substrate is combined with the second substrate. The sealant includes a first sealant which includes a filler and is spaced apart from the first substrate and the second substrate, and a second sealant which contacts the first substrate and the second substrate and covers at least a part of the first sealant. | 2011-12-15 |
20110303944 | Housing for an Optoelectronic Component - A housing ( | 2011-12-15 |
20110303945 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF PRODUCING A SEMICONDUCTOR ARRANGEMENT - A semiconductor arrangement including at least one lead arrangement with a top and a bottom opposite the top; a least one solder resist layer which partially covers the top and the bottom, at least sub-zones of the top and the bottom, which are not covered by the solder resist layer, forming electrical base members; an optoelectronic semiconductor element, which is mounted on at least one of the base members on the top of the lead arrangement and is connected electrically conductively therewith, and an encapsulant applied at least to the top of the lead arrangement, the encapsulant covering up the semiconductor element and lying at least partially against the solder resist layer, wherein the base members are bordered all round by the solder resist layer. | 2011-12-15 |
20110303946 | THERMAL STORAGE SYSTEM USING ENCAPSULATED PHASE CHANGE MATERIALS IN LED LAMPS - A phase change material (PCM) is used as thermal storage for lighting systems. The PCM is placed in a thermally conductive container in close contact with the lighting system. As the PCM absorbs heat, it changes from a solid to a liquid state, but the temperature of the PCM is clamped at its melting point temperature. For LED-based systems, the PCM is selected to have a melting point such that the junction temperatures of the LEDs in the system are maintained at approximately their optimum operating temperature inside the lighting system housing. Because the thermal conductivity of the molten PCM is poor, a low thermal resistance heat flow path is provided from the PCM to the container. | 2011-12-15 |
20110303947 | APPARATUS AND METHOD FOR PROTECTING ELECTRONIC CIRCUITS - Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type. | 2011-12-15 |
20110303948 | ESD and EMC optimized HV-MOS Transistor - Devices and circuits related to Electrostatic discharge (ESD) and Electromagnetic compatibility (EMC) are herein described. An ESD protection device is incorporated into a transistor in order to protect the gate of the transistor from excessive current loads related to ESD or EMC events. In an implementation, a device includes a first diode and a second diode that are electrically connected via their respective cathodes. The breakdown voltage of the first diode is lower than the breakdown voltage of the second diode in order to divert excessive current through the second diode. | 2011-12-15 |
20110303949 | SEMICONDUCTOR LIGHT-RECEIVING ELEMENT - A semiconductor light-detecting element includes: a semiconductor substrate of a first conductivity type; a light absorption recoupling layer of the first conductivity type, a multilayer reflection film of the first conductivity type, a light absorbing layer, and a window layer, which are laminated, in that order, on the semiconductor substrate; a doped region of a second conductivity type in part of the window layer; a first electrode connected to the doped region; and a second electrode connected to an underside of the semiconductor substrate. The band gap energy of the window layer is larger than the band gap energy of the light absorbing layer, and the band gap energy of the light absorption recoupling layer is smaller than the band gap energy of the semiconductor substrate. | 2011-12-15 |
20110303950 | FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET - Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region. | 2011-12-15 |
20110303951 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility. | 2011-12-15 |
20110303952 | High Electron Mobility Transistors And Methods Of Fabricating The Same - A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm. | 2011-12-15 |
20110303953 | GAS SENSOR AND METHOD FOR MANUFACTURING THE GAS SENSOR - It is an object to provide a gas sensor which is formed by a simple manufacturing process. Another object is to provide a gas sensor whose manufacturing cost is reduced. A transistor which includes an oxide semiconductor layer in contact with a gas and which serves as a detector element of a gas sensor, and a transistor which includes an oxide semiconductor layer in contact with a film having a gas barrier property and which forms a detection circuit are formed over one substrate by the same process, whereby a gas sensor using these transistors may be formed. | 2011-12-15 |
20110303954 | SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses. | 2011-12-15 |
20110303955 | Junction Field Effect Transistor Having A Double Gate Structure And Method of Making Same - A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region. | 2011-12-15 |
20110303956 | IMAGE SENSORS HAVING LIGHT SHIELD PATTERNS BETWEEN AN OPTICAL BLACK REGION AND AN ACTIVE PIXEL REGION - An image sensor having a light receiving region and an optical black region includes a semiconductor substrate, an interconnection disposed on the semiconductor substrate and extending along an interface between the light receiving region and the optical black region, and via plugs disposed between the interconnection and the semiconductor substrate and serving as light shielding members at the interface. The via plugs are arranged in a zigzagging pattern along the interface. | 2011-12-15 |
20110303957 | Concentric or Nested Container Capacitor Structure for Integrated Circuits - Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly | 2011-12-15 |
20110303958 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction. | 2011-12-15 |
20110303959 | Ultraviolet Energy Shield for Non-Volatile Charge Storage Memory - An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another. | 2011-12-15 |
20110303960 | LOW RESISTIVITY TUNGSTEN PVD WITH ENHANCED IONIZATION AND RF POWER COUPLING - Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal nitride film layer on the conductive film layer, a silicon-containing film layer on the refractory metal nitride film layer, and a tungsten film layer on the silicon-containing film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer. | 2011-12-15 |
20110303961 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A nonvolatile memory device including a cell array area in which a plurality of unit cells are arranged at least in one direction includes a plurality of memory transistors formed in the respective unit cells. Each memory transistor includes a gate pattern in which a tunnel insulating layer, a floating gate, an inter-gate insulating layer, and a control gate are laminated, and first and second junction areas arranged on opposite sides of the gate pattern, wherein the gate patterns are separated in the one direction by unit cells. The to nonvolatile memory device also includes a first conduction interconnection which extends in the one direction and is arranged in a position that overlaps the control gate and a plurality of first contacts, at least one of which is arranged for each of the control gates to connect the control gates and the first conduction interconnection. | 2011-12-15 |
20110303962 | NON-VOLATILE MEMORY DEVICES WITH NON-UNIFORM FLOATING GATE COUPLING - A memory device includes a substrate having an active region defined therein that extends linearly along a first direction. The device also includes a select line on the substrate and extending along a second direction to perpendicularly cross the active region, first and second floating gate patterns on the active region and spaced apart along the first direction, and first and second dielectric patterns on respective ones of the first and second floating gate patterns. The device further includes first and second word lines on respective ones of the first and second dielectric patterns and extending in parallel with the select line along the first direction. A first area of overlap of the first word line with the first floating gate pattern and the first dielectric pattern is less than a second area of overlap of the second word line with the second floating gate pattern and the second dielectric pattern. The first word line may be disposed between the select line and the second word line. | 2011-12-15 |
20110303963 | SEMICONDUCTOR DEVICES - A method of forming a semiconductor device includes forming line patterns on a substrate, the line patterns defining narrow and wide gap regions, forming spacer patterns in the narrow and wide gap regions on sidewalls of the line patterns, spacer patterns in the wide gap regions exposing an upper surface of the substrate, and spacer patterns in the narrow gap regions contacting each other to fill the narrow gap regions, forming an insulating interlayer to cover the spacer patterns and the line patterns, forming at least one opening through the insulating interlayer, the opening including at least one contact hole selectively exposing the upper surface of the substrate in the wide gap region, the contact hole being formed by using the spacer patterns in the narrow gap region as an etching mask, and forming a conductive pattern to fill the opening. | 2011-12-15 |
20110303964 | NONVOLATILE MEMORY, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE - Provided is a nonvolatile memory | 2011-12-15 |
20110303965 | SEMICONDUCTOR DEVICES - A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure. | 2011-12-15 |
20110303966 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 2011-12-15 |
20110303967 | Non-Volatile Memory With Air Gaps - Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements. | 2011-12-15 |
20110303968 | Nonvolatile Memory Array With Continuous Charge Storage Dielectric Stack - An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines. | 2011-12-15 |
20110303969 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors. | 2011-12-15 |
20110303970 | VERTICAL SEMICONDUCTOR DEVICES - A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively. | 2011-12-15 |
20110303971 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a three-dimensional semiconductor memory includes forming a plurality of stacked structures disposed on a substrate to be spaced apart from each other, each of the stacked structures including a plurality of dielectric patterns and a plurality of polysilicon patterns alternately stacked, forming a metal layer to cover sidewalls of the stacked structures and a top surface of the substrate exposed between the stacked structures, and forming stacked gate electrodes on the substrate and a conductive line in the substrate by performing a silicidation process between the metal layer and each of the polysilicon patterns and the substrate. | 2011-12-15 |
20110303972 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer. | 2011-12-15 |
20110303973 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD - The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film. | 2011-12-15 |
20110303974 | INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed. | 2011-12-15 |
20110303975 | Field effect transistor with self-aligned source and heavy body regions - A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench. | 2011-12-15 |
20110303976 | HIGH VOLTAGE CHANNEL DIODE - A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming. | 2011-12-15 |
20110303977 | LDPMOS STRUCTURE FOR ENHANCING BREAKDOWN VOLTAGE AND SPECIFIC ON RESISTANCE IN BICMOS-DMOS PROCESS - An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance. | 2011-12-15 |
20110303978 | Semiconductor Device Having an Enhanced Well Region - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region. | 2011-12-15 |
20110303979 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, includes a semiconductor layer, a first base region of a first conductivity type, a first source region of a second conductivity type, a second base region of the first conductivity type, a back gate region of the first conductivity type, a drift region of the second conductivity type, a drain region of the second conductivity type, a first insulating region, a second insulating region, a gate oxide film, a first gate electrode, a second gate electrode, a first main electrode and a second main electrode. These constituent elements are provided on the surface of the semiconductor layer. The distance between the first base region and the first insulating region is not more than 1.8 μm. The distance between the first base region and the first insulating region is shorter than a distance between the second base region and the second insulating region. | 2011-12-15 |
20110303980 | SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions. | 2011-12-15 |
20110303981 | Scheme to Enable Robust Integration of Band Edge Devices and Alternatives Channels - A method of forming a semiconductor device includes forming a buried oxide (BOX) layer on a semiconductor substrate, forming a silicon-on-insulator (SOI) layer on the BOX layer, depositing a hard mask including one of silicon, a nitride, and a metal oxide on the SOI layer, removing the hard mask from a first region of the semiconductor device, performing a cleaning process on the semiconductor device, wherein the hard mask is not removed from a second region of the semiconductor device by the cleaning process, epitaxially growing a semiconductor material in the first region of the semiconductor device, and removing the hard mask from the second region of the semiconductor device. | 2011-12-15 |
20110303982 | Resistive Device for High-K Metal Gate Technology and Method of Making the Same - A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity. | 2011-12-15 |
20110303983 | FINFET DEVICES AND METHODS OF MANUFACTURE - A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures. | 2011-12-15 |
20110303984 | Quadrangle MOS Transistors - A quadrangle transistor unit includes four transistor units. Each of the four transistor units includes a gate electrode. The gate electrodes of the four transistor units are aligned to four sides of a square. At least two of the four transistor units are connected in parallel. | 2011-12-15 |
20110303985 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer. | 2011-12-15 |