50th week of 2013 patent applcation highlights part 60 |
Patent application number | Title | Published |
20130332689 | Techniques For Reducing A Rate Of Data Transfer To At Least A Portion Of Memory - A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation. | 2013-12-12 |
20130332690 | Memory Systems and Memory Managing Methods of Managing Memory in a Unit of Memory Chunk - A method of managing a memory by a unit of memory chunk is provided. The method includes managing multiple memory chunks according to a chunk tree structure, managing program frequencies of the memory chunks of the memory according to a program of the memory, and allocating the memory chunks based on the program frequencies and the chunk tree structure. | 2013-12-12 |
20130332691 | EXTENDED UTILIZATION AREA FOR A MEMORY DEVICE - Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof. | 2013-12-12 |
20130332692 | COMPUTING SYSTEM AND CONTROLLING METHODS FOR THE SAME - Provided is a computer system capable equalizing the storage capacity immediately and reliably to multiple real logical areas dynamically providing storage capacity to virtual logical areas. | 2013-12-12 |
20130332693 | ALLOCATING STORAGE MEMORY BASED ON FUTURE FILE SIZE OR USE ESTIMATES - A method for allocating storage memory space is provided. The method involves receiving a request for storage memory allocation for a file of a current size; estimating a future size of the file, different than the current size of the file, based at least on a particular attribute associated with the file; and causing allocation of storage memory space for storage of the file based on the future size of the file. | 2013-12-12 |
20130332694 | MANAGING AN ABSTRACTION OF MULTIPLE LOGICAL DATA STORAGE CONTAINERS - Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated. | 2013-12-12 |
20130332695 | INFORMATION PROCESSING APPARATUS AND METHOD AND COMPUTER-READABLE MEDIUM - There is provided an information processing apparatus including a primary storage apparatus configured by combining a plurality of memories each having a different upper limit of a number of possible rewrites, and an allocation management section configured to allocate a storage area of data to be stored in the primary storage apparatus to one of the plurality of memories based on a rewrite frequency of the data. | 2013-12-12 |
20130332696 | SHARED PHYSICAL MEMORY - A computer implemented method for sharing physical memory among logical partitions. A computer reserves physical memory of a Central Electronic Complex (CEC) for communication within the CEC as a shared memory pool. The computer creates a first logical partition using resources of the CEC that are not reserved as the shared memory pool. The computer creates a second logical partition using resources of the CEC that are not reserved as the shared memory pool. The computer creates a virtual local area network (VLAN) having at least two addresses within the CEC. The computer allocates a portion of the shared memory to the VLAN as the shared memory pool. | 2013-12-12 |
20130332697 | STORAGE SUBSYSTEM AND STORAGE CONTROL METHOD - According to the prior art storage system, in order to add a storage device to a pool after a storage system has been operated for a certain period of time, the performance may be varied significantly according to the access performance of the application using the pool, and it was not possible to realize an optimum allocation corresponding to the operation form if the storage device is set to be included in a pool of a given tier based on the type of the storage device. Therefore, the present invention provides a system in which a performance test is performed in accordance with an access tendency of the application using the pool to thereby compute the tier capable of having the storage device added thereto, based on which the storage device can be allocated to an appropriate pool. | 2013-12-12 |
20130332698 | DATA PRESERVATION METHOD - A data preservation method applicable to an electronic device operating with an open operating system having a data storage region includes creating a disk partition; creating an authority to access the disk partition and get linked to a group ID (GID); mounting the disk partition in a directory having a user ID (UID) and the GID; and giving authority related to the linked GID to an application having the authority, so as to access data in the disk partition having the GID. The authority, coupled with the GID, allows a specific disk partition to store data generated as a result of execution of the application. Even if the application causes a UID change later for some reason, the application bestowed with the authority can still access data through the GID, thereby preserving data. | 2013-12-12 |
20130332699 | TARGET BUFFER ADDRESS REGION TRACKING - Embodiments relate to target buffer address region tracking. An aspect includes receiving a restart address, and comparing, by a processing circuit, the restart address to a first stored address and to a second stored address. The processing circuit determines which of the first and second stored addresses is identified as a same range and a different range to form a predicted target address range defining an address region associated with an entry in the target buffer. Based on determining that the restart address matches the first stored address, the first stored address is identified as the same range and the second stored address is identified as the different range. Based on determining that the restart address matches the second stored address, the first stored address is identified as the different range and the second stored address is identified as the same range. | 2013-12-12 |
20130332700 | Cloud Storage Arrangement and Method of Operating Thereof - There is provided a storage arrangement and a method of operating thereof. The storage arrangement comprises a first storage system and one or more second storage systems operatively coupled to the first storage system. First control layer is operable to handle a first logical address space comprising a first logical group characterized by a plurality of logical block addresses; first control layer comprises a first mapping module handling a first mapping structure associated with first logical group. Each second control layer comprises, respectively, a second mapping module handling a second mapping structure associated with first logical group. The first mapping structure is configured to provide mapping between logical addresses related to first logical group and corresponding addresses related to first physical address spaces, and/or to point to respective second mapping structure configured to provide mapping between these logical addresses and corresponding addresses related to respective second physical address spaces. | 2013-12-12 |
20130332701 | APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION - An apparatus and method are described for selecting elements to be used in a vector computation. For example, a method according to one embodiment includes the following operations: specifying whether to identify the first, last or next after last active element of an input mask register using an immediate value; identifying the first, last or next after last active element in the input mask register according to the immediate value; reading a value from an input vector register corresponding to the identified first, last or next after last active element in the input mask register; and writing the value to an output vector register. | 2013-12-12 |
20130332702 | CONTROL FLOW IN A HETEROGENEOUS COMPUTER SYSTEM - Methods, apparatuses, and computer readable media are disclosed for control flow on a heterogeneous computer system. The method may include a first processor of a first type, for example a CPU, requesting a first kernel be executed on a second processor of a second type, for example a GPU, to process first work items. The method may include the GPU executing the first kernel to process the first work items. The first kernel may generate second work items. The GPU may execute a second kernel to process the generated second work items. The GPU may dispatch producer kernels when space is available in a work buffer. The GPU may dispatch consumer kernels to process work items in the work buffer when the work buffer has available work items. The GPU may be configured to determine a number of processing elements to execute the first kernel and the second kernel. | 2013-12-12 |
20130332703 | Shared Register Pool For A Multithreaded Microprocessor - A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register. | 2013-12-12 |
20130332704 | Method for Improving Performance of a Pipelined Microprocessor by Utilizing Pipeline Virtual Registers - A method for improving performance of a pipelined microprocessor by utilizing pipeline virtual registers allows for either decreased register spillage or decreased area and power consumption of a microprocessor. The microprocessor takes advantage of register bypass logic to write short-lived values to virtual registers, which are discarded instead of being written to the register bank, thus reducing register pressure by avoiding short-lived values being written to the register bank. | 2013-12-12 |
20130332705 | PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY - A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region. | 2013-12-12 |
20130332706 | ELECTRONIC DEVICE, ELECTRONIC DEVICE COOPERATING SYSTEM, AND ELECTRONIC DEVICE CONTROLLING METHOD - There are included a communication part performing communication with other device; a command managing part transmitting a command of an own device to other device and receiving a command of other device to acquire the command of other device by the communication part, and managing the command of the own device and the command of other device; and a command processing part executing processing of a function corresponding to the command of the own device by the own device when a command selected from the commands managed by the command managing part is the command of the own device, and executing processing of a function corresponding to the command of other device by the other device when the command selected is the command of the other device. | 2013-12-12 |
20130332707 | SPEED UP BIG-NUMBER MULTIPLICATION USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES - A processing apparatus may be configured to include logic to generate a first set of vectors based on a first integer and a second set of vectors based on a second integer, logic to calculate sub products by multiplying the first set of vectors to the second set of vectors, logic to split each sub product into a first half and a second half and logic to generate a final result by adding together all first and second halves at respective digit positions. | 2013-12-12 |
20130332708 | PROGRAMMABLE PARTITIONABLE COUNTER - An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor. | 2013-12-12 |
20130332709 | SET SAMPLING CONTROLS INSTRUCTION - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 2013-12-12 |
20130332710 | MODULATING DYNAMIC OPTIMAIZATIONS OF A COMPUTER PROGRAM - Technologies and implementations for modulating dynamic optimizations of a computer program during execution are generally disclosed. | 2013-12-12 |
20130332711 | SYSTEMS AND METHODS FOR EFFICIENT SCHEDULING OF CONCURRENT APPLICATIONS IN MULTITHREADED PROCESSORS - Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride as disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching. | 2013-12-12 |
20130332712 | BRANCH PREDICTION TABLE INSTALL SOURCE TRACKING - Embodiments relate to branch prediction table install source tracking. An aspect includes a system for branch prediction table install source tracking. The system includes memory configured to store instructions accessible by a processor. The processor includes a branch target buffer, where the processor is configured to perform a method. The method includes receiving at the branch target buffer a request to install a branch target buffer entry corresponding to a branch instruction for branch prediction, and identifying a source of the request as an install source of the branch target buffer entry. The method further includes storing an install source identifier in the branch target buffer based on the install source. | 2013-12-12 |
20130332713 | FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION - Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method. The method includes determining that searching of the branch target buffer is to be performed under FIT control. A current search address for searching of the branch target buffer is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from the FIT structure. The searching of the branch target buffer is re-indexed based on the FIT next-search address. It is determined whether the searching at the saved current search address located the branch prediction. | 2013-12-12 |
20130332714 | FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION - Embodiments relate to using a fast index tree for accelerated branch prediction. A computer-implemented method includes determining, by a computer, that searching of a branch target buffer is to be performed under FIT control. A current search address is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from a FIT structure. The searching is re-indexed based on the FIT next-search address. Based on locating the branch prediction, the searching is continued under FIT control with the current search address set based on the FIT next-search address. Based on failing to locate the branch prediction, the searching is re-indexed with the saved current search address, and the searching is performed without FIT control. | 2013-12-12 |
20130332715 | GLOBAL WEAK PATTERN HISTORY TABLE FILTERING - Embodiments relate to global weak pattern history table (PHT) filtering. An aspect includes receiving a search address associated with a branch prediction, and receiving a prediction strength indicator and a tag from a PHT. Based on determining that the tag matches the search address and the prediction strength indicator is weak, an accuracy counter is compared to a comparison threshold to determine whether a PHT direction prediction from the PHT is more likely accurate than a branch history table (BHT) direction prediction from a BHT. The PHT direction prediction is selected as a direction prediction based on determining that the accuracy counter indicates that the PHT direction prediction is more likely accurate than the BHT direction prediction. The BHT direction prediction is selected as the direction prediction based on determining that the accuracy counter indicates that the BHT direction prediction is more likely accurate than the PHT direction prediction. | 2013-12-12 |
20130332716 | BRANCH TARGET BUFFER PRELOAD TABLE - Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry. | 2013-12-12 |
20130332717 | MULTI-THREAD PROCESSOR - A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector. | 2013-12-12 |
20130332718 | ACTIVATION-BASED REGULATORY UPDATES - The disclosed embodiments provide a system that activates an electronic device. The system includes an activation server that receives an activation request from the electronic device. Upon detecting, based on the activation request, that the electronic device requires a regulatory update, the activation server adds the regulatory update to an activation payload for the electronic device. Finally, the activation server transmits the activation payload to the electronic device. | 2013-12-12 |
20130332719 | System and Method for Providing Input/Output Functionality to a Processing Node - A remote component controller of a server rack includes a real time clock information unit to maintain real clock time and to respond to requests for real time clock information, and a communication module to receive over a communication link a request from a processing node of the server rack for real time clock information, to forward the request to the real time clock information unit, to receive from the real time clock information unit a response to the request, and to transmit the response to the request to the processing node over the communication link. | 2013-12-12 |
20130332720 | SYSTEMS AND METHODS FOR THERMAL MITIGATION WITH MULTIPLE PROCESSORS - A wireless communication device for thermal mitigation with multiple processors is described. The wireless communication device includes a first communications processor that processes a data call. The wireless communication device also includes a second communications processor coupled to the first communications processor. The first communications processor performs a thermal mitigation operation by sending instructions to the second communications processor when at least one thermal threshold is reached. The second communications processor receives and executes the instructions. | 2013-12-12 |
20130332721 | QUIET HOURS FOR NOTIFICATIONS - In some implementations, a computing device can be configured to automatically turn off notifications when generating a notification would cause a disturbance or be unwanted by a user. The device can be configured with quiet hours during which notifications that would otherwise be generated by the computing device can be suppressed. In some implementations, quiet hours can be configured as a time period with a start time and an end time. In some implementations, quiet hours can be derived from application data. For example, calendar data, alarm clock data, map data, etc. can be used to determine when quiet hours should be enforced. In some implementations, the device can be configured with exceptions to quiet hour notification suppression. In some implementations, the user can identify contacts to which the quiet hours notification suppression should not be applied. | 2013-12-12 |
20130332722 | REFACTORING DEVICE, REFACTORING METHOD AND PROGRAM - In a method for obtaining a system by combining program components, the relocation of the program components can be facilitated. | 2013-12-12 |
20130332723 | SYSTEMS AND METHODS FOR SECURE FILE PORTABILITY BETWEEN MOBILE APPLICATIONS ON A MOBILE DEVICE - Systems and methods for secure file portability between mobile applications in a cloud-based environment or cloud-based collaboration and file sharing environment. In one embodiment, a server-based key generation service generates an encryption key that is unique to each file transfer transaction between mobile applications accessed via a mobile device. Data packages leaving a mobile application are then encrypted using the encryption key to provide secure file portability between mobile applications. In another embodiment, a background service triggered by a mobile application detects when a user is logged out of the mobile application and revalidates the user session with the mobile application to maintain portability of files between mobile applications. The background service presents a minimal user interface to get the user's credentials for the mobile application, without the user having to switch to the mobile application, and obtains an authentication token from a remote server using the user's credentials. | 2013-12-12 |
20130332724 | User-Space Enabled Virtual Private Network - This invention includes apparatus, systems, and methods to establish a virtual private network (“VPN”), or a secured network for authenticated and encrypted data transmission to prevent disclosure of private information to unauthorized parties. This invention provides secure and authenticated data transmission from a communication device to another device over any public or private network while using existing standard applications such as email, VoIP, internet browsers, ISR applications, video conferencing, telecommuting, inventory tracking and control, etc. without the need to secure or add encryption features into each specific application. This invention provides the opportunity to selectively secure one or more existing applications with configuration changes that can be made at the user-space level of the software stack and without need for higher level software stack access, such as root access. | 2013-12-12 |
20130332725 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus includes a communication unit and a control unit. The control unit is configured to be capable of controlling the communication unit to receive, from a different information processing apparatus, storage location information representing a storage location of key information necessary for encrypted wireless communication with the different information processing apparatus, to access the storage location represented by the storage location information to receive the key information, and to establish a connection with the different information processing apparatus by using the received key information. | 2013-12-12 |
20130332726 | SYSTEM AND METHOD FOR VALIDATING SCEP CERTIFICATE ENROLLMENT REQUESTS - A system and method for validating SCEP certificate enrollment that enforces the pairing of a SCEP challenge password and a set of expected certificate request content. A SCEP Validation Service or software residing in another system component whether a certificate request is legitimate by comparing it to registered SCEP challenges and associated expected certificate request content. This system and method addresses a privilege-escalation vulnerability in prior SCEP-based systems that could lead to a practical attack. | 2013-12-12 |
20130332727 | ACCESS TOKEN EVENT VIRTUALIZATION - Systems, devices, and methods are disclosed for access token event virtualization. An access token may be received at a central server computer system from a terminal device. The access token event may indicate that an access device associated with the terminal device has received an access token. A virtual session associated with the received access token event may be identified at the central server computer system, and a set of rules may be applied to the received access token event and the identified virtual session to determine an action associated with the identified virtual session. The central server computer system may transmit an instruction to at least one device communicatively coupled with the central server computer system to carry out the action associated with the identified virtual session. | 2013-12-12 |
20130332728 | ELECTRONIC FILE ACCESS CONTROL SYSTEM AND METHOD - A method for controlling access to a digital file includes: associating digital content with a header, the header including data identifying a permitted access identity corresponding to a physical key removable from a reading computer. The method also includes encrypting the header and the digital content, the header being susceptible to decryption separate from the content by a key interface. | 2013-12-12 |
20130332729 | SEARCH SYSTEM, SEARCH METHOD OF SEARCH SYSTEM, INFORMATION PROCESSING DEVICE, SEARCH PROGRAM, CORRESPONDING KEYWORD MANAGEMENT DEVICE, AND CORRESPONDING KEYWORD MANAGEMENT PROGRAM - A searchable encryption resistant to frequency analysis. A conversion rule management device generates a conversion rule table associating a search keyword with a conversion keyword group. Based on the conversion rule table, a data registration device generates registration data associating encrypted data with an encrypted keyword, and registers the registration data in a server device. An information processing device obtains from the conversion rule table a conversion keyword group associated with a specified search keyword, generates an encrypted keyword group, and requests a data search by specifying the encrypted keyword group. Using as a search key an encrypted keyword included in the encrypted keyword group, the server device searches for encrypted data associated with the search key, and returns searched encrypted data. The information processing device decrypts the searched encrypted data, and outputs as a search result search data obtained by decryption. | 2013-12-12 |
20130332730 | EMBEDDED MODULE SYSTEM WITH ENCRYPTED TOKEN AUTHENTICATION SYSTEM - Method and systems for accessing and providing protected content are disclosed herein. An example system includes a client configured to access a third-party application to receive at least one piece of content associated with a first identifier; wherein the client comprises a token generator configured to generate a token requesting the at least one piece of content, the token comprising at least one private encryption key and the first identifier. The system further includes an embedded module system comprising a database of content, the content separated into a plurality of modules, the embedded module system configured to receive the token and decrypt the at least one private encryption key. The embedded module system may further authorize the client by comparing the first identifier with a second identifier stored in the database. | 2013-12-12 |
20130332731 | System for Determining Whether or Not Automaton Satisfies Context-free Grammar - A server that holds context-free grammar and is connectable to a client that holds an automaton. The server compares an edge pair with an encrypted string value such that the encrypted string value is hidden from the client. The edge pair represents a string for an encrypted value in which a nonfinal character is made to correspond to a state before and the state after held by the client and an encrypted string value represents a string for an encrypted value in which each of a plurality of nonfinal characters contained in a substituted symbol string for a production rule for the context-free grammar is given correspondence with an assigned state before and state after. The encrypted value in which in which the encrypted string value matches the edge pair has been encrypted is sent to the client along with the state before and state after that has been assigned. | 2013-12-12 |
20130332732 | SYSTEM AND METHOD FOR GENERATING AND MANAGING PRODUCT AUTHENTICATION CODES - A method for generating product authentication codes comprises allocating a lot identification value and a total lot size for an order of a plurality of product authentication codes, generating the plurality of product authentication codes based upon the lot identification value and the total lot size, and updating a counter table on an authentication server with the total lot size for the order of the authentication codes. A method for authenticating product codes comprises receiving a product code from a user of a product, decrypting the product code to obtain a sequence counter number unique to the product code and comparing the decrypted sequence counter number to a table of valid sequence counter number values to determine its authenticity. If the decrypted sequence counter number is authentic, it is added to an authentication table for future reference when operating to confirm a previous authentication of the sequence counter number. | 2013-12-12 |
20130332733 | METHOD FOR SECURE REMOTE BACKUP - The present invention is directed to an architecture and mechanism for securely backing up files and directories on a local machine onto untrusted servers over an insecure network. | 2013-12-12 |
20130332734 | PROCESS AND SYSTEM FOR DATA TRANSMISSION - In a method and a system for data transmission, authentication data and an electronic key may be generated, with the electronic key being stored as assigned to the authentication data. Data may be encrypted, such as by a central communications device, into encrypted data, using at least part of the electronic key. Based on reception of the authentication data from a communications terminal, at least a portion of the electronic key and the encrypted data may be transmitted from the central communications device to the communications terminal. | 2013-12-12 |
20130332735 | METHOD AND APPARATUS FOR PROTECTING DIGITAL CONTENT IN A STORAGE DEVICE - Techniques for protecting digital content in a storage device from pirate and illegal use are described. According to one aspect of the techniques, a method for protecting digital content stored in a storage device from illegally accessing by a host, comprises: exchanging data between the storage device and the host to achieve a mutual authentication between the storage device and the host; disabling an encryption/decryption module in the storage device to prohibit the host from reading out the digital content decrypted by the encryption/decryption module until the authentication of the storage device to the host passes; and disabling the host to prohibit the host from reading out the digital content decrypted by the encryption/decryption module if the authentication of the host to the storage device fails. Thereby, pirate and illegal use of the digital content stored in the storage device are effectively prevented or decreased. | 2013-12-12 |
20130332736 | ELECTRONIC KEY REGISTRATION SYSTEM - An immobilizer ECU transmits a vehicle ID code and a SEED code, which is read from an electronic key, to a data center online. The data center generates an encryption key from the received SEED code and a first logic, and generates a further SEED code from the encryption key, the vehicle ID code, and a second logic. The immobilizer ECU obtains the further SEED code online from the data center, generates the encryption key from the obtained further SEED code, the vehicle ID code, and the second logic, and stores the encryption key. | 2013-12-12 |
20130332737 | METHOD AND APPARATUS OF SECURELY PROCESSING DATA FOR FILE BACKUP, DE-DUPLICATION, AND RESTORATION - Disclosed are an apparatus and method of restoring at least one data file. The method may include retrieving the at least one data file to be restored from a data storage location, determining that the at least one data file is a link file, and regenerating a previously exchanged shared secret. The method may also include decrypting a key from the link file using the shared secret, and retrieving data from a data repository location to be restored. | 2013-12-12 |
20130332738 | COMMUNICATING IN A PEER-TO-PEER COMPUTER ENVIRONMENT - Communicating in a peer-to-peer computer environment. A request is received from a user device at a peer provider node computer system, wherein the request is signed by a private key. Provided a public key verifies the private key, providing potential peers to the user device from the peer provider node computer system such that the user device is enabled to utilize the peer-to-peer computer environment for a communication according to user requirements. | 2013-12-12 |
20130332739 | METHOD OF SHARING A SESSION KEY BETWEEN WIRELESS COMMUNICATION TERMINALS USING A VARIABLE-LENGTH AUTHENTICATION CODE - Disclosure relates to a method of sharing a session key between wireless communication terminals using a variable-length authentication code. The method includes: generating a public key by using an own private key; generating a message including the public key and a first random number and encoding the message using an own secret key to exchange an encrypted message with the other terminal; decoding the encrypted message of the other terminal by receiving a secret key of the other terminal; generating an authentication code by calculating the first random number and a second random number included in the decoded message; obtaining a medium value from the authenticated code; and generating a session key by using a public key included in the decoded message of the other terminal. | 2013-12-12 |
20130332740 | Visualization of Trust in an Address Bar - Described are a system and method for presenting security information about a current site or communications session. Briefly stated, a browsing software is configured to receive a certificate during a negotiation of a secure session between a local device and a remote device. The certificate includes security information about a site maintained at the remote device. The security information is displayed to a user of the browsing software in a meaningful fashion to allow the user to make a trust determination about the site. Displaying the security information may include presenting a certificate summary that includes the most relevant information about the certificate, such as the name of the owner of the site and the name of the certificating authority of the certificate. | 2013-12-12 |
20130332741 | KEY CAMOUFLAGING USING A MACHINE IDENTIFIER - A method is provided for generating a human readable passcode to an authorized user including providing a control access datum and a PIN, and generating a unique machine identifier for the user machine. The method further includes modifying the controlled access datum, encrypting the controlled access datum using the PIN and/or a unique machine identifier to camouflage the datum, and generating a passcode using the camouflaged datum and the PIN and/or the unique machine identifier. A mobile user device may be used to execute the method in one embodiment. The passcode may be used to obtain transaction authorization and/or access to a secured system or secured data. The unique machine identifier may be defined by a machine effective speed calibration derived from information collected from and unique to the user machine. | 2013-12-12 |
20130332742 | SPEED UP SECURE HASH ALGORITHM (SHA) USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES - A processing apparatus may comprise logic to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks, logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks, and logic to generate a message digest conforming to the selected SHA algorithm. | 2013-12-12 |
20130332743 | SPEED UP SECURE HASH ALGORITHM (SHA) USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES - A processing apparatus comprises logic to, according to a selected secure hash algorithm (SHA) algorithm, generate hash values by preparing message schedules for a plurality of message blocks in parallel using single instruction multiple date (SIMD) instructions and performing compression in serial, and logic to generate a message digest conforming to the secure hash algorithm (SHA) algorithm. | 2013-12-12 |
20130332744 | METHOD AND SYSTEM FOR ACCELERATING CRYPTOGRAPHIC PROCESSING - A method, an apparatus, and a non-transitory computer readable medium for accelerating cryptographic processing are presented. A cryptographic algorithm is parallelized, which includes breaking the cryptographic algorithm into components, parallelizing an entire component if the component is fully parallelizable, parallelizing part of a component if the component is partially parallelizable, and sequentially executing a component if the component is not parallelizable. Processing of the parallelizable component or the partially parallelizable component is distributed to one or more parallelized devices. The parallelized devices include at least one of: a graphics processing unit or a cryptographic processing device, which may include an integrated cryptographic processor or a cryptographic co-processor. | 2013-12-12 |
20130332745 | SECURE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) ARCHITECTURE - A method and system for configuring a field-programmable gate array (FPGA) includes receiving an encrypted FPGA load-decryption key at an FPGA from a remote key-storage device. The remote key-storage device may be external to and operatively connected with the FPGA. The encrypted FPGA load-decryption key is decrypted using a session key, which may be stored at both the FPGA and the remote key-storage device. Encrypted FPGA-configuration data is received at the FPGA, and decrypted and authenticated using the decrypted FPGA load-decryption key. The decryption of the FPGA-configuration data may indicate a cryptographic state associated with the FPGA-configuration data, which may be used in recurring authentication of the FPGA-configuration data. For recurring authentication, a challenge message may be received at the FPGA from an authentication device, which may be encrypted using the cryptographic state and the session key to generate a response message. The response message may then be sent to the authentication device to determine authenticity of the FPGA-configuration data. | 2013-12-12 |
20130332746 | METHOD, A DEVICE AND A COMPUTER PROGRAM SUPPORT FOR EXECUTION OF ENCRYPTED COMPUTER CODE - A device stores program code in a plurality of slots in its memory. When a processor of the device receives a call to an encrypted function, it uses a slot table to find the location of the cipher function and the cipher module and the key to decrypt the encrypted module. The encrypted module is decrypted, executed, re-encrypted and moved to a new memory slot. The cipher function used is moved to a further new slot and the slot table is updated. Also provided is a method and a computer program support. The invention can make it more difficult to analyse execution traces of the program code. | 2013-12-12 |
20130332747 | REMOVABLE DRIVE WITH DATA ENCRYPTION - A removable drive such as a USB drive or key is provided for connecting to computer devices to provide secure and portable data storage. The drive includes a drive manager adapted to be run by an operating system of the computer device. The drive manager receives a password, generates a random key based on the password, encrypts a user-selected data file in memory of the computer device using the key, and stores the encrypted file in the memory of the removable drive. The drive manager performs the encryption of the data file without corresponding encryption applications being previously loaded on the computer system. The drive manager may include an Advanced Encryption Standard (AES) cryptography algorithm The drive manager generates a user interface that allows a user to enter passwords, select files for encryption and decryption, and create folders for storing the encrypted files on the removable drive. | 2013-12-12 |
20130332748 | Bi-Modal Power Delivery Scheme for Integrated Circuits that Enables Fine Grain Power Management for Multiple Functional Blocks on a Single Die - Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources. | 2013-12-12 |
20130332749 | ELECTRONIC APPARATUS, CALCULATION METHOD, PROGRAM, AND INFORMATION PROCESSING APPARATUS - An electronic apparatus that includes a CPU and at least one device and that is identical to or different from an electronic apparatus in which the CPU is capable of simultaneously executing multiple applications. The electronic apparatus includes: a determiner that determines usage rates of the CPU and the device for each application being executed, on the basis of at least one of statistical information and log information of the CPU and the device; a divider that determines proportions of power consumptions of the CPU and the device relative to a power consumption of the entire electronic apparatus; and an estimator that estimates a proportion of a power consumption for each application relative to the power consumption of the entire electronic apparatus, on the basis of the determined usage rates and the determined proportions. | 2013-12-12 |
20130332750 | SEMICONDUCTOR DEVICE - A first overcurrent detection unit detects whether a drain-source voltage of an output transistor is greater than or equal to a first reference value and outputs a first detection signal. A second overcurrent detection unit detects whether an output current passing through the output transistor is greater than or equal to a second reference value and outputs a second detection signal. When receiving the first detection signal indicating that the drain-source voltage is greater than or equal to the first reference value, a latch circuit latches the second detection signal; when receiving the first detection signal indicating that the drain-source voltage is smaller than the first reference value, the latch circuit outputs the second detection signal without latching it. Based on the output of the latch circuit, the drive circuit controls the output transistor to either turn it off or turn it on and off alternately. | 2013-12-12 |
20130332751 | POWER SUPPLY AND PROGRAM - A power supply includes a storage device and a virtual machine power data transfer unit. The storage device is configured to store virtual machine power management data in which an identifier of a virtual machine run in emulation by a virtual host computer fed with power from the power supply, and power information on the virtual machine are associated with each other. The virtual machine power data transfer unit is configured to, when a virtualization management server migrates the virtual machine run in emulation by the virtual host computer fed with power from the power supply to a migration destination virtual host computer fed with power from a different power supply, extract the power information on the migrated virtual machine out of the virtual machine power management data, and transfer the power information to the different power supply. | 2013-12-12 |
20130332752 | POWER SUPPLY AND PROGRAM - A power supply includes a virtual machine state acquisition unit and a virtual machine management unit. The virtual machine state acquisition unit is configured to: send each of the virtual host computers in virtual host list data a request to acquire information on a virtual machine run in emulation by the virtual host computer; acquire, from each of the virtual host computers, the information on the virtual machine run in emulation by the virtual host computer; and create virtual machine management data in which an identifier of the virtual host computer, an identifier of the virtual machine thereof, and the acquired information on the virtual machine are associated with each other. The virtual machine management unit is configured to read the virtual machine management data and input a command related to a virtual power source of the virtual machine. | 2013-12-12 |
20130332753 | DYNAMIC POWER LIMIT SHARING IN A PLATFORM - A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention. | 2013-12-12 |
20130332754 | DATA STORAGE SYSTEM ENERGY AUDIT - An apparatus and associated methodology for a data storage system having an enclosure containing a plurality of drives that are individually selectable to transfer data corresponding to an execution of input/output (I/O) commands between the data storage system and another device. A memory in the enclosure temporarily stores unexecuted I/O commands, and a power supply device is capable of simultaneously operating all of the plurality of drives in support of multiple transfers of data. A power management device operably reduces a power output of the power supply device in response to a forecasted interruption in the transfer of data with one of the drives at a time when an unexecuted I/O command for the one of the drives resides in the memory. | 2013-12-12 |
20130332755 | POWER MANAGEMENT ENHANCEMENT - In one embodiment described herein, a device having an account permitting access to network-based storage, receives a push notification indicating that one or more assets has been shared by another person. In response to the push notification, the device begins downloading the new asset to the device, while starting two timers. When the first timer finishes, the user is notified about the new asset that is available. When the second timer finishes, the download, if still in progress, is interrupted to save power. | 2013-12-12 |
20130332756 | NEAR FIELD COMMUNICATION DEVICE AND POWER MANAGEMENT METHOD OF ELECTRONIC APPARATUS COMPRISING THE SAME - A near field communication device includes an RF power unit that generates an RF power supply voltage through wireless communication with an external communication device, a power detecting unit that detects an output level of a battery connected to the near field communication device, a driving control unit that controls the near field communication device, and a switching control unit that controls a supply of a power supply voltage to the driving control unit from the RF power unit or the battery. The switching control unit controls the supply of the power supply voltage based on at least one of the output level of the battery, a power on/off state of an electronic apparatus including the near field communication device, whether the electronic apparatus is connected to the battery, and whether the RF power supply voltage is generated. | 2013-12-12 |
20130332757 | SYSTEM AND METHOD FOR CONTROLLING TEMPERATURE IN AN INFORMATION HANDLING SYSTEM - Systems and methods for controlling temperature in an information handling system is provided. In certain embodiments, a method may include receiving a desired threshold value, determining if a current real-time system value exceeds the desired threshold value, determining if a power shedding mode is enabled, if the power shedding mode is enabled, adjusting power supplied to the information handling system, and if the power shedding mode is not enabled, dynamically adjusting a fan speed of a cooling fan associated with the information handling system. | 2013-12-12 |
20130332758 | SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION PROCESSING APPARATUS - In a semiconductor integrated circuit having a power domain and a mechanism for a power supply shutoff, when a power supply to the power domain is started, if a clock for an initialization operation is supplied in a state where a voltage to the power domain is unstable, power consumption during the initialization operation increases. Thus, the clock for the initialization operation of the power domain is supplied after detecting that the voltage supplied to the power domain is stabilized. | 2013-12-12 |
20130332759 | Inter-Processor Communication Channel Including Power-Down Functionality - Apparatuses and methods are disclosed for implementing an inter-processor communication channel including power-down functionality. In one embodiment, the apparatus may comprise a first integrated circuit (IC), a second IC coupled to the first IC via a communication interface, wherein the first IC is in one or more low power states and unable to monitor the communication interface. The apparatus may further comprise an inter-processor communication (IPC) channel coupled between the first and second ICs, wherein the IPC channel is separate from the communication interface and wherein the second IC generates at least one advisory signal to the first IC via the IPC channel. | 2013-12-12 |
20130332760 | THERMAL-BASED ACOUSTIC MANAGEMENT - At least certain embodiments of the disclosures relate to methods, devices, and data processing systems for thermal-based acoustic management. In one embodiment, a computer-implemented method defers one or more background tasks during normal operation of a system if the system has a reduced performance feature that allows reduced or throttled performance in a non-user state. The system enters a low power state (e.g., sleep state) to cool the system after a period of normal operation. The system enters a different low power state (e.g., dark wake state) with a reduced performance and performs at least one of the deferred background tasks while in this low power state without needing a cooling mechanism. | 2013-12-12 |
20130332761 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 2013-12-12 |
20130332762 | NETWORK NODE HAVING A POWER SAVING MODE - A network node has an interface which has different modes of operation, including at least a power saving mode and a normal operating mode. The node has a power saving mode management module for maintaining information about whether the interface is in the power saving mode of operation. The power saving mode management module is able to make available to one or more layers higher than the physical layer of the interface information about whether the interface is in the power saving mode of operation. | 2013-12-12 |
20130332763 | POWER-GATED MEMORY DEVICE WITH POWER STATE INDICATION - A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up. | 2013-12-12 |
20130332764 | INTELLIGENT INTER-PROCESSOR COMMUNICATION WITH POWER OPTIMIZATION - One embodiment of the present invention provides a system that facilitates intelligent inter-processor communication with power optimization. The system comprises a memory, a first router, a second router, a first physical link coupled between the first router and the second router, and a second physical link coupled between the first router and the second router. Furthermore, the system comprises a first communication bus implemented on the first physical link, as well as a second communication bus implemented on the second physical link. Note that the second communication bus provides lower power consumption and lower bandwidth than the first communication bus. During operation, the system receives a packet at the first router, wherein the packet is destined for the second router. Next, the system selects either the first communication bus or the second communication bus over which to route the packet. Finally, the system routes the packet according to the selection. | 2013-12-12 |
20130332765 | POWER SUPPLY ACOUSTIC NOISE MITIGATION - A method and system for reducing acoustic power supply noise, specifically acoustic noise related to power supply switching frequencies in a computing device, is disclosed. In one embodiment, a controller can monitor power consumed by the computing device, and an operational state of the computing device can be determined. If the computing device is in a first operational state and the power consumed is greater than a threshold amount, then the power supply can be operated at a first switching frequency or mode of operation, thereby avoiding switching frequencies that can produce acoustic noise. | 2013-12-12 |
20130332766 | METHOD AND SYSTEM FOR CALCULATING A CLOCK FREQUENCY OF A CLOCK SIGNAL FOR AN IC CARD - A clock frequency of a clock signal is calculated, with the clock signal being received by an IC card from a terminal or an internal clock within the IC card. A first time-stamp is received from the terminal, and a first value of the timer is set. The timer of the IC card is started when the first time-stamp is received. A second time-stamp is received, and a second value of the timer is read when the second time-stamp is received. The frequency is calculated by comparing a difference between the second and the first timer values, and a difference between the second and the first time stamps. | 2013-12-12 |
20130332767 | REDUNDANCY AND LOAD BALANCING IN REMOTE DIRECT MEMORY ACCESS COMMUNICATIONS - A system for managing communications to add a first Remote Direct Memory Access (RDMA) link between a TCP server and a TCP client, where the first RDMA link references first remote memory buffer (RMB) and a second RMB, and further based on a first remote direct memory access network interface card (RNIC) associated with the TCP server and a second RNIC associated with the TCP client. The system determines whether a third RNIC is enabled. The system adds a second RDMA link, responsive to a determination that the third RNIC is enabled. The system detects a failure in a failed RDMA link. The system reconfigures the first RDMA link to carry at least one TCP message of a connection formerly assigned to the failed RDMA link, responsive to detecting the failure. The system communicates at least one message of the at least one connection on the first RDMA link. | 2013-12-12 |
20130332768 | STORAGE SYSTEM, STORAGE CONTROL APPARATUS AND METHOD - A storage system comprises a storage device for storing data, a control apparatus which controls the storage device and comprises multiple communication ports, and a switch apparatus which expands the number of storage device couplings and comprises multiple communication ports. Respective multiple communication ports of the control apparatus are coupled to respective multiple communication ports of the switch apparatus, and the switch apparatus is coupled to the storage device. The control apparatus configures at least one communication port of the multiple communication ports of the control apparatus, to a dedicated communication port for outputting only a prescribed command issued when a failure is detected. | 2013-12-12 |
20130332769 | IN-FIELD BLOCK RETIRING - Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed. | 2013-12-12 |
20130332770 | ACTIVE/PASSIVE DATABASE MANAGEMENT ACROSS CLUSTERS - A primary active manager can manage a first copy of a database in a first computer system cluster according to a set of management rules that provide for an active copy and one or more passive copies of the database at a given time. The primary active manager can also manage a second copy of the database in a second computer system cluster according to the rules. The rules can allow the first copy of the database or the second copy of the database to be the active copy if one or more criterion in the rules is met for that active copy. The first copy can be designated as the active copy and the second copy can be designated as a passive copy. A failure of the first copy can be detected, and in response, the second copy can be automatically designated as the active copy. | 2013-12-12 |
20130332771 | METHODS AND APPARATUS FOR VIRTUAL MACHINE RECOVERY - Methods and apparatus for recovery of virtual machine failure. A succession of data images is captured, with each of the data images comprising an operating system of the virtual machine. The data images are images of data elements chosen based at least in part on their suitability for virtual machine restoration. Upon detection of a virtual machine failure, an attempt is made to restore the virtual machine using the highest ranked. If the attempt fails, further attempts are made using lower ranked data images, until an attempt is successful or all available data images have been used. | 2013-12-12 |
20130332772 | Registration Status Management for Endpoint Devices - A registration status manager may poll a user device, such as a session initiation protocol (SIP) endpoint device, for a registration state value indicative of its registration state. The registration status manager may receive the registration state value and determine that it indicates a registration state error such as an out-of-service no dial tone (NDT) condition. The registration status manager may determine a possible cause for failure associated with the registration state error. Subsequently, the registration status manager may determine a possible solution associated with the possible cause for failure. | 2013-12-12 |
20130332773 | GENERALIZED PATTERN RECOGNITION FOR FAULT DIAGNOSIS IN MACHINE CONDITION MONITORING - A generalized pattern recognition is used to identify faults in machine condition monitoring. Pattern clusters are identified in operating data. A classifier is trained using the pattern clusters in addition to annotated training data. The operating data is also used to cluster the signals in the operating data into signal clusters. Monitored data samples are then classified by evaluating confidence vectors that include substitutions of signals contained in the training data by signals in the same signal clusters as the signals contained in the training data. | 2013-12-12 |
20130332774 | TEST ACCESS SYSTEM, METHOD AND COMPUTER-ACCESSIBLE MEDIUM FOR CHIPS WITH SPARE IDENTICAL CORES - Exemplary system, method and computer-accessible medium for testing a multi-core chip can be provided which can have and/or utilize a plurality of identical cores. This can be performed by comparing each core with as many as at least the number of spare cores plus 1 using a comparator; the number of comparators can equal the total number of cores multiplied by one-half the number of spare cores plus 1. A mismatch between two cores can identify at least one of the two cores as defective and a perfect match between two cores can identify both cores as not defective. The multi-core chip can fail the test if the number of defective cores can be greater than the number of spare cores. | 2013-12-12 |
20130332775 | FAULT TREE ANALYSIS SYSTEM, FAULT TREE ANALYSIS METHOD AND PROGRAMME - The present invention is a fault tree analysis system, comprising: k/n conjunction weeding means for weeding a conjunction including disjoint basic k/n gates and/or disjoint simple k/n gates and removing the conjunction if its order is greater than a given maximal order of minimal cut sets. | 2013-12-12 |
20130332776 | FAULT TREE SYSTEM RELIABILITY ANALYSIS SYSTEM, FAULT TREE SYSTEM RELIABILITY ANALYSIS METHOD, AND PROGRAM THEREFOR - The present invention is a fault tree system reliability analysis system, comprising: k/n gate splitting means for splitting a disjunctive k/n gate with inputs of OR gates into disjoint conjunctive k/m gates (m≦n) without input of OR gate. | 2013-12-12 |
20130332777 | System And Method For Automatic Test Level Generation - A system and method for generating a specific level of software testing of algorithms and applications. A test plan, including input parameter values, expected output parameter values, and dataset size, is entered. The test plan is then executed, and results of the test are scored in accordance with predetermined software testing level definitions, yielding one of a predetermined possible testing levels achieved by the tested software. | 2013-12-12 |
20130332778 | PERFORMANCE-IMBALANCE-MONITORING PROCESSOR FEATURES - The current application is directed to architected hardware support within computer processors for detecting and monitoring various types of potential performance imbalances with respect to simultaneously executing hardware threads in simultaneous multi-threading (“SMT”) processors and SMT-processor cores. The architected hardware support may include various types of performance-imbalance-monitoring registers that accumulate indications of performance imbalances and that can be used, by performance-monitoring software and by human analysts to detect performance-degrading conflicts between simultaneously executing hardware threads. Such conflicts can be ameliorated by changing the scheduling of virtual machines, tasks, and other computational entities, by redesigning and re-implementing all or portions of performance-limited and performance-degrading applications, by altering resource-allocation strategies, and by other means. In addition, performance imbalance detection and monitoring can be used to provide accurate, computational-throughput-based accounting in cloud-computing environments. | 2013-12-12 |
20130332779 | METHOD FOR AUTOMATICALLY MONITORING AT LEAST ONE COMPONENT OF A PHYSICAL SYSTEM - A method for automatic monitoring of at least one component of a physical system, includes checking data of a data record for errors caused by a preceding data processing, checking the data in the physical context of the at least one sensor for errors resulting from infringements of the assumptions of physical and/or system-related factors in elements of the measurement chain, the context of the component for errors resulting from infringements of the physical and/or system-related factors of the component, and—checking the individually asserted errors against one another and then either rejecting the error or outputting the error as an error message with reference to the error source. | 2013-12-12 |
20130332780 | INFORMATION PROCESSING APPARATUS CAPABLE OF APPROPRIATELY PROVIDING NOTIFICATION OF STORAGE UNIT FAILURE PREDICTION, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - An information processing apparatus which is capable of reducing operational costs required for the information processing apparatus equipped with HDDs having a mirroring function and a self-diagnosis function. Status information indicative of statuses of the HDDs is obtained by the self-diagnosis function which the HDDs have. Based on the obtained status information obtained, whether or not the HDDs will fail is predicted. When a failure of the HDDs is predicted, and the mirroring function is disabled, an electronic device determined in advance is notified that replacement of the HDDs is necessary. When a failure of the HDDs is predicted, and the mirroring function is enabled, the electronic device is not notified that replacement of the HDDs is necessary. | 2013-12-12 |
20130332781 | RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS - Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor. | 2013-12-12 |
20130332782 | BACKGROUND BUFFERING OF CONTENT UPDATES - A computer-implemented method, system, and/or computer program product handles content availability error codes. A content refresh response, responsive to a content refresh request that requests content being displayed on a user interface to be updated, is received by and stored in a buffer in a client computer. The content refresh request was generated by a content renderer in the client computer, and the buffer is isolated from the content renderer. The content refresh response is then transmitted from the buffer to a content refresh handler, such that the content refresh handler prevents the content refresh response from being sent directly from the buffer to the content renderer without the content refresh response first being analyzed by the content refresh handler. | 2013-12-12 |
20130332783 | INTEGRITY OF AN ADDRESS BUS - A method for improving address integrity in a memory system generates error correction data corresponding to a memory address. The error correction data is transmitted to a memory device over an address bus coincident with transmitting a no-operation instruction over a command bus. | 2013-12-12 |
20130332784 | APPARATUS AND METHOD FOR TESTING A MEMORY - An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point. | 2013-12-12 |
20130332785 | TESTING OF NON STUCK-AT FAULTS IN MEMORY - A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell. | 2013-12-12 |
20130332786 | Test Data Volume Reduction Based On Test Cube Properties - Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals. | 2013-12-12 |
20130332787 | ALTERNATE SIGNALING MECHANISM USING CLOCK AND DATA - Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state. | 2013-12-12 |
20130332788 | HALF WIDTH COUNTING LEADING ZERO CIRCUIT USING COMPARATORS - A circuit and method are provided for providing a value representing the number of leading zero bits in an input data word. The input data word contains random data. The input data word is logically divided into odd and even bit positions. The circuit includes a first comparator circuit comparing data in the odd bit positions to data in the even bit positions. The circuit further includes a second comparator circuit comparing the data in the odd bit positions to a result of a logical operation performed on the data in the odd and even bit positions. The circuit further includes a half-width leading zero counting circuit that provides the value representing the number of leading zero bits in the input data word. The comparator circuits provide a correction bit value concatenated to the value. | 2013-12-12 |