50th week of 2013 patent applcation highlights part 42 |
Patent application number | Title | Published |
20130330883 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure. | 2013-12-12 |
20130330884 | METHODS FOR PROTECTING ELECTRONIC CIRCUITS OPERATING UNDER HIGH STRESS CONDITIONS - Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device. | 2013-12-12 |
20130330885 | SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS - A method to fabricate a novel graphene based, electrically tunable, nanoconstriction device is described. The device includes a back-gate dielectric layer formed over a conductive substrate. The back-gate dielectric layer is, in one example, hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts are formed over a portion of the graphene layer including at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between the at least one source contact, the at least one the drain contact and the at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer. | 2013-12-12 |
20130330886 | METHOD OF FORMING THIN FILM POLY SILICON LAYER AND METHOD OF FORMING THIN FILM TRANSISTOR - A method of forming a thin film poly silicon layer includes following steps. Firstly, a substrate is provided. A heating treatment is then performed. A thin film poly silicon layer is then directly formed on a first surface of the substrate by a silicon thin film deposition process. A method of forming a thin film transistor includes following steps. Firstly, a substrate is provided. A heating treatment is then performed. A thin film poly silicon layer is then directly formed on a first surface of the substrate by a silicon thin film deposition process. A first patterning process is performed on the thin film poly silicon layer to form a semiconductor pattern. Subsequently, a gate insulation layer, a gate electrode, a source electrode and a drain electrode are formed. | 2013-12-12 |
20130330887 | STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER - A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure. | 2013-12-12 |
20130330888 | IN SITU GROWN GATE DIELECTRIC AND FIELD PLATE DIELECTRIC - Methods and apparatuses are disclosed for providing heterostructure field effect transistors (HFETs) with high-quality gate dielectric and field plate dielectric. The gate dielectric and field plate dielectric are in situ deposited on a semiconductor surface. The location of the gate electrode may be defined by etching a first pattern in the field plate dielectric and using the gate dielectric as an etch-stop. Alternatively, an additional etch-stop layer may be in situ deposited between the gate dielectric and the field plate dielectric. After etching the first pattern, a conductive material may be deposited and patterned to define the gate electrode. Source and drain electrodes that electrically contact the semiconductor surface are formed on opposite sides of the gate electrode. | 2013-12-12 |
20130330889 | METHOD OF MAKING A FINFET DEVICE - The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed. | 2013-12-12 |
20130330890 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE - A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate ( | 2013-12-12 |
20130330891 | DRAM WITH A NANOWIRE ACCESS TRANSISTOR - A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure. | 2013-12-12 |
20130330892 | TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION - A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask. | 2013-12-12 |
20130330893 | INTEGRATING FORMATION OF A REPLACEMENT GATE TRANSISTOR AND A NON-VOLATILE MEMORY CELL USING A HIGH-K DIELECTRIC - A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate. | 2013-12-12 |
20130330894 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness. | 2013-12-12 |
20130330895 | METHOD OF MANUFACTURING THE TRENCH POWER SEMICONDUCTOR STRUCTURE - A method of manufacturing a trench power semiconductor structure is provided. The method comprising the steps of: providing a base, forming a dielectric pattern layer on the base to define an active region and a terminal region, wherein a portion of the base in the active region and the terminal region is covered by the dielectric pattern layer; selectively forming a first epitaxial layer on the base without being covered by the dielectric pattern layer; removing the dielectric pattern layer in the active region to form a gate trench on the base, and forming a gate dielectric layer on the first epitaxial layer and on the inner surface of the gate trench; forming the gate structure in the gate trench; utilizing the dielectric pattern layer to forming a body on or in the first epitaxial layer; and forming a source on the upper portion of the body. | 2013-12-12 |
20130330896 | MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE - A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening. | 2013-12-12 |
20130330897 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 2013-12-12 |
20130330898 | MOS TRANSISTOR PROCESS - A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure. | 2013-12-12 |
20130330899 | PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING - A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer. | 2013-12-12 |
20130330900 | METHODS OF TAILORING WORK FUNCTION OF SEMICONDUCTOR DEVICES WITH HIGH-K/METAL LAYER GATE STRUCTURES BY PERFORMING A FLUORINE IMPLANT PROCESS - One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed. | 2013-12-12 |
20130330901 | PROGRAMMABLE METALLIZATION MEMORY CELL WITH LAYERED SOLID ELECTROLYTE STRUCTURE - Programmable metallization memory cells having an active electrode, an opposing inert electrode and a variable resistive element separating the active electrode from the inert electrode. The variable resistive element includes a plurality of alternating solid electrolyte layers and electrically conductive layers. The electrically conductive layers electrically couple the active electrode to the inert electrode in a programmable metallization memory cell. Methods to form the same are also disclosed. | 2013-12-12 |
20130330902 | ENHANCED NON-NOBLE ELECTRODE LAYERS FOR DRAM CAPACITOR CELL - A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode materials are conductive molybdenum oxide. | 2013-12-12 |
20130330903 | MANUFACTURABLE HIGH-K DRAM MIM CAPACITOR STRUCTURE - A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin (3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material. | 2013-12-12 |
20130330904 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 2013-12-12 |
20130330905 | EDGE CONNECT WAFER LEVEL STACKING - A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package. | 2013-12-12 |
20130330906 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material. | 2013-12-12 |
20130330907 | METHODS OF FORMING SEMICONDUCTOR DEVICES BY FORMING SEMICONDUCTOR CHANNEL REGION MATERIALS PRIOR TO FORMING ISOLATION STRUCTURES - One example of a method disclosed herein for forming a transistor surrounded by an isolation structure includes the steps of, prior to forming the isolation structure, forming a semiconductor material on a region of a semiconducting substrate, after forming the semiconductor material, forming the isolation structure in the substrate around the semiconductor material, and forming a gate structure above the semiconductor material. | 2013-12-12 |
20130330908 | SEMICONDUCTOR COMPONENT WITH VERTICAL STRUCTURES HAVING A HIGH ASPECT RATIO AND METHOD - A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric. | 2013-12-12 |
20130330909 | METHOD FOR CUTTING BRITTLE SHEET-SHAPED STRUCTURE - A method for cutting brittle sheet-shaped structure is disclosed. A brittle sheet-shaped structure having a cutting surface including a first cutting line on the cutting surface of the brittle sheet-shaped structure is formed. The cutting surface is divided into a first section and a second section, wherein the first section has a predetermined shape. At least one second cutting line is formed on the second section along part of the first cutting line or a tangent line of the first cutting line. A number of third cutting lines are formed on the second section by taking the first cutting line as endpoints. A brittle sheet-shaped structure having the predetermined shape is finally obtained by splitting the brittle sheet-shaped structure along the first cutting line, the at least one second cutting line, and the third cutting lines. | 2013-12-12 |
20130330910 | DICING DIE BOND FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a dicing die bond film in which yielding and breaking of the dicing film are prevented and in which the die bond film can be suitably broken with a tensile force. In the dicing die bond film of the present invention, the tensile strength of the contact part in which the outer circumference of the push-up jig contacts the dicing film at 25° C. is 15 N or more and 80 N or less and the yield point elongation is 80% or more, the tensile strength of the wafer bonding part of the dicing film at 25° C. is 10 N or more and 70 N or less and the yield point elongation is 30% or more, [(the tensile strength of the contact part)−(the tensile strength of the wafer bonding part)] is 0 N or more and 60 N or less, and the breaking elongation rate of the die bond film at 25° C. is more than 40% and 500% or less. | 2013-12-12 |
20130330911 | METHOD OF SEMICONDUCTOR FILM STABILIZATION - Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed. | 2013-12-12 |
20130330912 | SILICON OXYCARBIDE, GROWTH METHOD OF SILICON OXYCARBIDE LAYER, SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O | 2013-12-12 |
20130330913 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A structure includes a substrate, a template layer formed on the surface of the substrate and including an AlN layer, and a device structure portion formed by stacking AlGaN semiconductor layers on the template layer. For the structure, the AlN layer is irradiated from a side close to the substrate with a laser light with a wavelength by which the laser light passes through the substrate and the laser light is absorbed by the AlN layer, in a state in which the AlN layer receives compressive stress from the substrate. This allows the AlN layer to expand more than the surface of the substrate on at least an interface between the AlN layer and the substrate so as to increase the compressive stress, in order to remove the substrate from the AlN layer. | 2013-12-12 |
20130330914 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide a thin film transistor having favorable electric characteristics and high reliability and a semiconductor device which includes the thin film transistor as a switching element. An In—Ga—Zn—O-based film having an incubation state that shows an electron diffraction pattern, which is different from a conventionally known amorphous state where a halo shape pattern appears and from a conventionally known crystal state where a spot appears clearly, is formed. The In—Ga—Zn—O-based film having an incubation state is used for a channel formation region of a channel etched thin film transistor. | 2013-12-12 |
20130330915 | METHOD OF MAKING A THIN CRYSTALLINE SEMICONDUCTOR MATERIAL - A method of preparing a thin material layer from a semiconductor substrate is presented. The method entails forming a stress-generating epitaxial layer on a base substrate to form a stressed region, and achieving separation along the stressed region to produce a first part and a second part. The stress-generating epitaxial layer may be boron-doped or a Si | 2013-12-12 |
20130330916 | METHODS OF FORMING HIGH MOBILITY FIN CHANNELS ON THREE DIMENSIONAL SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming high mobility fin channels on three dimensional semiconductor devices, such as, for example, FinFET semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define an original fin structure for the device, and wherein a portion of a mask layer is positioned above the original fin structure, forming a compressively-stressed material in the trenches and adjacent the portion of mask layer, after forming the compressively-stressed material, removing the portion of the mask layer to thereby expose an upper surface of the original fin structure, and forming a final fin structure above the exposed surface of the original fin structure. | 2013-12-12 |
20130330917 | APPARATUS AND PROCESS FOR INTEGRATED GAS BLENDING | 2013-12-12 |
20130330918 | PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS - A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate. | 2013-12-12 |
20130330919 | MANUFACTURING PROCESS OF GATE STACK STRUCTURE WITH ETCH STOP LAYER - A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench. | 2013-12-12 |
20130330920 | METHOD AND APPARATUS FOR SUBSTRATE PRECLEAN WITH HYDROGEN CONTAINING HIGH FREQUENCY RF PLASMA - A high-frequency, hydrogen-based radio-frequency (RF) plasma is used to reduce a metal oxide and other contaminant disposed in an aperture that is formed in an ultra-low k dielectric material. Because the frequency of the plasma is at least about 40 MHz and the primary gas in the plasma is hydrogen, metal oxide can be advantageously removed without damaging the dielectric material. | 2013-12-12 |
20130330921 | Plating Process and Structure - A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. | 2013-12-12 |
20130330922 | Semiconductor Constructions and Assemblies and Electronic Systems - The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies. | 2013-12-12 |
20130330923 | MIDDLE OF LINE STRUCTURES AND METHODS FOR FABRICATION - A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures. | 2013-12-12 |
20130330924 | Gas Cluster Ion Beam Process for Opening Conformal Layer in a High Aspect Ratio Contact Via - A method for opening a conformal layer at the bottom of a contact via on a substrate is described. The method includes providing a substrate having a first layer with a via pattern formed therein and a second layer conformally deposited on the first layer and within the via pattern to establish a contact via pattern characterized by an initial mid-critical dimension (CD). The method further includes etching through the second layer at the bottom of the contact via pattern to extend the contact via pattern through the second layer and form a contact via while retaining at least part of the second layer on the top surface of the first layer, the corner at the entrance to the via pattern, and the sidewalls of the via pattern, wherein the etching is performed by irradiating the substrate with a gas cluster ion beam (GCIB) according to a GCIB etching process. | 2013-12-12 |
20130330925 | METHODS OF TREATING A DEVICE-SUBSTRATE AND SUPPORT-SUBSTRATES USED THEREIN - Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall. | 2013-12-12 |
20130330926 | DEPOSITING TUNGSTEN INTO HIGH ASPECT RATIO FEATURES - Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner. | 2013-12-12 |
20130330927 | CLEANING LIQUID FOR LITHOGRAPHY AND METHOD FOR FORMING WIRING - A cleaning liquid for lithography, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for includes an alkali or an acid, a solvent, and a silicon compound generating a silanol group through hydrolysis. The method forms a metal wiring layer by embedding a metal in an etching space formed in a low dielectric constant layer of a semiconductor multilayer laminate. In this method, the semiconductor multilayer laminate is cleaned using the cleaning liquid for lithography, after formation of the etching space. | 2013-12-12 |
20130330928 | FILM FORMING DEVICE, SUBSTRATE PROCESSING SYSTEM AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A substrate processing system of forming a resist pattern having a molecular resist of a low molecular compound on a substrate includes a film forming device configured to form a resist film on the substrate; an exposure device configured to expose the formed resist film; and a developing device configured to develop the exposed resist film. The film forming device includes a processing chamber configured to accommodate therein the substrate; a holding table that is provided in the processing chamber and configured to hold the substrate thereon; a resist film deposition head configured to supply a vapor of the molecular resist to the substrate held on the holding table; and a depressurizing device configured to depressurize an inside of the processing chamber to a vacuum atmosphere. | 2013-12-12 |
20130330929 | SEAL MEMBER, ETCHING APPARATUS, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a seal member according to embodiments. The seal member is disposed between an upper electrode and a backing plate in an etching apparatus to seal a gap between the upper electrode and the backing plate. In addition, the seal member is configured to include a high heat conductivity member having a heat conductivity higher than that of a first member formed by using siloxane bond and a low resistance member having a resistivity lower than that of the first member. | 2013-12-12 |
20130330930 | SUBSTRATE PROCESSING APPARATUS, METHOD FOR MANUFACTURING SUBSTRATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A substrate processing apparatus includes: a processing chamber that accommodates a substrate; a heating portion that is provided so as to surround a accommodating region of the substrate within the processing chamber; a gas nozzle that is provided inside the heating portion and that supplies a processing gas to the accommodating region of the substrate; and a gas heating mechanism that is provided inside the heating portion and that supplies the processing gas from an upstream side of the gas nozzle into the gas nozzle. A ratio of a flow channel circumferential length to a flow channel cross-sectional area in a gas flow channel of the gas heating mechanism is larger than a ratio of a flow channel circumferential length to a flow channel cross-sectional area in a gas flow channel of the gas nozzle. | 2013-12-12 |
20130330931 | METHOD OF MAKING A SEMICONDUCTOR DEVICE - In one embodiment, a method for forming an electronic device includes providing a substrate having a plurality of electronic devices formed therein, forming a protective layer over a major surface of the substrate containing the plurality of electronic devices, forming a mold layer over the protective layer, thinning a major surface of the substrate opposite to the major surface containing the plurality of electronic devices, and removing the adhesive layer and the mold layer. In another embodiment, a zone coating layer can be included between the protective layer and the mold layer. | 2013-12-12 |
20130330932 | HARDMASK MATERIALS - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si | 2013-12-12 |
20130330933 | Method for Forming Silicon-Containing Dielectric Film by Cyclic Deposition with Side Wall Coverage Control - A method of forming a dielectric film having Si—C bonds and/or Si—N bonds on a semiconductor substrate by cyclic deposition, includes: (i) conducting one or more cycles of cyclic deposition in a reaction space wherein a semiconductor substrate is placed, using a Si-containing precursor and a reactant gas; and (ii) before or after step (i), applying a pulse of RF power to the reaction space while supplying a rare gas and a treatment gas without supplying a Si-containing precursor, whereby a dielectric film having Si—C bonds and/or Si—N bonds is formed on the semiconductor substrate. | 2013-12-12 |
20130330934 | METHOD OF FORMING THIN FILM POLY SILICON LAYER - A method of forming a thin film poly silicon layer includes following steps. Firstly, a substrate is provided. The substrate has a first surface. A heating treatment is then performed. A thin film poly silicon layer is then directly formed on the first surface of the substrate by a silicon thin film deposition process. | 2013-12-12 |
20130330935 | REMOTE PLASMA BASED DEPOSITION OF SiOC CLASS OF FILMS - Provided are methods and systems for providing oxygen doped silicon carbide. A layer of oxygen doped silicon carbide can be provided under process conditions that employ silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the oxygen doped silicon carbide. The one or more radical species can be formed in a remote plasma source. | 2013-12-12 |
20130330936 | METHOD OF DEPOSITION OF Al2O3/SiO2 STACKS, FROM ALUMINIUM AND SILICON PRECURSORS - A method of forming an Al | 2013-12-12 |
20130330937 | Process for Producing Silicon and Oxide Films from Organoaminosilane Precursors - A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: | 2013-12-12 |
20130330938 | ROTATABLE AND TUNABLE HEATERS FOR SEMICONDUCTOR FURNACE - A method for forming a layer of material on a semiconductor wafer using a semiconductor furnace that includes a thermal reaction chamber having a heating system having a plurality of rotatable heaters for providing a heating zone with uniform temperature profile is provided. The method minimizes temperature variations within the thermal reaction chamber and promotes uniform thickness of the film deposited on the wafers. | 2013-12-12 |
20130330939 | LEAKAGE CURRENT DETECTION INTERRUPTER PLUG HAVING DETACHABLE CONNECT TERMINALS - An electric plug includes an end block and a power cord. The end block includes a plurality of first connectors and the power cord includes a plurality of second connectors which correspond to the first connectors and detachably connected thereto. The first connectors and second connectors are electrically conductive. One or more first connectors are connected to the second connectors by press-fitting and are retained therewith by friction. Alternatively, the first connectors may be a terminal screw assembly and the second connectors are wires of the power cord. | 2013-12-12 |
20130330940 | Multi-Level Connector and Use Thereof that Mitigates Data Signaling Reflections - An improved electrical connector for connecting bus lines to a card such as a memory card or media card, including a multi-level connector comprising a latching device having a plurality of insertable latch positions that advantageously allows for selectively connecting or isolating an electrical path to an adjoining connector. The connectors of unpopulated DIMM slots are disconnected from the network along with the traces that would normally form a stub with associated undesirable signal reflections that would otherwise disturb the signal transmitted to the receiving end if not properly terminated. The contacts of the edge connector itself are used as a means to selectively connect or disconnect adjacent/downstream cards in a serially cascaded architecture. The burden of the stubs due to unpopulated card slots and the need to place one card at the far end of the network are thus eliminated. | 2013-12-12 |
20130330941 | CIRCUIT BOARD HAVING PLATED THRU-HOLES AND GROUND COLUMNS - A circuit board including a board substrate having opposite first and second sides. The board substrate has a thickness measured along a z-axis that is perpendicular to the first and second sides. The circuit board also includes plated thru-hole (PTH) vias extending along the z-axis from the first side into the board substrate. The PTH vias are arranged to form multiple signal pairs. The circuit board also includes signal traces that are directly coupled to the PTH vias and extend perpendicular to the z-axis in the board substrate. The signal traces and the PTH vias are configured to transmit differential signals. The circuit board also includes ground columns that extend along the z-axis in the board substrate. The ground columns are distributed relative to the signal pairs to form shield arrays. Each of the shield arrays surrounds one of the signal pairs, wherein the ground columns comprise microvias. | 2013-12-12 |
20130330942 | COMPLIANT CONDUCTIVE NANO-PARTICLE ELECTRICAL INTERCONNECT - An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a resilient substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles. | 2013-12-12 |
20130330943 | BOARD-TO-BOARD CONNECTOR - A board-to-board connector is disclosed. The board-to-board connector comprises a first connector and a second connector. The first connector has first terminals and a first housing which has first fitting guide portions formed at both ends in the longitudinal direction of the first housing. The second connector has second terminals configured to make contact with the first terminals, and a second housing which has second fitting guide portions formed at both ends in the longitudinal direction of the second housing and configured to engage with the first fitting guide portions. | 2013-12-12 |
20130330944 | SPRING-LOADED BLIND-MATE ELECTRICAL INTERCONNECT - An electronic device, configured to be blindly mated with a printed circuit board, comprises a housing and at least one RF interconnect. The RF interconnect comprises an outer conductor, an insulator, and an inner conductor that function in a manner similar to the outer conductor, insulator, and inner conductor of a coaxial cable, respectively. The inner conductor comprises a spring-loaded electrical contact such as a POGO pin. An upper end of the outer conductor is electrically coupled to the housing and a lower end of the outer conductor is configured to electrically couple to a ground return path of the printed circuit board. In its normally extended position, the spring-loaded contact extends beyond the lower end of the outer conductor, and the outer conductor limits the compression distance of the spring-loaded contact. | 2013-12-12 |
20130330945 | ELECTRICAL CONNECTOR ASSEMBLY WITH AN ADAPTOR FOR ELECTRICAL CONNECTING THE ELECTRICAL CONNECTOR AND THE PCB - An electrical connector assembly includes a printed circuit board, an electrical connector assembled on the printed circuit board and an interposer assembled between the electrical connector and the printed circuit board, the electrical connector includes an insulative housing and a plurality of terminals and a shielding element received therein, and wherein the interposer electrically connect the terminals and the shielding element and electrically connect the printed circuit board. | 2013-12-12 |
20130330946 | ROTATING CONNECTOR - A rotating connector includes a cable accommodation chamber formed between an outer case and an inner case in their radial direction, a flexible flat cable housed in the cable accommodation chamber, and multiple idlers housed in the cable accommodation chamber. The idlers are rotatably provided in a direction of an annular slidable member. The idlers are rotatable on their own axes. The flat cable is wound on an inner periphery of the outer case and an outer periphery of the inner case by way of a reversed portion of the flat cable. The flat cable is wound thereon in opposite directions. The idlers are pivotally supported by the slidable member so as to change a space between the idlers and the inner case and a space between the idlers and the outer case depending on winding of the flat cable. | 2013-12-12 |
20130330947 | HOMEPLUG WITH CHANGEABLE TOP CASE STRUCTURE - A HomePlug with a changeable top case structure includes a casing and a socket assembly. The casing has a first coupling portion therein and has an opening. The socket assembly has a second coupling portion for coupling with the first coupling portion, such that the socket assembly corresponds in position to the opening and thereby is coupled to the casing from inside and exposed from the opening. The HomePlug with a changeable top case structure is effective in dispensing with redesign and the manufacturing of a casing in its entirety, cutting die and material costs, enhancing ease of product design, and increasing assembly universality. | 2013-12-12 |
20130330948 | FEMALE FUSE TERMINAL AND PRINTED CIRCUIT BOARD ASSEMBLY THEREFOR - A female fuse terminal is provided with a longitudinally extending blade portion sized to be received within a socket. An intermediate portion extends from the blade portion and extends at an acute angle from a longitudinal direction of the blade portion. A female portion is sized to receive a fuse blade, and extends from the intermediate portion such that the female portion is offset parallel to the blade portion. A printed circuit board assembly is provided with a (PCB) having a socket sized to receive the terminal. | 2013-12-12 |
20130330949 | FUSE HOUSING ASSEMBLY - A fuse housing assembly is provided with a housing having a base adapted to be mounted to a printed circuit board (PCB) at least partially over a through aperture. The housing has at least one receptacle sized to receive a case-type fuse. The housing has an aperture in the base aligned with the at least one receptacle for receipt of a terminal blade from the PCB for electrical communication with the case-type fuse. At least one connector blade is mounted to the housing and extends into the at least one receptacle and extends through the base to extend through the PCB through aperture for electrical communication with the case-type fuse and the connector. | 2013-12-12 |
20130330950 | ELECTRICAL CONNECTION SYSTEM THAT INCLUDES AN INTEGRALLY FORMED RETAINING MEANS TO SECURE A SEALING MEMBER DISPOSED THEREIN - An electrical connection system includes a first connector housing including electrical contacts and a second connector housing including corresponding electrical mating contacts. The first connector housing and electrical contacts are configured to mate with the second connector housing and the electrical mating contacts along a mating axis. At least one of the first and second connector housings includes a sealing member that surrounds the electrical contact associated with the at least one of the first and second connector housings and further contains a retaining means to retain the sealing member therein. The retaining means is integrally formed with the connector housing. A method to construct the electrical connection system that includes the sealing member and the integral retaining means is also presented. | 2013-12-12 |
20130330951 | CONNECTOR OF ELECTRONIC DEVICE, PLUG OF ELECTRONIC DEVICE, AND WATERPROOF STRUCTURE OF ELECTRONIC DEVICE - Provided is a connector of an electronic device, in which a space in a housing of the electronic device can be enlarged, the number of circuits can be increased, a battery can be made larger, and the housing of the electronic device can be made thinner and more compact. The connector of the electronic device is provided with a substantially cylindrical case; connector-side terminals introduced into the case; and a sealing material that is formed in the vicinity of the end of the case on a plug insertion side so as to protrude to the plug insertion side, wherein a first convex stripe is formed along the inner circumference of the protruding section of the sealing material, and the first convex stripe is formed so as to be circumferentially pressed against and brought into contact with an outer circumferential surface of a part of a cover to be inserted. | 2013-12-12 |
20130330952 | CONNECTOR WITH SMALL HOUSING - A connector is provided with a terminal fitting, a housing, a rear holder, a rubber closures, and a spacers. The spacer is provided with a main body shaped cutaway-circular in cross-section, positioning the electric wire connection part and an electric wire | 2013-12-12 |
20130330953 | STRUCTURE FOR REMOVABLE PROCESSOR SOCKET - A socket has top side pins that may form electrical connections to a central processing unit chip, and a bottom side ball grid array of discrete, electrically-conductive metal surfaces. Differently-keyed setoff apertures are formed through the socket that when disposed about corresponding standoffs projecting upward from a planar circuit board align the socket ball grid array surfaces with grid array pad connections on the circuit board. Retaining screws passing through the socket setoff apertures, when tightened into the planar board standoffs, bring a heat-sink downward with compressive force against the socket top side. The socket responsively brings the ball grid array into compressive electrical contact connections with the grid array pad connections on the circuit board, and also compresses against the planar board. The resilient ring may thereby form a seal about the compressively-connected ball grid array and circuit board pads. | 2013-12-12 |
20130330954 | RELEASE DEVICE AND RELEASE SYSTEM AND OUTDOOR UNIT THEREOF - A release device for detaching a male plug of a cable line from a female receptacle includes a holding portion, an accommodating portion, a connecting portion and an engaging portion. The accommodating portion includes a first guiding part that is configured for alignment between the accommodating portion and the male plug. The holding portion connects to the connecting portion that connects to the accommodating portion. The accommodating portion connects to the engaging portion, which includes a concave area that is configured for engaging the male plug. | 2013-12-12 |
20130330955 | ELECTRICAL CONNECTOR ASSEMBLY - An electrical connector assembly includes a female part ( | 2013-12-12 |
20130330956 | Joint Connector - A joint connector includes a plurality of female terminal fittings, a joint terminal that includes a plurality of tab pieces to which the female terminal fittings are fitted and connected and a connecting portion which conductively connects the tab pieces to each other, and a resin connector housing that includes one end which accommodates and holds the joint terminal in a state where the tab pieces face the other end of the housing, the other end in which female terminal accommodating holes are arranged to cause the female terminal fittings and the tab pieces to be engaged with each other by inserting the female terminal fittings to a specified position, and lances that include elastic pieces extending along the female terminal accommodating holes and protrusions which are protruded on a free end side of the elastic pieces toward the female terminal accommodating holes. | 2013-12-12 |
20130330957 | CONNECTOR ASSEMBLY HAVING A SLIDABLE CONNECTOR - A connector assembly including an outer housing having a front end, a back end, and a central axis extending therebetween. The outer housing has a passage that extends therethrough. The connector assembly also includes a slidable connector that is disposed within the passage. The slidable connector includes a communication module. The connector assembly also includes a spring frame that is positioned between the slidable connector and the outer housing. Prior to mating with a mating connector, the spring frame mechanically couples the slidable connector with respect to the outer housing. After the mating connector and the communication module are communicatively coupled, the spring frame releases the slidable connector from the outer housing such that the slidable connector is permitted to move relative to the outer housing. The spring frame mechanically couples the slidable connector relative to the mating connector. | 2013-12-12 |
20130330958 | PLUG WIRE TYPE LAMPHOLDER - A plug-wire type lampholder comprises an acting body having a set of slots formed in the acting body and provided for installing a wire clamping plate separately, and the wire clamping plate has at least one end bent to form two into movable plates, and each slot has two notches and different notches are separated with an interval apart, so that when the wire clamping plate is installed into the slot, the movable plates remain in different corresponding notches respectively, and in different notches the same slot are provided for plugging bare ends of different electric wires respectively to achieve an electric conduction, so as to facilitate connecting lamps of different plug-wire type lampholders into a lamp string quickly. | 2013-12-12 |
20130330959 | ELECTRICAL CONNECTION SYSTEM INCLUDING MATING ASSIST LEVER THAT CONTAINS LOCKING MEANS AND CPA MEMBER THAT INTERACTS THEREWITH - An electrical connection system and method includes a first connector housing matable to a second connector housing along a mating axis. The first connector housing contains a mating assist lever (MAL) that rotationally pivots between an INOPERATIVE position and a CLOSED position and includes a locking means. When the MAL is positionally rotatable to the CLOSED position the first connector housing and the second connector housing are mated together such that the locking means is disposed adjacent an external surface of the second connector housing. A sufficiently applied force against the locking means actuates the locking means so that the locking means latchingly secures the first connector housing to the second connector housing. A CPA member, also disposed on the MAL, slidingly communicates with the latched locking means transverse to the mating axis and ensures the latched locking means does not become unlatched so that electrical connection system remains mated. | 2013-12-12 |
20130330960 | INTERCONNECT DEVICE - An interconnect device includes a contact assembly having a carrier holding an array of conductors. Each of the conductors have opposite first and second ends configured to engage corresponding first and second electrical components. The conductors define conductive paths between the first and second ends to electrically interconnect the first and second electrical components. The interconnect device includes a frame defining a receiving space configured to receive the first electrical component therein. The frame includes corner frames having metal spring fingers configured to engage different side edges of the first electrical component to locate the first electrical component in the receiving space. The spring fingers are deflectable and are configured to be spring biased against corresponding side edges of the first electrical component. | 2013-12-12 |
20130330961 | HOMEPLUG HAVING PANEL REPLACEMENT STRUCTURE - A HomePlug having a panel replacement structure includes a HomePlug body and a panel. The HomePlug body has an operation side and a network port. The operation side has an insertion portion and a first coupling portion. The panel has an opening and second coupling portion. The second coupling portion can be coupled to the first coupling portion so as to allow the opening to correspond in position to the insertion portion. Changes in the appearance of the HomePlug are brought about by panel replacement. A heat dissipation vent is disposed at the junction of the operation side and an adjacent side, such that heat dissipation takes place at the adjacent side-neighboring portion of the heat dissipation vent when the panel is coupled to the operation side and covers the operation side. | 2013-12-12 |
20130330962 | AUDIO JACK HAVING DUAL MECHANICAL DETECTION SWITCHES - Circuits, methods, and apparatus that may provide for reliable detection of electrical and optical audio plugs. One example may detect an optical audio plug by employing one or more mechanical detect switches. These switches may include a first contacting portion and a second contacting portion that are separated from each other when an audio plug is inserted into the audio jack. The second contacting portion may include one or more arms to contact a surface portion of the first contacting portion. The first contacting portion and the second contacting portion may be biased such that they tend to stay in contact with each other as the first contacting portion begins to be deflected by the insertion of an audio plug, thereby wiping dust or debris from between the first contacting portion and the second contacting portion. | 2013-12-12 |
20130330963 | FLAT CIRCUIT CONNECTOR - A flat circuit connector includes a first connector which is resin molded at an end part of a flat circuit body and a second connector including a terminal. The first connector includes a block part made of resin and a flange part. The flange part is integrally formed at a rear side in a direction in which the block part is fitted. A projecting wall is provided on a surface of the flange part which is parallel to a main surface of the flat circuit body. The second connector includes a first peripheral wall with which the block part is fitted, and a second peripheral wall which is integrally formed at the rear side of the first peripheral wall. The second peripheral wall is formed with a cut part in which the projecting wall is fitted. | 2013-12-12 |
20130330964 | CONNECTOR CABLE STOWAGE SYSTEM FOR HANDHELD AND MOBILE COMPUTING DEVICE ACCESSORIES - A connector cable stowage system for an accessory device for a handheld computing device is disclosed. The accessory device has a housing. The stowage system includes a connector cable that has a head with a connector and a cable. The connector is adapted for electrical connection to a handheld computing device. The cable is electrically connected to an accessory device. A head receptacle is molded in the housing of the accessory device. The head receptacle is configured to receive the head of the connector cable therein. | 2013-12-12 |
20130330965 | Electrical Outlet Sealing System - A system for sealing a building electrical outlet of the type mounted within a wall surface of the building having one or more electrical plug sockets adapted to receive an electrical plug and a cover plate. The system includes two primary components. A gasket formed of an elastomeric material is provided with a pair of electrical terminal slots. A plug cover element forms a front cover panel and includes a pair of tabs extending from a back of the face surface to engage the electrical plug socket terminal slots. Two modes of operation are available. When an electrical plug is inserted into the electrical plug socket, the gasket is positioned between the plug and the socket to seal against air infiltration. When an electrical plug is not inserted into the socket, the plug cover is used to maintain the gasket in position for sealing against the electrical plug socket. | 2013-12-12 |
20130330966 | CONNECTION PIN FOR MOUNTING IN A COMPONENT CARRIER, A METHOD FOR PRODUCING AN ELECTRONIC ASSEMBLY COMPRISING A MOTHERBOARD WITH STACKABLE MODULES COMPRISING A COMPONENT CARRIER, AND SUCH AN ELECTRONIC ASSEMBLY - A connection pin for mounting in a through-hole provided in a component carrier of an electronic assembly, the connection pin comprising an anchoring part adapted for insertion into said through-hole, a contact part adapted to extend outside said through-hole, and a flange part adapted to abut against said component carrier and located between said anchoring part and said contact part. The connection pin is provided with an internal cavity, which is provided with an outer opening at a free end of the anchoring part. The contact part is provided with a protruding elongated interconnection member at a free end thereof, and the respective shapes of the interconnection member and the internal cavity are such that the interconnection member is adapted for insertion into a corresponding internal cavity of another similar connection pin. A method for producing an electronic assembly with stackable modules is also disclosed. | 2013-12-12 |
20130330967 | Coaxial Cable Connector with Alignment and Compression Features - A coaxial cable connector for coupling a coaxial cable to an electrical device includes a body, a threaded fitting, and an alignment mechanism carried and compressed between the body and the fitting so as to exert an axial force against the fitting to maintain electrical contact between the fitting and the body. The body of the connector includes an outer barrel formed with an inner compression band, and a compression collar carried on the outer barrel and formed with an inner compression band. In response to compression of the connector by a compression tool, the inner and outer compression bands deform and move from an uncompressed condition to a compressed condition crimped onto the coaxial cable so as to securely apply the connector to the coaxial cable. | 2013-12-12 |
20130330968 | CONNECTION TERMINAL, COAXIAL ELECTRICAL CONNECTOR AND WIRING STRUCTURE THEREOF - Disclosed is a connection terminal, a coaxial electrical connector and a wiring structure thereof which could ensure the reliability of the electrical connection between the connection terminal and a coaxial cable core. The connection terminal includes a terminal body, two contact resilient pieces formed by bending and extending from two sides of the terminal body, and a core connection resilient arm extending from a rear end of the terminal body in a direction remote from the contact resilient pieces. The cross-section of the core connection resilient arm is essentially “Z” shaped, and a contact surface for contacting the coaxial cable core is formed on the core connection resilient arm. The contact surface has an arcuate protrusion protruding in a direction remote from the contact resilient pieces. The coaxial electrical connector and the wiring structure thereof all include the above connection terminal. | 2013-12-12 |
20130330969 | SOCKET WITH INSERT-MOLDED TERMINAL - A socket includes a housing that supports terminal bricks that can contain one or more terminals. The terminal bricks are inserted into apertures in the housing. The location of the terminal bricks can be adjusted separate from a side of the housing, thus providing the potential to improve coplanarity of the terminals in the socket. | 2013-12-12 |
20130330970 | BOARD-TO-BOARD CONNECTOR - A board-to-board connector comprising a first connector having a first terminal and a first housing that includes a first fitting guide part formed on both ends in the long side direction, and a second connector having a second terminal that contacts to the first terminal and a second housing that includes a second fitting guide part that fits with the first fitting guide part, includes a switch that closes a detection circuit that electrically detects a complete fit of the first connector and the second connector. | 2013-12-12 |
20130330971 | CONNECTOR - A connector capable of realizing a narrower pitch of contact members, and suppressing displacement of the contact members. A connector comprises a frame and a plurality of contact members held by the frame. The contact members held by the frame are elastically deformed by being sandwiched between an IC package and a printed board. At this time, terminal portions of the IC package and terminal portions of the printed board are electrically connected via a plurality of conductive path portions of each contact member. The frame is formed by a frame portion, a plurality of longitudinal ribs extending in a manner bridging the frame portion, and a plurality of transverse ribs extending orthogonal to the longitudinal ribs in a manner bridging the frame portion. The contact members are held in slits formed by the longitudinal ribs and the transverse ribs. | 2013-12-12 |
20130330972 | CONNECTOR AND FORMING METHOD THEREOF - A connector comprises a first contact, a housing and an arrangement member other than the housing. The first contact has a contact portion and a terminal portion. The housing holds the contact portion of the first contact so that the contact portion extends along a first direction. The housing is provided with an engaged portion. The arrangement member holds the terminal portion of the first contact so that the terminal portion extends along a second direction intersecting the first direction. The arrangement member is provided with an engaging portion. The engaging portion engages the engaged portion in a direction intersecting the second direction so that the arrangement member is held by the housing and the terminal portion of the first contact is bent to extend along the second direction. | 2013-12-12 |
20130330973 | CONNECTOR - A connector allows a sheet-like or plate-like object to be inserted thereinto. The object is, for example, an FPC or an FFC. The connector comprises a signal contact and a holding member. The signal contact and the holding member have the same shape as each other. Each of the signal contact and the holding member has a contact portion and a lock portion. Each of the contact portions has a non-angular shape which is suitable for a contact with the object. Each of the lock portions has an angular shape which is suitable for holding the object. | 2013-12-12 |
20130330974 | HOMEPLUG - A HomePlug includes a body, a power socket, and a network port. The body has an installation region, an insertion region, and an operation region defined on a side surface of the body. The power socket is disposed on the insertion region and has a central point. The network port is disposed on the operation region and spaced apart from the central point by a specific distance. Accordingly, not only is the HomePlug convenient to manipulate, but a network cable connected to the HomePlug is also unlikely to bend, even though the HomePlug is installed at an electric outlet positioned proximate to the ground. | 2013-12-12 |
20130330975 | CABLELESS BATTERY INTEGRATION - An interposer for electrically coupling a battery-management circuit board in a power supply and a motherboard is described. The interposer includes: a substrate having a top surface and a bottom surface; first spring connectors, disposed on the top surface, which electrically couple to the battery-management circuit board; and second spring connectors, disposed on the bottom surface and electrically coupled to the first spring connectors, which electrically couple to the motherboard. Spring connectors in a first subset of the first and second spring connectors that convey power signals have a first vertical height, and spring connectors in a second subset of the first and second spring connectors that convey monitoring signals for the power supply have a second, smaller vertical height. In this way, the first subset is activated before the second subset is activated, thereby ensuring that an electrical path for the power signals is established first. | 2013-12-12 |
20130330976 | DUAL CONNECTOR HAVING GROUND PLANES IN TONGUES - Connector receptacle assemblies that may be simple to manufacture, provide multiple receptacles, and provide a good ground contact path. One example may provide a connector receptacle assembly formed of a housing having a tongue that may include openings on one or more sides for contacts as well as openings on its sides for ground contacts. Another example may provide a connector receptacle assembly having at least two tongues, where each tongue may be aligned with a corresponding opening in a device enclosure. Another example may provide a connector receptacle assembly having a tongue with a center ground contact, where the center ground contact may be located between the top row and the bottom row of contacts. Another example may provide a connector receptacle assembly having a titanium-copper center ground contact. | 2013-12-12 |
20130330977 | LOW PROFILE HARD-DISK DRIVE CONNECTOR - Connector receptacles for hard-disk drives that do not consume a significant amount of space. One connector receptacle may include a housing having one or more horizontal slots corresponding to one or more tongues of a connector insert. The connector receptacle may include a number of vertical slots, each having a contact to form an electrical connection with a contact on the one or more tongues. These contacts may emerge from the top of the housing to connect to a flexible conductor. A stiffening layer may be placed over the top of the flexible conductor. The housing may also include vertical bridging pieces that may be located between a top portion and a bottom portion of the connector receptacle. Shielding may be included above, in front of, or below the housing, or any combination thereof. | 2013-12-12 |
20130330978 | AUDIO JACK FOR PORTABLE COMPUTING DEVICE - The present application describes various embodiments regarding an apparatus and method for providing an audio jack for a portable computing device. More specifically a method and apparatus are disclosed for mounting the audio jack to machined audio jack mounts extending from an interior sidewall of the portable computing device housing. The machined mounts allow the audio jack to be suspended above an inner surface of the portable computing device so that the audio jack does not interfere with audio output or aesthetics of a speaker grill drilled into the portable computing device housing. | 2013-12-12 |
20130330979 | CONNECTOR FOR A COVERING MEMBER OF A CABLE - A connector for a covering member of a cable contains a connector; the covering member, including an outer tube having a first hole, the first hole having an external portion extending outward from a peripheral side of another end thereof, the outer tube being retained in the connector, a bottom end of the external periphery being larger than the first hole; an inner tube having a second hole; a needle portion having a head projection and an engaging section; wherein after the needle projection retains in the second hole of the inner tube, the needle portion and the inner tube are received in the first hole of the outer tube so as to retain in the connector with the outer tube. | 2013-12-12 |
20130330980 | STRUCTURE OF SECURITY AND PROTECTION FOR CONNECTION SOCKET - A structure of security and protection for connection socket includes a connection socket, a connection block, a resilient member, and a security member. The connection socket forms a receiving space and a slide channel. The slide channel is located at one side of the receiving space. The connection block is coupled to a rear end of the connection socket and forms a positioning section. The resilient member includes at least one resilient engagement section and is arranged in the positioning section of the connection block. The security member has an end forming a bar section that forms at a rear side thereof a barb section. The barb section is coupled to the at least one resilient engagement section of the resilient member. The bar section has two ends extending rearward to connect to a plate section. The security member is received in the slide channel of the connection socket. | 2013-12-12 |
20130330981 | HIGH-CURRENT INSERTION-TYPE CONNECTOR HAVING ANNULAR RESILIENT CONTACT - A high current connector for transmitting electric currents, having a housing made of electrically conductive material for mechanical and electrical connection to a cable, an open side for the insertion of a matching plug connector made of an electrically conductive material, and a contact element disposed and formed in the housing such that it produces an electrical contact with a contact surface and contact pressure between the housing and the matching plug connector inserted therein, wherein the contact element has at least one annular helical spring. | 2013-12-12 |
20130330982 | ELECTRICAL JUNCTION BOX CONNECTIONS - A junction box assembly is provided with a conductive boss having a first contact surface and a second contact surface spaced apart from the first contact surface. A pair of threaded conductive studs each extends from one of the contact surfaces. A housing is overmolded onto the boss so that the first contact surface, the second contact surface, and the pair of studs are exposed. A printed circuit board (PCB) is oriented in the housing. A busbar is oriented in the housing in electrical communication with the PCB. The busbar has a conductive tab with an aperture formed therethrough. One of the pair of studs is received within the aperture and the contact tab is in electrical communication with one of the first contact surface and the second contact surface. | 2013-12-12 |