50th week of 2009 patent applcation highlights part 30 |
Patent application number | Title | Published |
20090303714 | ADJUSTABLE LIGHT - An adjustable illumination apparatus includes an illumination source having a housing carrying an illuminatable element. A mount is adapted to surround an imaging system lens. An extensible and retractable support has first and second ends mounts the illumination source to the mount. First and second connections movably couple the first and second ends of the support to the mount and the illumination source. The support includes one or more telescoping legs or a cross link bar assembly. In one aspect, the apparatus includes multiple illumination sources. The connections allow each illumination source to be independently positioned relative to other illumination sources. The illuminatable elements in each illumination source may be independently controlled. | 2009-12-10 |
20090303715 | LIGHT SOURCE MODULE HAVING A PLURALITY OF LIGHT-EMITTING ELEMENTS AND ILLUMINATION APPARATUS - A light source module has a reflector having a light reflection face and a plurality of light emitting elements. The light reflection face is curved in a circular arc shape in a width direction of the reflector and extends in a longitudinal direction of the reflector. The light emitting elements are arranged in a center portion in the width direction of the light reflection face and are arranged linearly along the longitudinal direction of the reflector. | 2009-12-10 |
20090303716 | LIGHT ASSEMBLY - A light assembly is disclosed which can include an LED array and a reflector. The LED array can include a plurality of LEDs which are disposed such that each LED is substantially aligned to define a focal axis. Each LED can emit light substantially along an optical output axis, with each optical output axis being perpendicular to the focal axis. The optical output axis of the LED array can be disposed in intersecting relationship with the reflector surface. The reflector can be defined by a curve section defined with respect to a principal axis. The principal axis and the output axis of the LED array can be in non-parallel relationship with each other. The optical output axis of the LED array can be substantially perpendicular to the principal axis of the curve section of the reflector. | 2009-12-10 |
20090303717 | LED LAMP ASSEMBLY - An LED lamp assembly includes a first heat sink, a plurality of second heat sinks secured to a periphery of the first heat sink, a plurality of LED modules respectively attached to the second heat sinks and a plurality of heat pipes interconnecting the first heat sink and the second heat sinks. The first heat sink comprises a heat conducting body defining a through hole therein and a plurality of first fins around the heat conducting body. The second heat sinks each comprise a plurality of second fins facing the first fins of the first heat sink. The heat pipes each comprise an evaporating section attached to a corresponding second heat sink and a condensing section extending into the through hole of the heat conducting body of the first heat sink and attached to the heat conducting body. | 2009-12-10 |
20090303718 | LED LAMP - An LED lamp includes a lamp cover consisting of a plurality of sector-shaped connecting bodies, a plurality of fins attached to the lamp cover and a plurality of LED modules attached to the lamp cover and opposing the fins. A locking device is pivotably mounted to the lamp cover and comprises a supporting pole extending in the lamp cover, a plurality of branches pivotably mounted to the lamp cover and the supporting pole. The branches are movable along the supporting pole to be locked at a desired position, whereby an illumination angle of the LED modules of the lamp cover relative to the supporting pole is changeable via movement of the branches along the supporting pole of the locking device. Thus, an illumination area and an illumination intensity of the LED lamp are adjustable. | 2009-12-10 |
20090303719 | LIGHTING DEVICE - A lighting device is provided. The lighting device has a cooling lampstand made out of one piece by a resin composition. The circuit and at least one light emitting diode (LED) are directly disposed on the cooling lampstand. | 2009-12-10 |
20090303720 | LED Lighting Device - An arrangement of a multiplicity of LEDs, drive circuitry, and supporting structure to form a replacement for standard fluorescent tubes without the need to rewire or remove the magnetic or electronic ballasts in use in standard fluorescent fixtures. | 2009-12-10 |
20090303721 | Matrix LED street light gain structure - A matrix LED street light gain structure, and more particularly, a matrix LED street light that serves the purposes of dissipating heat, saving energy, and increasing illumination area is provided. The matrix LED street light gain structure includes a metal lamp base. The metal lamp base includes a plurality of screw holes formed on an oblique surface of the metal lamp base and each adapted to be screwingly engaged with a matrix LED light strip. The oblique surface of the metal lamp base is a single oblique surface or a plurality of oblique surfaces for extending the reach of illumination of the matrix LED light strip. The metal lamp base further includes a plurality of spaced-apart heat-dissipating fins protrudingly formed on a rear surface of the metal lamp base. | 2009-12-10 |
20090303722 | FLUORESCENT LIGHT FIXTURE WITH LAMP CATCHER - A fluorescent lamp tube catcher formed of bent wire can be detachably engaged with a light fixture, with the central portion of the lamp tube catcher positioned below fluorescent tubes in the light fixture during use. In the event that a fluorescent lamp tube inadvertently becomes loose in the light fixture, the fluorescent lamp tube catcher can stop the loose fluorescent lamp tube from falling. The fluorescent lamp tube catcher can be loosely retained on the light fixture, for example while replacing a fluorescent lamp tube that has failed. | 2009-12-10 |
20090303723 | STAGE PROJECTOR - A stage projector extends along a first axis and is provided with a first optical system having a first focus and designed substantially to generate and concentrate a light beam in the first focus, and a second optical system set downstream of the first focus and having a second focus, the second optical system having a first optical assembly, set in a given position along the first axis so that the second focus coincides with the first focus, and a second optical assembly, selectively mobile between an operative position, in which the second optical assembly intercepts the light beam between the first focus and the first optical assembly, and a position of rest, in which the second optical assembly does not intercept the light beam, the first and the second optical assemblies being mobile along the first axis in order to modify the form of the light beam and obtain a homogeneous distribution of the light within the light beam, when the second optical assembly is set in the operative position. | 2009-12-10 |
20090303724 | LIGHT SOURCE MODULE FOR A LIGHT FIXTURE - A method for generating an air stream for cooling a light source, and a light source module for a light fixture with a blower for cooling the light source and the light source base. To achieve highly effective cooling of a lamp in a light fixture or a projector at least one forced air stream is generated by a blower system which blower system can be placed at a distance from the light source module and can be connected from the blower through a tube to a duct which directs an air stream towards the light source. By using a tube for the connection between the blowing unit and the actual place where air stream is to be used for cooling, it is possible to operate the blower in a place where the suction inlet for air into the blowing unit is a relatively cool place. | 2009-12-10 |
20090303725 | LED heat sink - An LED heat sink having an LED unit and a pipe. The LED unit has a base having a top and an LED chip attached to the top of the base. The pipe has a inlet end, a outlet end, a body, multiple inlets, multiple partitioning walls and multiple partitions. The inlet end is attached to the base of the LED unit. The inlets are defined near the base. The partitioning walls are formed inside the body. The partitions are defined within the body by the partitioning walls and communicate with the inlet end. | 2009-12-10 |
20090303726 | LED LENS MOUNTING DEVICE - A headlight for a vehicle has a lens, a mounting frame, an LED on an LED board. The LED board is mounted on a heat sink. The heat sink has a first adjustment slot and a second adjustment slot. Each of the slots is dimensioned and disposed to closely cooperate with an eccenter adjustment device mounted on one of the LED module or an LED module carrier, said eccenters being adjustable on a fulcrum such that adjustment of one of the eccenters adjusts one of a first position or a second position of the LED module within a plane normal to an optical axis of a lens mounted in a fixed position relative to the LED module carrier. | 2009-12-10 |
20090303727 | Versatile safety reflectors - A Safety reflector suitable as a road stud or hazard reflecting ornament able to utilize ambient light without solar panels batteries or diodes, in order to reflect light multi-dimensionally | 2009-12-10 |
20090303728 | LIGHT EMITTING DEVICE - A light emitting device comprises a light emitting element disposed within a space surrounded by a reflective surface of a reflector disposed on a board. A lower portion of the reflector is placed within a recess formed in the board, and a side wall of the recess is interposed between the lower end of the reflective surface of the reflector and the light emitting element. | 2009-12-10 |
20090303729 | Light Emitting Diode Lamp-Set - A light emitting diode lamp-set includes a shell, at least one module block, a light source device and a lamp shade. An interior of the lamp shell is defined into a holding space, the holding space is installed with the module blocks (such as circular, elliptical or polygonal blocks), the module blocks are assembled into surfaces of different angles from various configurations, and the surfaces assembled by the module blocks are adhered with at least one light source device (such as LED lamps). As the LED lamps emit straight light, the LED lamps on the module blocks can project the light in a wide angle by changing different surfaces. Thus, an assembly mode of the module blocks is changed freely according to environment or a purpose of utilization, to increase or decrease a projection surface of different angle, which provides a user with a more diversified way of utilization. | 2009-12-10 |
20090303730 | Light Fixture Having A Glare-Eliminating Optical System - An undercabinet light fixture, comprising a housing for supporting a light source. A glare-eliminating optical system is mounted on the housing and through which light illuminated by the light source passes. The glare-eliminating optical system includes a textured surface and a non-textured surface. The textured surface includes an array of longitudinally extending prismatic elements for redirecting light illuminated from the light source. The non-textured surface is located below the light source and permits light illuminated from the light source to pass therethrough without being substantially redirected. | 2009-12-10 |
20090303731 | Light-Transmittable Cover For a Light-Emitting Diode Bulb - A light-transmittable cover for a light-emitting diode bulb is provided on a bulb adaptor having at least one light-emitting diode and covers the light-emitting diode. The light-transmittable cover comprises a reflective layer on an outside surface of a top thereof to reflect the light emitted from the light-emitting diode to an area where the light-emitting diode cannot reach. | 2009-12-10 |
20090303732 | ROD-SHAPED LIGHT GUIDE AND IMAGE READING DEVICE - A rod-shaped light guide includes an end face to which light is incident, a bottom plane on which a scattering pattern to scatter light incident to the end face is formed, and a light emitting portion located to be opposite to the bottom plane and emitting light outside. The light emitting portion is formed as a first plane and a second plane connected to each other. The first plane is formed to be smaller than the second plane so that the cross section thereof perpendicular to the longitudinal direction is asymmetrical. | 2009-12-10 |
20090303733 | COLLAPSIBLE LAMPSHADE - A collapsible lampshade includes: an upper frame defining an axis, and formed with a plurality of angularly spaced-apart connecting grooves, each of the connecting grooves extending in a radial direction with respect to the axis; a lower frame surrounding the axis; a plurality of support rods each having a first end pivotally connected to the lower frame, and a second end opposite to the first end, the second end being received releasably in and being slidable along a respective one of the connecting grooves; and a foldable cover connected to and extending between the upper frame and the lower frame. | 2009-12-10 |
20090303734 | Structure in the outer enveloping shells of Christmas lamps - The present invention is to provide a structure improvement in the outer enveloping shells of Christmas lamps, which is characterized in that the outer enveloping shell is co-assembled by sleeved objects with different colors or different shell veins and formed an integrated outer shell. After being inserted, assembled and clip-fit in the lamp stand set with a LED lamp, it is then assembled and connected with an integrating stand set with the power line to form a complete Christmas lamp efficiently and practically. | 2009-12-10 |
20090303735 | Light emitting diode lamp with high heat-dissipation capacity - This invention relates to a light emitting diode lamp with high heat-dissipation capacity wherein the lamp has at -least one heat-dissipating unit, a plurality of air-flow channels being provided within each heat sink unit, an electrical insulation layer with high heat-conductivity being provided on the surface of the light emitting diode mounted with heat-dissipating unit, a metal circuit being formed on the electrical insulation layer with high heat-conductivity according to demand, at least one light emitting diode being packaged on the metal circuit such that provision of circuit board or coating of heat sink paste become unnecessary for the lamp. | 2009-12-10 |
20090303736 | Heat-dissipation gain structure of matrix LED light - A heat-dissipation gain structure of a matrix LED light includes a metal heat-dissipation unit coupled to a matrix LED light chip, and a metal seat housing, so as to provide rapid heat dissipation and thereby maintain a low temperature. The metal seat housing has a plurality of vent holes for air to pass through and circulate between the metal seat housing, the matrix LED light chip and the metal heat-dissipation unit. Thus, the metal heat-dissipation unit can absorb and rapidly dissipate heat generated by the matrix LED light chip, allowing the matrix LED light chip to remain at a low temperature, preventing the matrix LED light chip from premature aging, and thereby increasing its service life. | 2009-12-10 |
20090303737 | LAMP WITH A BOX-LIKE LAMP HOUSING ELEMENT AND A LIGHT OUTLET ELEMENT - A luminaire having a box-like luminaire housing for receiving at least one elongate light source and at least one reflector surface arranged—seen from the region to be illuminated—neighbouring the light source, the luminaire housing forms a light exit opening which is closed by a light exit element. The light exit element has in a first emission region, located in substance in front of the light source, a first light emission characteristic, and has in a second emission region, separate from the first emission region, a second light emission characteristic different with respect to the first light emission characteristic. | 2009-12-10 |
20090303738 | DISPLAY DEVICE FOR A MOTOR VEHICLE, COMPRISING A SUBSTANTIALLY PARALLEL LIGHT BEAM - Disclosed is a display device for a motor vehicle, particularly for a combined instrument of a motor vehicle. The display device comprises a display area and an illumination means that is provided with a light emission area and a light source. The display area has a visible face and a rear face. The illumination means is disposed on the rear face of the display area. A light beam that is emitted from the light emission area is incident directly on the rear face of the display area. The light beam has an angle of spread of less than about 20°. | 2009-12-10 |
20090303739 | Adjustable underhood light - An adjustable light, comprising, a power track, two clips, a battery cable, a repositionable semi-rigid corrugated tube and a plurality of line voltage pendant lights. The two clips slidably insert into track upper channel, wherein the clips clamp the track to the lateral edges of the underside of any size automobile hood. The battery cables supply low voltage power to the track. The tubes connect the lights to the track lower channel. An auto mechanic working under an auto hood can reposition the lights by bending the tubes, which remain in bent position until repositioned. | 2009-12-10 |
20090303740 | SUBASSEMBLY FOR THE MOUNTING OF A HEADLIGHT - A deformable subassembly ( | 2009-12-10 |
20090303741 | VEHICLE HEADLIGHT CAPABLE OF COMPENSATING FOR LIGHT INTENSITY OF DARK REGION - A vehicle headlight capable of compensating for light intensity of a dark region includes a lamp holder, a light source, a light shield, and a light guide. The lamp holder defines an accommodation space, and includes a reflector and a lens disposed on a front side of the reflector. The light source is installed in the accommodation space and disposed along an optical axis, and light rays emitted from the light source are refracted by the lens and emitted forwards. The light shield is assembled on the lamp holder and located between the light source and the lens, and the light shield is used to shield some of the light rays emitted from the light source. The light guide conducts some of the light rays towards the lens, such that the light rays are emitted forwards and upwards, thereby compensating for the light intensity of the dark region above the optical axis. | 2009-12-10 |
20090303742 | VEHICLE LAMP - There is provided a vehicle lamp. The vehicle lamp includes a lamp body including a hole portion therein; an outer lens, attached to the lamp body to form a lamp chamber; a lamp unit provided in the lamp chamber and including a light emitting element serving as a light source; a heat sink; and a fan. The heat sink includes a base portion fitted into the hole portion of the lamp body; outer fins disposed on a surface of the base portion and extending outside of the lamp body; and inner fins disposed on another surface of the base portion and extending into the lamp chamber. The fan moves air in the lamp chamber toward the inner fins, which are configured such that the air passing between the respective inner fins is guided toward the outer lens. | 2009-12-10 |
20090303743 | Display including waveguide, micro-prisms and micro-mirrors - A display including a light source for generating light, an optical waveguide for receiving and evenly distributing light in a light propagation direction by total internal reflections and a matrix of electromechanical picture elements for modulating light to produce an image. | 2009-12-10 |
20090303744 | PLANAR ILLUMINATION DEVICE - It is an object to provide a planar illumination device that is thin and light weight, and can emit uniform illumination light with little brightness unevenness and can be enlarged in size. It is to provide a planar illumination device comprising: a first light source and a second light source which are arranged at predetermined intervals; and a light guide plate which is arranged between the first light source and the second light source and has: a light exit surface; a first light incident surface which is opposed to the first light source and includes a side of the light exit surface; a second light incident surface which is opposed to the second light source and includes an opposite side to the side; and a rear surface which is formed to be opposed to the light exit surface, wherein a cross section on a plane perpendicular to the side, of the rear surface of the light guide plate has a curved line in which a distance from the light exit surface increases with a shift from the first light incident surface and the second light incident surface to a center, an inclined angle relative to the light exit surface reduces with a shift from the first light incident surface or the second light incident surface to the center, and the inclined angle relative to the light exit surface is zero degrees at the center. | 2009-12-10 |
20090303745 | Display backlight - A backlight assembly includes an array of optical waveguides that are arranged in rows and columns. The array of optical waveguides has a planar upper surface substantially comprised of light exit facet of optical waveguides and spaced-apart lower surface substantially comprised of light input facet of optical waveguides. Backlight assembly also includes a light reflector panel that is spaced-apart from the lower surface of the array. Disposed between reflector panel and the lower light input facet of the optical waveguides are light sources. Light sources comprise light emitting diodes having 120 degree emission angles. | 2009-12-10 |
20090303746 | EDGE SHADOW REDUCING METHODS FOR PRISMATIC FRONT LIGHT - Embodiments herein relate to light systems designed to reduce Moiré interference while simultaneously reducing dark regions due to the edge shadow effect. For example, configurations of light sources, light guides and turning features may direct light across a display while reducing Moiré interference. | 2009-12-10 |
20090303747 | HEAT DISSIPATING STRUCTURE OF BACKLIGHT MODULE - A heat dissipating structure of a backlight module includes two light emitting portions and a backlight portion having a light guide plate, a back reflector and a metal clad. The light guide plate is connected to the back reflector. A dent is formed and attached to the light guide plate. The back reflector is connected to the metal clad. Each light emitting portion includes a metal cover, a lamp cup reflector, at least one lamp tube and lamp holders. The lamp cup reflector is attached to the metal cover. A containing groove is formed at the lamp cup reflector and contains the lamp tubes and lamp holders. A thermal conducting plate is extended from the metal cover and contacted with the metal clad. Thus, the heat produced by the lamp tube can be conducted to the metal clad through the lamp holder and the metal cover for heat dissipation. | 2009-12-10 |
20090303748 | LIGHT GUIDE DEVICE AND BACKLIGHT MODULE - A light guide device and a backlight module. The backlight module comprises a light guide device and a plurality of light sources. The light guide device comprises a housing, comprising a frame around the housing; and a light guide plate, integrated inside the frame and comprising a light-emitting surface on one side of the light guide plate inside the frame and a light-receiving surface on one edge of the light guide plate, wherein a plurality of slots are disposed between the light guide plate and the frame and on other edges different from the edge whereon the light-receiving surface is disposed, and each of a plurality of barriers is disposed on an inner side of the light guide plate while being adjacent to one of the plurality of slots. The barriers are capable of reflecting the light traveling toward the frame back to the backlight module to improve the light efficiency. | 2009-12-10 |
20090303749 | Pick-Up Apparatus for Inductive Power Transfer Systems - An Inductive Power Transfer (IPT) pick-up apparatus includes a magnetically permeable core, a first coil, being wound about the core so as to be inductive coupled therewith such that a current induced in the first coil is most sensitive to a first directional component of magnetic flux and a second coil, being wound about the core so as to be inductively coupled therewith such that a current induced in the second coil is most sensitive to a second directional component of magnetic flux. The first directional component is substantially orthogonal to the second directional component. | 2009-12-10 |
20090303750 | METHOD AND SYSTEM OF SYNTONIC CIRCUIT MODULATION CONTROLLING - A modulation control method and system for a resonance circuit that generally relate to electrical communication technique. In the system, a controlling chip of the resonance circuit is connected to associated controlling means providing voltage matching and resistance control. The controlling means provides controlling parameters to the chip in accordance with input voltage. The controlling chip modulates the resonance circuit accordingly. A phase-shifting pulse width modulation controlling chip or a pulse width modulation controlling chip is connected to a voltage matching module and a resistance controlling module, wherein the voltage matching module matches the voltage ranges and the resistance controlling module adjusts the equivalent resistance of RT terminal to the external as the voltage of loop circuit changes accordingly. In the method, a controlling chip is used to realize a controlling mode of frequency modulation, pulse width modulation, and combination thereof with respect to the resonance circuit through the voltage matching module and the resistance controlling module. The present invention is advantageous in low cost and high efficiency. | 2009-12-10 |
20090303751 | POWER SOURCE APPARATUS AND CONTROL METHOD THEREOF - A power source apparatus includes a DC voltage generator ( | 2009-12-10 |
20090303752 | Switching Power Supply - A switching power supply includes an active device for pulling out a part of a control signal from a control terminal of the switching device in an RCC, and a control signal generation circuit that applies adjustment voltage as ON/OFF time control voltage to a control terminal of the active device. The active device pulls out the control signal so as to decrease or increase an OFF time of the switching device while fixing the ON time of the switching device when the adjustment voltage is decreased or increased in the active region of the active device, respectively. An element of a timing circuit in the RCC pulls out the control signal so as to increase or decrease an ON time of the switching device while fixing the OFF time of the switching device when the adjustment voltage is decreased or increased in the cut-off region of the active device, respectively. | 2009-12-10 |
20090303753 | Multi-Element Resonant Converters - A resonant switched power converter having switching frequency controlled in response to an output voltage thereof achieves over-current protection such as at start-up or under short circuit conditions using a resonant tank circuit which provides a notch filter in addition to a band pass filter. A additional band pass filter provided in the resonant tank circuit achieves increased power transfer to a load and reduced circulating resonant currents and conduction losses. The inductances of the preferred LCLCL tank circuit or other tank circuit with two pass band filters and a notch filter may be integrated into a single electrical component. | 2009-12-10 |
20090303754 | SWITCHING MODE POWER SUPPLY AND A METHOD OF OPERATING THE POWER SUPPLY IN A POWER SAVE MODE - A switching mode power supply and a method of operating the power supply in a power save mode. The switching mode power supply includes a first PWM controller and a second PWM controller that are driven by different driving voltages and control first and the second voltages to be output, respectively, a first transformer that is controlled by the first PWM controller to output the first voltage and having a primary coil, a secondary coil to induce the first voltage, and an auxiliary winding, and a rectifier that rectifies and smoothes a current flowing through the auxiliary winding of the first transformer, generates a power save mode voltage based on the respective driving voltages of the first and the second PWM controllers, and supplies the power save mode voltage to the first and the second PWM controllers. Accordingly, the power save mode is operated using a voltage difference without requiring an extra controller. | 2009-12-10 |
20090303755 | POWER CONVERTER APPARATUS - A power converter apparatus for receiving an input voltage and produces an output voltage by converting includes a switching-type voltage converting circuit circuit and a voltage level tuning circuit. The switching-type voltage converting circuit circuit includes an inductor, a switch and a synchronous rectifier, wherein the switch is for disabling/enabling the energy-storing operation conducted by the inductor. The synchronous rectifier produces the output voltage by using the stored electrical energy during the above-mentioned energy-storing operation. Besides, the voltage level tuning circuit is across coupled onto the switch for reducing the voltage difference between the two terminals of the switch. | 2009-12-10 |
20090303756 | Maximum output power control of a flyback converter - A method and apparatus for a flyback converter estimate the next value of the current limit for the flyback converter according to a present current limit value to achieve the maximum output power control of the flyback converter. An arithmetic circuit is used to calculate the next current limit value according three parameters, the present current limit value, the value of the current sense signal taken after a first time period counting from the instant when the present duty is triggered, and the variation of the current sense signal during a second time period, thereby narrowing the tolerance of the output power from the flyback converter. | 2009-12-10 |
20090303757 | METHOD OF FORMING A POWER SUPPLY CONTROLLER AND STRUCTURE THEREFOR - In one embodiment, a switching controller uses an auxiliary winding voltage of a transformer to form a signal representative of current flow through a secondary winding of the transformer. | 2009-12-10 |
20090303758 | CONVERTER - A converter for converting alternating voltage into direct voltage and vice versa in a converter station of a high voltage transmission system including a series connection of a plurality of converter valves. The converter has connections to transformers on both of two opposite sides of the converter valves. | 2009-12-10 |
20090303759 | DC filter and voltage source converter station comprising such filter - The resistors of a filter block in a voltage source converter station are connected with a floating neutral point. | 2009-12-10 |
20090303760 | Resonant transformer systems and methods of use - Resonant transformer systems and methods of use are described. One aspect may include a primary winding, a secondary winding, and at least one output winding. In further aspects, a transformer may be coupled to the secondary winding. In one aspect, the output winding is coupled to rectifying circuitry, which may be coupled to one or more capacitors. | 2009-12-10 |
20090303761 | CONVERTER STATION AND A METHOD FOR CONTROL THEREOF - A converter station an element adapted to determine a value of an actual temperature of any critical component of the station and an element adapted to determine a value of an actual temperature of any media used to cool the critical component. An arrangement is adapted to utilize these temperature values and information about actual cooling capacity of any cooling equipment present to cool the critical component and information about the thermal behavior of the critical component and the possible cooling media upon a possible change of the power actually transmitted through the station in a mathematical model for calculating the present overload capabilities of the converter station for use in the control of converters of the station upon a possible request of utilizing an overload capability of the station. | 2009-12-10 |
20090303762 | POWER FACTOR CORRECTION RECTIFIER THAT OPERATES EFFICIENTLY OVER A RANGE OF INPUT VOLTAGE CONDITIONS - A PFC rectifier comprises a first converter having a first output capacitor and a second converter having a second output capacitor. The he first and second capacitors are coupled to each other to increase the output voltage of the PFC rectifier. Fore example the first or second output capacitors can be serially coupled to each other. At least one or both of the first or second converters comprise buck or buck-boost converters, including inverting or non-inverter buck converters. The first and second converters can also form a bi-directional ac-ac inverter. | 2009-12-10 |
20090303763 | PHOTOVOLTAIC INVERTER - A photovoltaic inverter that can respond to changes in temperature and the amount of sunlight and that can automatically start up is provided, which has a simple configuration and is inexpensive. The photovoltaic inverter has a first voltage detection means for detecting an output voltage of a photovoltaic panel; a current detection means, a control means and a driving means. It further has a model voltage storage means for storing a model voltage table of inverter start-up kick voltages produced based on variation values of an amount of sunlight, a model voltage read-out means, a second voltage detection means for detecting an inverter start-up kick voltage, and an inverter start-up control means. | 2009-12-10 |
20090303764 | UNIVERSAL THREE PHASE CONTROLLERS FOR POWER CONVERTERS - The systems and methods described herein provide for a universal controller capable of controlling multiple types of three phase, two and three level power converters. The universal controller is capable of controlling the power converter in any quadrant of the PQ domain. The universal controller can include a region selection unit, an input selection unit, a reference signal source unit and a control core. The control core can be implemented using one-cycle control, average current mode control, current mode control or sliding mode control and the like. The controller can be configured to control different types of power converters by adjusting the reference signal source. Also provided are multiple modulation methods for controlling the power converter. | 2009-12-10 |
20090303765 | Switching power source system - An error voltage Verr, being a difference between DC output voltage Vout and output reference voltage Vref, and an input voltage Vin are multiplied to produce first threshold voltage signal Vth | 2009-12-10 |
20090303766 | METHOD AND APPARATUS FOR INCREASING THE POWER CAPABILITY OF A POWER SUPPLY - Techniques are disclosed to extend an on time period of switch to regulate a transfer of energy from an input of a power supply to an output of a power supply. One example integrated circuit includes an energy transfer element coupled between an input and an output of the power supply. A switch is coupled to the input of the energy transfer element. A controller is coupled to the switch to control switching of the switch to regulate a transfer of energy from the input of the power supply to the output of the power supply in response to a feedback signal received from the output of the power supply. The controller is coupled to limit a maximum on time period of the switch a first maximum on time period in response to a first range of power supply operating conditions and to a second maximum on time period for a second range of power supply operating conditions. | 2009-12-10 |
20090303767 | SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data. | 2009-12-10 |
20090303768 | MEMORY MODULE, METHOD FOR USING SAME AND MEMORY SYSTEM - In a multi-rank memory module having a terminal resistance of a data input/output pad | 2009-12-10 |
20090303769 | ROM ARRAY WITH SHARED BIT-LINES - Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits. | 2009-12-10 |
20090303770 | Memory chip and semiconductor device - A memory chip is provided, including internal signal/data terminals disposed in a central part of the memory chip and memory cell arrays arranged around the internal terminals to surround the same and electrically connected thereto. A semiconductor device is also provided, having a memory chip and a logic chip stacked with an interposer interposed therebetween. The logic chip has internal signal/data terminals disposed in its central part and electrically connected to the memory chip. The memory chip includes internal signal/data terminals disposed in its central part, and memory arrays arranged around the internal terminals to surround the same and connected thereto. The internal terminals of the logic chip are connected to the internal terminals of the memory chip via through holes (through electrodes) in the interposer. | 2009-12-10 |
20090303771 | RADIO FREQUENCY IDENTIFICATION DEVICE INITIALIZING A MEMORY USING AN OFFSET VOLTAGE - An RFID device sets initial data stored in a memory using an offset voltage and includes an analog block, a digital block, and a memory block. The memory blocks is configured to read/write data in a cell array unit. The memory block includes an offset controller that is configured to set an offset voltage value of a bit line connected to the cell array unit. | 2009-12-10 |
20090303772 | Two-Terminal Reversibly Switchable Memory Device - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 2009-12-10 |
20090303773 | Multi-terminal reversibly switchable memory device - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 2009-12-10 |
20090303774 | METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES - A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R. | 2009-12-10 |
20090303775 | Static random access memory cell and devices using same - A bit-cell may include a pair of cross-coupled inverters, a left bit-line, a right bit-line, a word-line and a write-line. The left bit-line may be coupled to a left inverter of the cross-coupled inverters via a left word-line transistor and a left write-line transistor. The right bit-line may be coupled to a right inverter of the cross-coupled inverters via a right word-line transistor and a right write-line transistor. The word-line may be coupled to the gates of the left and right word-line transistors and the write-line may be coupled to the gates of the left and right write-line transistors. A memory device may include a controller, an array of such bit-cells and a differential sensing buffers. Further, a computing device may include a processor and a memory device having the above bit-cells. | 2009-12-10 |
20090303776 | STATIC RANDOM ACCESS MEMORY CELL - A six transistor (“6T) static random access memory (“SRAM”) cell and method for using the same are disclosed herein. The 6T SRAM cell includes a single read pass gate transistor and a single write pass gate transistor. The single read pass gate transistor is connected to a read bit line and a read word line. The single write pass gate transistor connected to a write bit line and a write word line. | 2009-12-10 |
20090303777 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the invention includes plural writing word lines; first and second writing bit lines that intersect with the writing word lines; and plural memory cells that are provided at portions in which the plural writing word lines and the first and second writing bit lines intersect with each other. In the semiconductor memory device, the memory cell includes a flip-flop circuit that includes first and second nodes of a complementary pair; a first transfer transistor that is connected between the first writing bit line and the first node, a gate of the first transfer transistor being connected to the writing word line; and a second transfer transistor that is connected between the second writing bit line and the second node, a gate of the second transfer transistor being connected to the writing word line. The first and second writing bit lines are in a floating state whenever data is not written in the memory cell. | 2009-12-10 |
20090303778 | Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices - Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit. | 2009-12-10 |
20090303779 | Spin Torque Transfer MTJ Devices with High Thermal Stability and Low Write Currents - An integrated circuit structure includes a first fixed magnetic element; a second fixed magnetic element; and a composite free magnetic element between the first and the second fixed magnetic elements. The composite free magnetic element includes a first free layer and a second free layer. | 2009-12-10 |
20090303780 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL - An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line. | 2009-12-10 |
20090303781 | Method and apparatus for thin film memory - A multi-layer thin-film device includes thin film memory and thin film logic. The thin film memory may be programmable resistance memory, such as phase change memory, for example. The thin film logic may be complementary logic. | 2009-12-10 |
20090303782 | Standalone thin film memory - A standalone memory device includes thin-film peripheral circuitry, including decoding circuitry. The standalone thin film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass. The memory is configured for operation with an external memory controller. | 2009-12-10 |
20090303783 | Thin film input/output - Input/Output circuitry employs thin-film switching devices to drive output signals from an integrated circuit to an external device and to receive input signals from an external device. Three terminal ovonic threshold switches (3T OTS) may be employed to drive input and output signals. | 2009-12-10 |
20090303784 | Asymetric threshold three terminal switching device - An asymmetric-threshold three-terminal electronic switching device includes three terminals coupled to a threshold-switching material. A signal applied across first and second terminals affects an electrical characteristic between the second and third electrodes to a greater extent than the same signal applied across the first and third electrodes. The affected electrical characteristic may be a threshold voltage or conductivity, for example. | 2009-12-10 |
20090303785 | PHASE CHANGE MEMORY DEVICES AND READ METHODS USING ELAPSED TIME-BASED READ VOLTAGES - A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described. | 2009-12-10 |
20090303786 | SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS - The present invention provides at least one programmable via structure that includes at least two phase change material vias that are both directly contacting a heating element, the programmable via structure further including a first terminal in contact with a first portion of the heating element, a second terminal in contact with a second portion of the heating element, a third terminal in contact with one of the at least two programmable vias, and a fourth terminal in contact with another one of the at least two programmable vias; a first circuit block in contact with one of the third and fourth terminals; a second circuit block in contact with the third or fourth terminal not contacting the first circuit block; a source region of a first field effect transistor in contact with one of the first and second terminals; and a drain region of a second field effect transistor in contact with the first or second terminal that is not contacting the source region of the first field effect transistor. A method of operating the at least one programmable via structure is also provided. | 2009-12-10 |
20090303787 | NONVOLATILE MEMORIES WITH TUNNEL DIELECTRIC WITH CHLORINE - In a nonvolatile memory cell with charge trapping dielectric ( | 2009-12-10 |
20090303788 | METHODS AND APPARATUS UTILIZING PREDICTED COUPLING EFFECT IN THE PROGRAMMING OF NON-VOLATILE MEMORY - Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized to tighten the distribution of threshold voltages for a given bit pattern by compensating for anticipated threshold voltage shift due to capacitive coupling, which can facilitate more discernable Vt ranges, and thus a higher number of bits of data per memory cell. Tightening the distribution of threshold voltages can further facilitate wider margins between Vt ranges, and thus an increased reliability in reading the correct data value of a memory cell. | 2009-12-10 |
20090303789 | DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT - Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page bit values of a complete page of MLC memory cells when a count of the lower page data values is equal to or greater than a particular value or a comparison of current levels compared with a reference current level is equal to or exceeds some threshold condition. Memory devices and methods are also disclosed providing a means for determining initial programming pulse conditions for a population of memory cells based on the number of lower page data values being programmed to a logical 0 or a logical 1 data state. | 2009-12-10 |
20090303790 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation. The semiconductor memory device includes:
| 2009-12-10 |
20090303791 | Semiconductor Memory Device for Storing Multivalued Data - Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction. | 2009-12-10 |
20090303792 | METHOD FOR PROGRAMMING A MULTILEVEL MEMORY - A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K | 2009-12-10 |
20090303793 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 2009-12-10 |
20090303794 | Structure and Method of A Field-Enhanced Charge Trapping-DRAM - A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments, the FE-TDRAM device comprises a charge trapping FinFET structure including an upside-down U-shaped volatile programmable structure and an upside-down U-shaped dielectric structure overlying the volatile programmable structure. | 2009-12-10 |
20090303795 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 2009-12-10 |
20090303796 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device including: a memory cell coupled to a bit line via a select gate transistor; a sense amplifier configured to have a current source for supplying current to the bit line, and detect cell current of the memory cell flowing on the bit line; and a select gate line driver configured to drive the select gate transistor so as to keep the memory cell applied with substantially constant drain-source voltage independently of the bit line resistance at a read time. | 2009-12-10 |
20090303797 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the substrate, a first gate electrode formed on the gate insulating film, source and drain regions formed in the substrate so as to sandwich the first gate electrode, an intergate insulating film formed on the first gate electrode and including an opening, a second gate electrode formed on the intergate insulating film and electrically connected to the first gate electrode through the opening, and a boost electrode formed on the intergate insulating film and electrically isolated from the first gate electrode and the second gate electrode. | 2009-12-10 |
20090303798 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 2009-12-10 |
20090303799 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD THEREOF - A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit. | 2009-12-10 |
20090303800 | NON-VOLATILE MEMORY CONTROL CIRCUIT - An efficient erasure is performed. The voltage of a source line SL is manipulated in units of a sector comprising a plurality of memory cells. An erase command is received for the desired memory cells to be erased in a plurality of word line WL units arranged within a sector and all data within the sector, which includes the desired memory cells to be erased, is saved in a separate memory. Erasure is then performed for the entire sector, and among the saved data the data outside the desired memory cells to be erased is returned to the memory cells. | 2009-12-10 |
20090303801 | Carbon nanotube memory including a buffered data path - Carbon nanotube memory comprises a buffered data path including a forwarding write line and a returning read line for transferring data. Furthermore, bit line is multi-divided for reducing parasitic capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives a memory cell output through the bit line, a segment sense amp receives a local sense amp output, and a global sense amp receives a segment sense amp output. By the sense amps, a voltage difference in the bit line is converted to a time difference for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as reference signal. Additionally, alternative circuits and memory cell structures for implementing the memory are described. | 2009-12-10 |
20090303802 | SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM HAVING TERMINATION RESISTOR UNITS - A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a command/address buffer that receives a command/address signal and a second reference voltage via first and second input terminals, and a first termination resistor unit connected to the first input terminal of the data input buffer. The semiconductor memory module further includes a second termination resistor unit located on the memory module board and connected to an internal command/address bus. The first termination resistor unit includes a first resistor connected between a first voltage source and the first input terminal of the data input buffer, and the second termination resistor unit includes a second resistor connected between a second voltage source and the first input terminal of the command/address input buffer. | 2009-12-10 |
20090303803 | Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Voltage Mode Sensing - A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels. | 2009-12-10 |
20090303804 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal of an active command mode, an equalizing signal generating unit configured to generate an equalizing signal which is controlled with an overdriving voltage VPP level higher than a normal drive voltage during a first duration of an activation period and with the normal drive voltage VDD during a second duration of the other activation period after the first duration in response to the first drive signal and the second drive signal, and an equalization unit configured to equalize first and second lines in response to the equalizing signal. | 2009-12-10 |
20090303805 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite to the predetermined logic value, an erasing operation is needed and the data writing is regulated. By rewriting a pointer value stored in a pointer memory in place of performing the erasing operation, an operation of switching a memory core to be selected to a second memory core (data “11111111”) is performed. Data is newly written into the second memory core selected by the rewritten pointer value. | 2009-12-10 |
20090303806 | SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include,.but is not limited to, a storing unit and a selecting unit. The storing unit stores serial input data at at least one of a first type edge and a second type edge of a clock signal. The selecting unit receives the input data from the storing unit. The selecting unit selects the input data. The selecting unit outputs the selected input data in parallel. | 2009-12-10 |
20090303807 | Semiconductor device and semiconductor system having the same - A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished. | 2009-12-10 |
20090303808 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks. | 2009-12-10 |
20090303809 | CIRCUIT AND METHOD FOR TERMINATING DATA LINE OF SEMICONDUCTOR INTEGRATED CIRCUIT - A data line termination circuit in a semiconductor integrated circuit includes a data line, a control unit for generating a termination control signal activated during a time section that includes a driving section in which data is driven to the data line, and a termination unit for terminating the data line to a predetermined voltage level in response to the termination control signal | 2009-12-10 |
20090303810 | Semiconductor memory device - Disclosed is a semiconductor memory device. The semiconductor memory device includes a signal generating unit for generating first and second enable signals in response to a power-up signal, a first sub-word line signal driving unit for driving a first sub-word line signal in response to the first enable signal, a first voltage supplying unit for supplying a first voltage to a pair of bit lines in response to the first enable signal, a second sub-word line signal driving unit for driving a second sub-word line signal in response to the second enable signal, and a second voltage supplying unit for supplying a second voltage to a pair of bit lines in response to the second enable signal. | 2009-12-10 |
20090303811 | ROW ADDRESS DECODER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight lo main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times. | 2009-12-10 |
20090303812 | PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS - A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches. | 2009-12-10 |
20090303813 | INTEGRATED CIRCUIT THAT STORES FIRST AND SECOND DEFECTIVE MEMORY CELL ADDRESSES - An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circuit detects second defective memory cells via the sense first addresses and stores second addresses of the second defective memory cells in the volatile storage and in the non-volatile storage. | 2009-12-10 |