49th week of 2011 patent applcation highlights part 28 |
Patent application number | Title | Published |
20110299279 | MICROCHANNEL COOLER FOR LIGHT EMITTING DIODE LIGHT FIXTURES - A lighting module has an array of light emitters, a heat sink having a first surface, the array of light emitters being mounted to the first surface, a microchannel cooler arranged on a second surface of the heat sink on an opposite side of the heat sink from the first surface, the microchannel cooler arranged to transport a liquid through a channel on the second surface of the heat sink, and a cooling unit thermally coupled to a microchannel cooler and arranged to remove heat from the liquid. | 2011-12-08 |
20110299280 | LIGHTING UNIT - A lighting unit includes a fire resistant housing ( | 2011-12-08 |
20110299281 | SYSTEM FOR RETROFITTING AN EXISTING LIGHT FIXTURE WITH AN LED LUMINAIRE - An adapter plate is provided that fits an existing luminaire in place of an existing globe that mounts to the luminaire. A heat sink mates to the adapter plate and also houses a solid state light engine and associated electronics. The heat sink may provide an enclosed, protective volume for the associated electronics, such as a power supply for the solid state light engine. A globe mounting ring attached to the heat sink allows either an existing globe to be re-mounted or a new globe to be installed. | 2011-12-08 |
20110299282 | WINDOW ASSEMBLY FOR USE IN SUBSTRATE PROCESSING SYSTEMS - Embodiments of a window assembly are provided herein. In some embodiments, a window assembly for use in a substrate processing system comprising a first window at least partially transparent to light energy; a second window transparent to light energy and substantially parallel to the first window; and a separator disposed proximate the peripheral edges of the first and second windows and defining a sealed gap between the first and second windows, wherein the separator has an inlet and outlet to flow a gas through the sealed gap. In some embodiments, one or more support elements are disposed in the sealed gap to maintain a substantially uniform gap distance between the first and second windows. In some embodiments, a plurality of light adjusting elements are disposed in the gap to adjust one or more properties of light energy that passes through the light adjusting element. | 2011-12-08 |
20110299283 | REFLECTIVE DEVICE FOR AN ELECTRIC FIREPLACE AND AN ELECTRIC FIREPLACE INCORPORATING THE SAME - A reflective device for use in an electric fireplace and a fireplace incorporating the same. The reflective device includes a shaft having a first and a second end cap mounted at opposite ends. An intermediate member extends outwardly from the shaft between the first and second end caps. One or more reflecting strips extend longitudinally between the first and second end caps and are spaced a distance away from the shaft. The reflecting strips are separated from each other by longitudinal gaps and are mounted so that they angle downwardly relative to the shaft from the intermediate member toward the first and second end caps. The shaft is rotated about its longitudinal axis so that it reflects light from a light source toward one of a screen, simulated ember bed and artificial log display in the fireplace housing. | 2011-12-08 |
20110299284 | SOLID STATE LIGHT SOURCE EMITTING WARM LIGHT WITH HIGH CRI - Solid state light sources, lighting devices and lamps arranged to provide emission with a warm temperature and high CRI. One embodiment of a solid state lighting device according to the present invention comprises a light emitting diode (LED) device capable of emitting light in an emission spectrum. A filter arranged so that at least some light from the LED light source passes through it, with the filter filtering at least some of one or more portions of the light source emission spectrum. The resulting light source light has a different temperature but substantially the same CRI after passing through the filter. | 2011-12-08 |
20110299285 | FILTER DEVICE FOR THE COMPENSATION OF AN ASYMMETRIC PUPIL ILLUMINATION - The invention relates to a filter device for an illumination system, especially for the correction of the illumination of the illuminating pupil, including a light source, with the illumination system being passed through by a bundle of illuminating rays from the light source to an object plane, with the bundle of illuminating rays impinging upon the filter device, including at least one filter element which can be introduced into the beam path of the bundle of illuminating rays, with the filter element including an actuating device, so that the filter element can be brought with the help of the actuating device into the bundle of illuminating rays. | 2011-12-08 |
20110299286 | LED LAMP - An LED lamp at least includes an LED lamp set and an adjustment assembly. The LED lamp set includes an LED set and a cooling set. The LED set includes at least one LED lamp element which is replaceable individually and a holder to hold the LED lamp element. The cooling set is fastened to the holder. The adjustment assembly includes an adjustment member and an adjustment holder that contain mating engaging portions engageable with each other. The adjustment member is coupled with the adjustment holder and the LED lamp set to provide adjustment function of light illumination angle. The invention further includes an assembly dock coupled with a plurality of LED lamp sets and adjustment assemblies according to requirements to enhance expandability and usability. The structure thus formed can be assembled and disassembled easily, and also provides greater expandability, replacement capability and practicality. | 2011-12-08 |
20110299287 | FOCUSING MECHANISM FOR LED SPOT LAMP - A focusing mechanism for LED spot lamp includes a lamp seat and a lens barrel being extendably assembled to the lamp seat. The lamp seat has an LED chip mounted thereon. The lens barrel includes a barrel body having a bottom portion and an opposing top portion, and a lens mounted to the top portion. The bottom portion of the lens barrel is assembled to the lamp seat via an extension coupling structure, such that the lens is located above the LED chip to cover the same. With the extension coupling structure, the lens barrel can be adjusted in position to project from the top of the lamp seat by different distances, so that the focal length between the lens and the LED chip can be regulated to accordingly regulate the focusing and diffusing effects of light emitted from the LED chip. | 2011-12-08 |
20110299288 | Solder and Lead Free Electronic Circuit and Method of Manufacturing Same - An electronic circuit contains a circuit board with conducting tracks to which one or more electronic components with conducting contacts are positioned overlying portions of the conducting tracks and each such electronic component is held in place by a clamp that covers and is contact with the top surface of the electronic components so as to hold their conducting contacts in electrical contact with the conducting tracks of the circuit board. The clamp can include a resilient layer held between the top surface of electronic components and a rigid clamping sheet. | 2011-12-08 |
20110299289 | Self-Aligning Light Source and Detector Assembly - Self-aligning light source and detector assembly having a sensor support mounted in a predetermined, fixed position, a light source holder mounted in a predetermined, fixed position relative to the sensor support, a sensor mounted in a fixed position on the sensor support, and a lamp assembly removably mounted to the light source holder in a predetermined position defined by mating surfaces which engage each other and seat the lamp assembly in the predetermined position whenever the lamp assembly is installed in the holder. | 2011-12-08 |
20110299290 | Light fixture mounting method and assembly - An assembly for mounting a light fixture in a hole in a ceiling panel and including an annular trim ring that's held upward against a lower surface of a ceiling panel by the light fixture to be mounted, such that the trim ring spans an annular gap between such light fixture and the ceiling panel hole. A top plate is carried by the ceiling panel across the ceiling panel hole and includes a top plate hole that receives the light fixture to be mounted such that the top plate spans an annular gap between the light fixture and the ceiling panel hole. A mount supports the light fixture on the top plate in a position holding the trim ring up against the lower surface of the ceiling panel. | 2011-12-08 |
20110299291 | MULTI-LAMP FLUORESCENT LIGHTING FIXTURE APPARATUS AND WIRING METHOD - A fluorescent lamp fixture apparatus ( | 2011-12-08 |
20110299292 | Flexirigid support plate - In various embodiments, a rigid-flex mounting board for at least one semiconductor light source is provided. The mounting board may include at least one rigid support region configured to mount the at least one semiconductor light source; and a flexible support region, wherein the flexible support region has been produced by thinning of a rigid support region. | 2011-12-08 |
20110299293 | AIRCRAFT POSITION LIGHT ASSEMBLY - An aircraft position light assembly having one or more light emitting diode (LED) modules. The LED module can be installed in a variety of aircraft wing-tip cavities. An example LED module includes a support device that mounts within an aircraft wingtip, a bracket device that attaches to the support device, at least one circuit board that mounts to the bracket, and two pairs of LEDs. Each pair of LEDs is mounted on opposing major surfaces at a first end of the circuit board. A first pair of reflectors is attached to the circuit board adjacent to two of the LEDs on the opposing major surfaces. A second pair of reflectors is attached to the circuit board adjacent to the other two LEDs on the opposing major surfaces. | 2011-12-08 |
20110299294 | LIGHTED EXTERIOR REARVIEW MIRROR SYSTEM - A lighted exterior rearview mirror system includes an exterior rearview mirror assembly including a reflective element and an electrically-operable actuator. The exterior rearview mirror assembly includes a breakaway joint assembly. The reflective element has an electrically powered heater operable to remove ice or dew from the reflective element. The exterior rearview mirror assembly includes a turn signal indicator lamp that has a light source and a lens. The lamp is included in the exterior rearview mirror assembly and unaffected by operation of the actuator. The breakaway joint assembly includes a wire-way through which a wire cable passes. The wire cable includes wires for operating the actuator, the heater and the lamp. The light source includes at least one light emitting diode. | 2011-12-08 |
20110299295 | LIGHT EMITTING DEVICE AND OPTICAL ELEMENT - Disclosed are a light emitting device and a light emitting element that can decrease fabrication difficulties, while improving lighting efficiency and controlling the distribution of intensity that occurs in the emitted light. A light emitting device comprises a rod-shaped light guide, an LED that inputs light to the light guide, and a prism that changes the direction of light input from the lengthwise end of the light guide, and emits redirected light from a light exit surface that is disposed opposite the prism. The light emitting device is constituted so that an input lens is formed at the lengthwise end of the light guide as a parallel light forming body to make light exiting from the LED toward the light guide nearly parallel light, and the LED is shifted from the center axis of the light guide toward the side closer to the prism, or toward the side away from the prism, and thus said nearly parallel light is directed to the exit surface of the light guide or to the prism. | 2011-12-08 |
20110299296 | BACKLIGHT MODULE AND HEAT DISSIPATION MODULE - A backlight module includes a back plate having a trench, a light guide plate disposed on the back plate, a reflecting sheet disposed between the back plate and the light guide plate, a heat dissipation module, and a light emitting element. The heat dissipation module includes a heat dissipation element, a heat conducting element, and a position-limiting element. The heat dissipation element is disposed on the back plate. The heat conducting element is disposed in the trench. One end of the heat conducting element is aligned with the heat dissipation element. The first position-limiting element is detachably assembled in the trench and supports the reflecting sheet. One section of the heat conducting element is pressed onto a bottom wall of the trench by the first position-limiting element. The light emitting element is disposed on the heat dissipation element and faces one side of the light guide plate. | 2011-12-08 |
20110299297 | BACKLIGHT MODULE - A backlight module may include an optical substrate, at least one light guide pipe, and at least one first light source. At least one accommodation trench is disposed on the optical substrate for accommodating the light guide pipe. The first light source is disposed at one side of the light guide pipe and is arranged for emitting at least one first light into the light guide pipe. The first light is transferred in the light guide pipe and leaves the light guide pipe when being reflected by the optical substrate. | 2011-12-08 |
20110299298 | BACKLIGHT MODULE - A backlight module including a plurality of light guide plates, a plurality of light emitting devices, and a back frame is provided. The adjacent light guide plates are coupled with each other to form a piece-coupled light guide plate. The light emitting devices provides light to the piece-coupled light guide plate. The back frame has a back sheet and a bending element. The back sheet has at least one broken hole. The bending element is disposed near the broken hole and forms an angle with the back sheet. The bending element has a locking groove, and the piece-coupled light guide plate is leaned against the locking groove. A supporting and fastening device can be adopted to further fasten the piece-coupled light guide plate and films below the piece-coupled light guide plate. Additionally, a reflector is disposed below the piece-coupled light guide plate for reflecting the light upwards. | 2011-12-08 |
20110299299 | ANTENNA WITH LIGHTING FUNCTION FOR MOBILE COMMUNICATION SYSTEM - An antenna with a lighting function for a mobile communication system is provided. The antenna includes a radome for passing or spreading light through at least one specific part, and at least one light source for irradiating light to the radome. | 2011-12-08 |
20110299300 | LIGHTING SYSTEM FOR A DATA DISPLAY DEVICE INCLUDING A LIGHT GUIDE - Lighting system for a data display device ( | 2011-12-08 |
20110299301 | FIXED-FREQUENCY LLC RESONANT POWER REGULATOR - An LLC resonant AC/DC power regulator system ( | 2011-12-08 |
20110299302 | RESONANT CONVERTER SYSTEM WITH HYBRID CONTROL APPARATUS AND CONTROLLING METHOD THEREOF HAVING RELATIVELY BETTER EFFICIENCY - The configurations of a resonant converter system and a controlling method thereof are provided. The proposed resonant converter system includes a resonant converter and a hybrid control apparatus coupled to the resonant converter for generating a driving signal to adjust a phase angle and a frequency of the resonant converter such that the resonant converter would reach a relatively lower voltage gain and have a relatively lower loss during an abnormal operation. | 2011-12-08 |
20110299303 | Inverter of new and renewable energy storage system - Provided is an inverter of a renewable energy storage system, which has an input port and an output port electrically insulated, and is compact and low-priced, while having a simplified circuit. The inverter includes a DC-DC converting unit connected to the DC link, and an inverting unit connected between the DC-DC converting unit and the power system, wherein the DC-DC converting unit is an unregulated DC-DC bus converter. | 2011-12-08 |
20110299304 | DC/DC CONVERTER WITH MAGNETIC FLUX DENSITY LIMITS - A DC/DC converter may include a power stage circuit, a pulse generator circuit, a flux density monitor, and power control logic. The power stage circuit includes an input, an output, and a transformer with a core. The power stage circuit may be configured to operate in a power transfer mode during which power is transferred from the input to the output and a reset mode during which flux density in the core of the transformer is reduced. The pulse generator circuit may be configured to generate pulses that regulate the output of the power stage circuit. The flux density monitor circuit may be configured to generate flux density information indicative of the flux density of the core of the transformer during both the power transfer mode and the reset mode. The power stage control logic may be configured to regulate the output of the power stage circuit based on the pulses and to prevent the core of the transformer from saturating based on the flux density information. | 2011-12-08 |
20110299305 | DIGITAL DYNAMIC DELAY MODULATOR AND THE METHOD THEREOF FOR FLYBACK CONVERTER - A digital dynamic delay modulator and the method thereof are applied to a flyback converter. A first input voltage signal from the flyback converter is received and compared with a threshold voltage to determine whether a counting condition is matched. When the counting condition is matched, an integer predetermined count number is counted to determine a delay time. After finishing the counting, a first output signal is generated to turn on a switching device for the flyback converter. The slope of the first input voltage signal is detected when the switching device is turned on, and the slope is used to adjust the count number with integer increment/decrement. Therefore, the delay time for switching the flyback converter can be precisely controlled in digital and dynamic manner. | 2011-12-08 |
20110299306 | METHOD AND APPARATUS FOR A CONTROL CIRCUIT RESPONSIVE TO AN IMPEDANCE COUPLED TO A CONTROL CIRCUIT TERMINAL - An example power supply controller includes a regulation circuit, a current sense circuit, and a response circuit. The regulation circuit is coupled to regulate a sense terminal to a voltage level. The current sense circuit is coupled to the sense terminal to sense a current through the sense terminal a measurement delay period after a magnitude of the current through the sense terminal reaches a first threshold current level. The response circuit is coupled to the sense circuit and is responsive to the current through the sense terminal only after the measurement delay period. | 2011-12-08 |
20110299307 | UNINTERRUPTIBLE POWER SUPPLY APPARATUS - An uninterruptible power supply apparatus includes a cooler cooling a converter/chopper circuit and a cooler cooling a PWM inverter. The converter/chopper circuit and the cooler make up one integrated unit. Accordingly, a smaller apparatus can be achieved, compared with a conventional apparatus in which a cooler is provided for each of a converter and a chopper. | 2011-12-08 |
20110299308 | COMMON MODE VOLTAGE REDUCTION APPARATUS AND METHOD FOR CURRENT SOURCE CONVERTER BASED DRIVE - Current source converter drives and common mode voltage reduction techniques are presented in which a space vector modulation zero vector for current source inverter (or rectifier) control is selected according to the switching state of the current source rectifier (or inverter) and according to the AC input power and the AC output power to control the output common mode voltage. | 2011-12-08 |
20110299309 | Ultra-High Efficiency Switching Power Inverter and Power Amplifier - An apparatus for providing a power output proportional to a source signal, including a phase modulator driving an upper and an lower power driver with carrier waveforms having a relative phase difference and having a signal modulated thereon, and coupled to a resonator circuit to operate as a substantially zero-voltage zero-current switching element, with the output fed into respective upper and lower transformers. Identical symmetrical secondary circuits on the transformers have a rectifier stage electrically connected to an inductor in series with an upper capacitor to form an upper low pass filter, and a high speed semiconductor switch coupled to a node between the inductor and rectifier stage provides a return path to ground. The lower secondary circuit inductor is highly coupled (>=0.99) to the upper inductor, and an output formed across the upper and lower output elements is isolated from rail voltage and balanced with bi-directional current. | 2011-12-08 |
20110299310 | SYNCHRONOUS OPERATING SYSTEM FOR DISCHARGE TUBE LIGHTING APPARATUSES, DISCHARGE TUBE LIGHTING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A synchronous operating system for operating a plurality of discharge tube lighting apparatuses at the same frequency and same phase includes (1) an oscillator of a triangular wave signal whose inclination for charging a capacitor C | 2011-12-08 |
20110299311 | Power Generation System, Power Converter System, And Methods Of Converting Power - A power converter system includes an inverter including a first bridge and a second bridge, wherein each of the first bridge and the second bridge includes at least one switch. The power converter system also includes an inductor including a first winding coupled to an output of the first bridge and a second winding coupled to an output of the second bridge. | 2011-12-08 |
20110299312 | INVERTER FOR SOLAR CELL ARRAY - A full-bridge, NPC inverter uses pulse width modulation (PWM) to convert the DC voltage from a solar panel array to an AC voltage at the output of the inverter that is acceptable for connection to a utility. The PWM control unit has a predetermined carrier frequency. The carrier unit uses for each carrier period either positive or negative values of a reference voltage to generate a predetermined number of signals to control the switching on and off of each of the eight inverter switching elements in a predetermined pattern for a predetermined period of the carrier frequency period to thereby produce the acceptable alternating current voltage at the inverter output and not produce between the inverter input and earth ground a carrier frequency component. | 2011-12-08 |
20110299313 | VARIABLE REACTIVE ELEMENT IN A RESONANT CIRCUIT - A resonant converter is provided which may be used for supplying power to the primary conductive path of an inductively coupled power transfer (ICPT) system. The converter includes a variable reactive element in the resonant circuit which may be controlled to vary the effective inductance or capacitance of the reactive element. The frequency of the converter is stabilised to a nominal value by sensing the frequency of the converter resonant circuit, comparing the sensed frequency with a nominal frequency and varying the effective inductance or capacitance of the variable reactive element to adjust the converter frequency toward the nominal frequency. | 2011-12-08 |
20110299314 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array. | 2011-12-08 |
20110299315 | COMMUNICATION CIRCUIT FOR DRIVING A PLURALITY OF DEVICES - A system and method is provided for transmitting a signal to a plurality of slave devices (e.g., memory devices, etc.) via a communication circuit having a plurality of segments that are substantially equal in length and/or impedance. Specifically, according to one embodiment of the invention, an electronic system includes a processor, a plurality of memory devices, and a communication circuit (i.e., a bus) having a central node and a plurality of segments. Specifically, the plurality of segments are used to connect the plurality of devices (e.g., the processor, the plurality of memory devices) to the central node. For example, the processor is connected to the central node via a primary segment, the first memory device (M | 2011-12-08 |
20110299316 | Memory module, method and memory system having the memory module - The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set. | 2011-12-08 |
20110299317 | INTEGRATED CIRCUIT HEATING TO EFFECT IN-SITU ANNEALING - In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device. | 2011-12-08 |
20110299318 | SEMICONDUCTOR MEMORY CELL AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory cell includes: a memory element formed by a first field effect transistor having a gate insulating film made of a ferroelectric film; and a select switching element formed by a second field effect transistor having a gate insulating film made of a paraelectric film. The ferroelectric film and the paraelectric film are stacked together with a semiconductor film of a compound semiconductor interposed therebetween. A first gate electrode of the first field effect transistor is formed on a side of the ferroelectric film, and a second gate electrode of the second field effect transistor is formed on a side of the paraelectric film so as to face the first gate electrode. The semiconductor film forms a common channel layer of the first and second field effect transistors. | 2011-12-08 |
20110299319 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write data to the plural memory cells, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data. The data writing unit stops the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plural memory cells, according to the detection result of the resistance state detecting circuit. | 2011-12-08 |
20110299320 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array, the memory cell array including a plurality of first lines, a plurality of second lines configured to intersect the first lines, and a plurality of electrically rewritable memory cells disposed at each of intersections of the first lines and the second lines, each of the memory cells being configured from a variable resistor operative to store a resistance value of the variable resistor as data in a nonvolatile manner. A voltage supply circuit applies a certain voltage to the memory cells via the first lines and the second lines during writing data to the memory cells or forming of the memory cells. A detection circuit detects a change of the resistance value of the variable resistor in the memory cell during application of the certain voltage to the memory cells and outputs the detected change of the resistance value of the variable resistor as detection information. An output circuit outputs to external at least a portion of the detection information outputted from the detection circuit. | 2011-12-08 |
20110299321 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with an embodiment includes a plurality of first word lines, a plurality of bit lines, a resistance varying material, a plurality of second word lines and an insulating film. The bit lines intersect the first word lines. The resistance varying material is disposed at respective intersections of the first word lines and the bit lines. The second word lines intersect the bit lines. The insulating film is disposed at respective intersections of the second word lines and the bit lines. One of the first word lines and one of the second word lines are disposed so as to sandwich the bit lines. The second word lines, the bit lines, and the insulating film configure a field-effect transistor at respective intersections of the second word lines and the bit lines. The field-effect transistor and the resistance varying material configure one memory cell. | 2011-12-08 |
20110299322 | METHOD OF PROGRAMMING VARIABLE RESISTANCE ELEMENT, METHOD OF INITIALIZING VARIABLE RESISTANCE ELEMENT, AND NONVOLATILE STORAGE DEVICE - A method of programming a variable resistance element includes: performing a writing step by applying a writing voltage pulse having a first polarity to a transition metal oxide comprising two metal oxide layers which are stacked, so as to change a resistance state of the transition metal oxide from high to low, each of the two metal oxide layers having a different degree of oxygen deficiency; and performing an erasing step by applying an erasing voltage pulse having a second polarity to the transition metal oxide so as to change the resistance state of the transition metal oxide from low to high, the second polarity being different from the first polarity, wherein |Vw | 2011-12-08 |
20110299323 | Floating Source Line Architecture for Non-Volatile Memory - A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line. | 2011-12-08 |
20110299324 | WRITE CURRENT COMPENSATION USING WORD LINE BOOSTING CIRCUITRY - Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction. | 2011-12-08 |
20110299325 | SRAM Devices And Methods Of Manufacturing The Same - Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be vertically connected to the first transistors. In example embodiments, the second transistors may be vertical transistors that include vertical gates surrounding vertical channels. | 2011-12-08 |
20110299326 | TFET BASED 4T MEMORY DEVICES - A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction. | 2011-12-08 |
20110299327 | FOUR-TRANSISTOR AND FIVE-TRANSISTOR BJT-CMOS ASYMMETRIC SRAM CELLS - A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half. | 2011-12-08 |
20110299328 | Memory Arrays - Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F | 2011-12-08 |
20110299329 | BOTTOM ELECTRODE GEOMETRY FOR PHASE CHANGE MEMORY - A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode. | 2011-12-08 |
20110299330 | PSEUDO PAGE MODE MEMORY ARCHITECTURE AND METHOD - A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line. | 2011-12-08 |
20110299331 | FLASH MEMORY PROGRAM INHIBIT SCHEME - A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming. | 2011-12-08 |
20110299332 | TEST SYSTEM AND HIGH VOLTAGE MEASUREMENT METHOD - Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result. | 2011-12-08 |
20110299333 | NON-VOLATILE MEMORY PROGRAMMING - Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying different voltages to data lines associated with different memory cells based on threshold voltages of the memory cells in an erased state. Other embodiments including additional memory devices and methods are described. | 2011-12-08 |
20110299334 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array connected to word lines and bit lines, and formed by arranging a plurality of memory cells in a matrix, each memory cell storing one of n values (n is a natural number of not less than 2), and a control circuit configured to write data in the memory cells by controlling potentials of the word lines and the bit lines in accordance with input data. The control circuit performs a write verify operation a plurality of number of times by changing a voltage level, stores data of the voltage level at which verify pass occurs, and determines a write voltage based on the stored data of the voltage level. | 2011-12-08 |
20110299335 | Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed. | 2011-12-08 |
20110299336 | SINGLE-POLYSILICON LAYER NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF - A single-polysilicon layer non-volatile memory having a floating gate transistor, a program gate and a control gate is provided. The floating gate transistor has a floating gate and a tunneling dielectric layer. The floating gate is disposed on a substrate. The tunneling dielectric layer is disposed between the floating gate and the substrate. The program gate, the control gate and the erase gate are respectively disposed in the substrate under the floating gate separated by the tunneling dielectric layer. Therefore, during a program operation and an erase operation, charges are injected in and expelled out through different regions of the tunneling dielectric layer, so as to increase reliability of the non-volatile memory. | 2011-12-08 |
20110299337 | METHODS AND APPARATUS FOR AN ISFET - An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself. | 2011-12-08 |
20110299338 | Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed. | 2011-12-08 |
20110299339 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 2011-12-08 |
20110299340 | Non-Volatile Memory Having 3d Array of Read/Write Elements and Read/Write Circuits and Method Thereof - A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions. | 2011-12-08 |
20110299341 | METHOD OF PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE - A method of programming a semiconductor memory device includes the steps of grouping memory cells in accordance with levels of threshold voltages to be programmed, programming the memory cell groups by sequentially applying program voltages to the memory cell groups, and program-verifying the memory cell groups. | 2011-12-08 |
20110299342 | Flash memory device and systems and reading methods thereof - A read method of a flash memory device is provided which comprises reading a plurality of adjacent memory cells connected with a word line different from a plurality of selected memory cells; reading the plurality of selected memory cells one or more times using a plurality of coupling compensation parameters; and selectively latching the read result of the selected memory cells based on the read result of the adjacent memory cells. | 2011-12-08 |
20110299343 | NON-VOLATILE MEMORY DEVICE, PRECHARGE VOLTAGE CONTROLLING METHOD THEREOF, AND SYSTEM INCLUDING THE SAME - A non-volatile memory device, precharge voltage control method thereof, and system including the same are provided. The non-volatile memory device includes a bit line connected with a non-volatile memory cell, a precharge voltage generation circuit configured to generate a precharge voltage during a precharge operation, and a control circuit configured to apply the precharge voltage of a second level to the bit line in response to a control signal at a first level during a precharge period in a normal read operation and to apply the precharge voltage of a fourth level to the bit line in response to the control signal at the third level during a precharge period in a verify read or erase operation. | 2011-12-08 |
20110299344 | A NEW LOW VOLTAGE AND LOW POWER MEMORY CELL BASED ON NANO CURRENT VOLTAGE DIVIDER CONTROLLED LOW VOLTAGE SENSE MOSFET - A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines. | 2011-12-08 |
20110299345 | Early Read After Write Operation Memory Device, System And Method - A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. | 2011-12-08 |
20110299346 | APPARATUS FOR SOURCE-SYNCHRONOUS INFORMATION TRANSFER AND ASSOCIATED METHODS - An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device. | 2011-12-08 |
20110299347 | DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT - A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request. | 2011-12-08 |
20110299348 | SEMICONDUCTOR MEMORY DEVICE AND INTEGRATED CIRCUIT - A semiconductor memory device includes a write control signal generating circuit and a write enable signal generating unit. The write control signal generating circuit is configured to generate a write control signal activated during a time period from an input time point of a read command to an end time point of a data output time period. The write enable signal generating unit is configured to output a write command as a write enable signal in response to the write control signal. | 2011-12-08 |
20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 2011-12-08 |
20110299350 | PRECHARGE CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A precharge control circuit includes a precharge voltage supply unit for generating a precharge voltage according to a voltage level of a precharge control signal, a voltage generator for generating an operating voltage for controlling the voltage level of the precharge control signal in response to a first enable signal and a voltage control signal, and a signal generator for fixing the precharge control signal to a specific voltage level in response to a second enable signal and for linearly changing the voltage level of the precharge control signal according to a slope, determined by a level of the operating voltage, when the second enable signal is disabled. | 2011-12-08 |
20110299351 | INPUT/OUTPUT BANK ARCHITECTURE FOR AN INTEGRATED CIRCUIT - An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data. | 2011-12-08 |
20110299352 | Semiconductor device including memory cells that require refresh operation - A semiconductor device includes a first circuit that generates a self refresh signal in a predetermined cycle asynchronous with a cycle set externally, a second circuit that generates a refresh address in response to the self refresh signal and updates the refresh address and outputs the refresh address, a third circuit that retains a relief address, a fourth circuit that counts number of generation of the self refresh signal and activates an interrupt signal when a count of the number of generation reaches a predetermined count, a fifth circuit that specifies the refresh address when the interrupt signal is in an inactive state and specifies the relief address when the interrupt signal is in an active state, and a sixth circuit that performs a refresh operation on memory cells specified by the selected refresh address or the relief address. The second circuit temporarily stops updating the refresh address in response to activation of the interrupt signal. | 2011-12-08 |
20110299353 | POWER SAVING MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage to change during a time interval after a refresh operation of the memory device. Other embodiments including additional apparatus, systems, and methods are disclosed. | 2011-12-08 |
20110299354 | MEMORY ARRAY CIRCUIT INCORPORATING MULTIPLE ARRAY BLOCK SELECTION AND RELATED METHOD - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 2011-12-08 |
20110299355 | WORD LINE DRIVER FOR MEMORY - A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line. | 2011-12-08 |
20110299356 | STRAIGHT THROUGH CEMENT MIXER - A cement mixing method for mixing cement used in cementing oil wells casing and the mixer used in that method. The mixer employs a straight bulk cement inlet, five annular recirculation jets and five annular water jet orifices located downstream of the recirculation jets so that all of the jets discharge at an angle towards the mixing chamber and the discharge from the water jet orifices intersects with the flow from the recirculation jets. This five jet, intersecting flow design allows for more thorough wetting of the cement powder with a smaller, lighter, less expensive and more durable mixer that is less inclined to foul and easier to clean. | 2011-12-08 |
20110299357 | Mixing Apparatus and Method of Using Same - An apparatus and a method for admixing an additive for a drilling fluid. for use in the drilling of a petroleum well are described. The apparatus includes a mixing chamber which is connected, in terms of fluid, to an inlet line for drilling fluid, an outlet line for drilling fluid and at least one dosing device for an additive. The dosing device being arranged to supply the additive from a container to the mixing chamber and to form a pressure-tight barrier between the mixing chamber and the container. A pumping device is arranged downstream of the mixing chamber, which is arranged to suck drilling fluid through the mixing chamber. | 2011-12-08 |
20110299358 | CASSETTE SYSTEM INTEGRATED APPARATUS - A cassette integrated system. The cassette integrated system includes a mixing cassette, a balancing cassette, a middle cassette fluidly connected to the mixing cassette and the balancing cassette and at least one pod. The mixing cassette is fluidly connected to the middle cassette by at least one fluid line and the middle cassette is fluidly connected to the balancing cassette by at least one fluid line. The at least one pod is connected to at least two of the cassettes wherein the pod is located in an area between the cassettes. | 2011-12-08 |
20110299359 | DISTRIBUTIVE AND DISPERSIVE MIXING APPARATUS OF THE CDDM TYPE, AND ITS USE - A distributive and dispersive mixing apparatus of the CDDM type comprising two confronting surfaces as being the inner surface of shell ( | 2011-12-08 |
20110299360 | SEISMIC ARRAY WITH SPACED SOURCES HAVING VARIABLE PRESSURE - An over/under seismic source system includes a first umbilical to a first gun array at a first depth and a second umbilical at a different air pressure to a second gun array at a second, lower depth. The air pressure to the second, lower gun array is tuned so that the periods of the gun bubbles from the higher and lower gun arrays match in order to improve wavefield separation in subsequent data processing. | 2011-12-08 |
20110299361 | APPARATUS AND METHOD FOR IMAGING SUBSURFACE STRUCTURE - The present invention relates to an imaging technique for modeling a subsurface structure through waveform inversion in the Laplace domain. According to the present invention, a source equivalent to the real source is calculated. The equivalent source is at least one source arranged on a virtual grid of the area to be measured, and the virtual grid has a large size which cannot be employed as the location of the real source in conventional techniques. The equivalent source has a vector obtained by multiplying an analytical solution vector and an impedance matrix of a Laplace domain wave equation, wherein said analytical solution vector is obtained from the analytical solution of a Laplace domain wave equation in a homogeneous half space by the real source. | 2011-12-08 |
20110299362 | Underwater camera communication system - An underwater communications system is provided that transmits electromagnetic and/or magnetic signals to a remote receiver. The transmitter includes a data input. A digital data compressor compresses data to be transmitted. A modulator modulates compressed data onto a carrier signal. An electrically insulated, magnetic coupled antenna transmits the compressed, modulated signals. The receiver that has an electrically insulated, magnetic coupled antenna for receiving a compressed, modulated signal. A demodulator is provided for demodulating the signal to reveal compressed data. A de-compressor de-compresses the data. An appropriate human interface is provided to present transmitted data into text/audio/visible form. Similarly, the transmit system comprises appropriate audio/visual/text entry mechanisms. | 2011-12-08 |
20110299363 | COMMUNICATIONS SYSTEM - An underwater communications system is provided that transmits electromagnetic and/or magnetic signals to a remote receiver. The transmitter includes a data input. A digital data compressor compresses data to be transmitted. A modulator modulates compressed data onto a carrier signal. An electrically insulated, magnetic coupled antenna transmits the compressed, modulated signals. The receiver that has an electrically insulated, magnetic coupled antenna for receiving a compressed, modulated signal. A demodulator is provided for demodulating the signal to reveal compressed data. A de-compressor de-compresses the data. An appropriate human interface is provided to present transmitted data into text/audio/visible form. Similarly, the transmit system comprises appropriate audio/visual/text entry mechanisms. | 2011-12-08 |
20110299364 | Diver Communication System - An underwater communications system is provided that transmits electromagnetic and/or magnetic signals to a remote receiver. The transmitter includes a data input. A digital data compressor compresses data to be transmitted. A modulator modulates compressed data onto a carrier signal. An electrically insulated, magnetic coupled antenna transmits the compressed, modulated signals. The receiver that has an electrically insulated, magnetic coupled antenna for receiving a compressed, modulated signal. A demodulator is provided for demodulating the signal to reveal compressed data. A de-compressor de-compresses the data. An appropriate human interface is provided to present transmitted data into text/audio/visible form. Similarly, the transmit system comprises appropriate audio/visual/text entry mechanisms. | 2011-12-08 |
20110299365 | TIMEPIECE HAVING A TIME INDICATOR HAND WHICH IS MOVABLE BETWEEN TWO POSITIONS - Timepiece having a timepiece movement and comprising a time indicator hand which can indicate a first piece of time information when in a first position, and a second piece of time information when in a second position; a first time indication moving part; and a second time indication moving part, in which the timepiece movement includes a first cam ( | 2011-12-08 |
20110299366 | UNIDIRECTIONAL COUPLING-CLUTCH RUNNER - A unidirectional coupling-clutch runner includes a coaxial pinion and wheel which pivot relative to one another. The runner includes a first driving part angularly integral with the pinion having at least one elastic catch with the general shape, in plan view, of a C, one branch of which is elongated and terminates with a free end; and a second driving part angularly integral with the wheel and which is coplanar with the first driving part having an internal wolf-toothing. In the neutral rest position the first and second driving parts do not touch one another, the end of the elastic catches in the rest position which are not elastically deformed being located on a circumference whose diameter is larger than a circumference which goes through the top of the wolf-teeth and smaller than a circumference going through the bottom of the toothing of the second driving part. | 2011-12-08 |
20110299367 | THERMALLY ASSISTED MAGNETIC RECORDING DEVICE - There is provided a thermally assisted magnetic recording device capable of preventing collision between a thermally assisted magnetic recording head and a disk due to thermal deformation of a near-field transducer. The thermally assisted magnetic recording device includes a temperature sensor for measuring the temperature in the vicinity of the near-field transducer, a table that stores the relationship between temperature and deformation in the vicinity of the near-field transducer, and a control unit. The control unit calculates the deformation in the vicinity of the near-field transducer, from the temperature measured by the temperature sensor and the relationship between temperature and deformation stored in the table. Then, the control unit drives the flying height control actuator according to the calculated deformation to control the distance between the thermally assisted magnetic recording and the disk in order to avoid contact between them. | 2011-12-08 |
20110299368 | SYSTEM FOR RECORDING DATA IN AN OPTICAL DISC - According to one embodiment, a system is provided for recording data in an optical disc having frames having different numbers. The system records data in each of the frames while writing synchronization information in each frame. The system is provided with an even/odd frame judgment unit, a synchronization information output unit, a synchronization information selection unit and a selection information output unit. The even/odd frame judgment unit judges whether the number of a frame having a land pre-pit is an even number or an odd number. The synchronization information output unit outputs plural pieces of synchronization information corresponding to different synchronization patterns. The synchronization information selection unit generates a selection signal for selecting one of the pieces of synchronization information to be written in each frame. The selection information output unit outputs the selected one of the pieces of synchronization information. | 2011-12-08 |
20110299369 | OPTICAL DISC DEVICE AND OPTICAL DISC RECORDING/REPRODUCING METHOD - There are provided an optical disc device and its recording/reproducing method for managing the management information about plural optical discs efficiently. In the present invention, the management information about the plural optical discs is stored in a memory. Moreover, the management information about part or all of the optical discs stored in the memory is recorded in the optical disc. | 2011-12-08 |
20110299370 | OPTICAL DISK APPARATUS - An optical disk apparatus according to the present invention includes: a controller | 2011-12-08 |
20110299371 | OPTICAL DISK DEVICE, OPTICAL DISK CONTROL METHOD, AND INTEGRATED CIRCUIT - To provide an optical disk device, an optical disk control method and an integrated circuit, which are capable of writing a recordable mark by changing the reflectance ratio of a reflective film formed on concave-convex pits without using an industrial special device or a high-power laser light source. A data reproduction controller ( | 2011-12-08 |
20110299372 | OPTICAL DRIVE - An optical drive according to the present invention can write information on an optical disc, which includes a substrate on which a number of pre-pits ( | 2011-12-08 |
20110299373 | APPARATUS HAVING SWITCHABLE SERVO GAINS AND OFFSETS FOR OPTICAL DISK DRIVE AND METHOD THEREOF - An apparatus having switchable servo gains and offsets for an optical disk drive adjusts its gains and offsets through the coupling of a servo signal and a switch with several changeable paths. The servo signals are either designated to undergo signal reduction with respect to a first offset through the switch and then be output after a first gain unit performed proportional conversion, or designated to undergo signal reduction with respect to a second offset and then be output after a second gain unit performed proportional conversion. The switch is switched on/off in the light of the working status of the pick-up head, for example, seeking or tracking, at a data area or at a blank area, and at a groove area or at a land area, so as to choose different offsets and gains to have the conversion of the servo signals. | 2011-12-08 |
20110299374 | MULTILAYER OPTICAL DISC - A multilayer optical disc which has three or more recording layers and enables easy positioning of a focused beam spot onto a particular recording layer in which a BCA is disposed. An inter-layer distance between a particular recording layer and a recording layer adjacent to the particular recording layer is larger than the other inter-layer distances in which, at the focused beam spot positioning, the focused beam spot traverses the said adjacent recording layer earlier than the other recording layer adjacent to the particular recording layer. | 2011-12-08 |
20110299375 | OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS - In a small-sized optical pickup device for enabling to obtain a stable servo-signal, as well as, a focus error signal and a tracking error signal, without receiving ill influences of stray lights from other layers, when recording/reproducing a multi-layer optical disc, a reflection light from the multi-layer optical disc is divided into plural numbers of regions by a diffraction grating. And, it is divided into at least four (4) regions, by a division line in the tangential direction of the optical disc and a division line in the radial direction thereof. Light receiving parts, for detecting either one of grating diffraction lights, i.e., a +1 | 2011-12-08 |
20110299376 | FORMING A VISIBLE LABEL ON AN OPTICAL DISC - A system, method, and medium for forming a visible label on an optical disc. Label data for a label track of the disc is received into a buffer of a disc drive. The label data is analyzed to identify the label track. A surface contour of the disc is mapped only near the label track. Focus actuator signals for the label track are derived using the surface contour. The label track is marked, with a laser of the disc drive, according to the label data while the laser is focusing the focus actuator signals. | 2011-12-08 |
20110299377 | LENS AND OPTICAL PICK-UP - A lens including: a lens body having first and second surfaces; a flange part formed to protrude from a periphery of the lens body and to have a cylindrical outer circumferential surface; a lens installation surface formed at an outer edge part of the flange part; a recessed part formed as a part of the flange part such that a part of the cylindrical outer circumferential surface is recessed toward the optical axis; and a gate root part located at a central part of the recessed part. The gate root part has a flat surface which is in a same level with respect to the lens installation surface. The gate root part lies on an optical axis side with respect to a virtual curved surface formed by extending the cylindrical outer circumferential surface through the recessed part. | 2011-12-08 |
20110299378 | Optical Pickup Having Radially Arranged Lenses in a Low Profile Construction - An optical pickup includes a first source which emits a first beam with a first wavelength; a second source which emits a second beam with a wavelength shorter than the first wavelength; a first collimate lens which collimates the first beam; a second collimate lens which collimates the second beam; a first objective lens which converges the first collimated beam onto an optical disc; and a second objective lens which converges the second collimated beam onto the disc. The first and second objective lenses are arranged in the disc radial direction. The second objective lens is arranged closer to the side of the disc outer circumference than the first objective lens. The first collimate lens is arranged on the right-hand side when the second objective lens is viewed from the first objective lens. The second collimate lens is arranged on the left-hand side when the first objective lens is viewed from the second objective lens. The gap between the first collimate lens and the first objective lens is larger than the gap between the second collimate lens and the second objective lens. | 2011-12-08 |