49th week of 2012 patent applcation highlights part 17 |
Patent application number | Title | Published |
20120305957 | SOLID STATE LIGHTING DEVICES HAVING SIDE REFLECTIVITY AND ASSOCIATED METHODS OF MANUFACTURE - Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies. | 2012-12-06 |
20120305958 | RED NITRIDE PHOSPHORS - Provided according to embodiments of the invention are phosphor compositions that include Ca | 2012-12-06 |
20120305959 | LIGHT-EMITTING DIODE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting diode (LED) device, includes a substrate, having a first and a second surfaces, a first bonding layer, disposed on the first surface, a first epitaxial structure, having a third and a fourth surfaces and comprising a first and a second groove, wherein the first epitaxial structure comprises a second electrical type semiconductor layer, an active layer and a first electrical type semiconductor layer sequentially stacked on the first bonding layer, and the first groove extends from the fourth surface to the first electrical type semiconductor layer via the active layer, the second groove extends from the fourth surface to the third surface, a first electrical type conductive branch, a first electrical type electrode layer, an insulating layer, filled in the first and the second grooves, and a second electrical type electrode layer, electrically connected to the second electrical type semiconductor layer. | 2012-12-06 |
20120305960 | LED PACKAGE AND METHOD FOR MAKING THE SAME - An LED package includes a substrate, an electrode structure, an LED die, a packaging portion, and a covering portion. The electrode structure is formed on the substrate. The LED die is mounted on the substrate, and electrically connected to the electrode structure. The packaging portion covers the LED die. The covering portion surrounds a periphery of the LED package and seals a joint between the substrate, the electrode structure and the packaging portion. The covering portion is made of silicone-titanate resin with reactive monomers, wherein the reactive monomers comprises more than 60% of heptane, 7.0% to 13.0% of allytrimethoxysilane, 5.0% to 10.0% of tetrabutyl titanate, and less than 0.1% of tetramethoxysilane. | 2012-12-06 |
20120305961 | LED DEVICE AND METHOD FOR MANUFACTURING THE SAME - An LED device comprises a substrate, an LED chip and a luminescent conversion layer. The substrate comprises a first electrode, a second electrode and a reflector located on top faces of the first and the second electrodes. The LED chip is disposed on the first electrode and electrically connected to the first and the second electrodes. The luminescent conversion layer is located inside the reflector and comprises a first luminescent conversion layer and a second luminescent conversion layer with different specific gravities. A manufacturing method for the LED device is also provided. | 2012-12-06 |
20120305962 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - A light emitting device package is disclosed. The light emitting device package includes a light emitting device disposed on a first lead frame, the light emitting device having an electrode pad on an upper surface thereof, a first wire to electrically interconnect a second lead frame spaced apart from the first lead frame and the electrode pad, and a first bonding ball disposed on the second lead frame, the first bonding ball spaced apart from a first contact point, which is in contact with the first wire and the second lead frame, wherein the first bonding ball is disposed between the first wire and the second lead frame to electrically interconnect the first wire and the second lead frame. | 2012-12-06 |
20120305963 | LIGHT-EMITTING DEVICE AND LUMINAIRE - According to one embodiment, a light-emitting device includes a substrate, a reflecting layer formed on the substrate, a light-emitting element placed on the reflecting layer, and a sealing resin layer that covers the reflecting layer and the light-emitting element. The oxygen permeability of the sealing resin layer is equal to or lower than 1200 cm | 2012-12-06 |
20120305964 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting element includes a light emitting element includes a semiconductor stacked body including a light emitting layer, a reflection layer, a support substrate, a first bonding electrode and a second bonding electrode. The reflection layer is made of a metal and has a first surface and a second surface opposite to the first surface. The semiconductor stacked body is provided on a side of the first surface of the reflection layer. The first bonding electrode is provided between the second surface and the support substrate and includes a convex portion projected toward the support substrate and a bottom portion provided around the convex portion in plan view. The second bonding electrode includes a concave portion fitted in the convex portion of the first bonding electrode and is capable of bonding the support substrate and the first bonding electrode. | 2012-12-06 |
20120305965 | LIGHT EMITTING DIODE SUBSTRATE AND LIGHT EMITTING DIODE - A light emitting diode (LED) substrate includes a sapphire substrate which is characterized by having a surface consisting of irregular hexagonal pyramid structures, wherein a pitch of the irregular hexagonal pyramid structure is less than 10 μm. A symmetrical cross-sectional plane of each of the irregular hexagonal pyramid structures has a first base angle and a second base angle, wherein the second base angle is larger than the first base angle, and the second base angle is 50° to 70°. This LED substrate has high light-emitting efficiency. | 2012-12-06 |
20120305966 | ORGANIC LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME - Provided are an organic light emitting diode and a method of fabricating the same. The organic light emitting diode may include a light-scattering layer, a first electrode, an organic light-emitting layer, and a second electrode, which are sequentially stacked on a substrate, wherein the light-scattering layer may include uneven shaped nanostructures having irregular width and spacing. The method of fabricating the organic light emitting diode may include sequentially stacking a light-scattering medium layer and a metal alloy layer on a substrate, heat treating the metal alloy layer to form etching mask patterns, etching the light-scattering medium layer by using the etching mask patterns to form a light-scattering layer, removing the etching mask patterns, and forming a planarizing layer on the light-scattering layer. | 2012-12-06 |
20120305967 | Flip Chip Type Light Emitting Diode and Manufacturing Method Thereof - The present disclosure provides a flip chip type light emitting diode which comprises a substrate and a light emitting diode chip. The substrate comprises a body, a plurality of third pads, a fourth pad, a first electrode, a second electrode, a plurality of first vias, and a second via. The body has a first surface and a second surface opposite to the first surface. The third pads and the fourth pad are disposed on the first surface of the body. The first electrode and the second electrode are disposed on the second surface of the body. The first vias traverse through the body and are each electrically coupled to a respective one of the third pads and the first electrode. The second via traverses through the body and is electrically coupled to the fourth pad and the second electrode. | 2012-12-06 |
20120305968 | LIGHT EMITTING DEVICE - Provided is a light emitting device that can suppress variation in a resonance frequency of a mode, so that light emission can be enhanced at high efficiency even in a case where photonic crystal, in which defect cavities are periodically arranged, is used. The light emitting device includes: an active layer; a photonic crystal layer including defects introduced therein, the defects disturbing periodicity of a refractive index distribution of photonic crystal; and a cladding layer having a refractive index lower than an effective refractive index of the photonic crystal layer, in which the defects are used as defect cavities. The photonic crystal layer has a structure in which the defect cavities are arranged. Each of the defect cavities has a major axis and a minor axis having different axial lengths, and the major axes are directed in different directions between neighboring defect cavities. | 2012-12-06 |
20120305969 | REFLECTING MATERIAL AND LIGHT EMITTING DIODE DEVICE - A reflecting material contains a silicone resin composition prepared from a polysiloxane containing silanol groups at both ends, an ethylenic silicon compound, a silicon compound containing an epoxy group, an organohydrogenpolysiloxane, a condensation catalyst, and an addition catalyst; and a light reflecting component. | 2012-12-06 |
20120305970 | LIGHT EMITTING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - There is provided a light emitting device package including a substrate having a cavity therein; alight emitting device mounted on a bottom surface of the cavity; a first wavelength conversion part including a first phosphor for a wavelength conversion of light emitted from the light emitting device and covering the light emitting device within the cavity; and a second wavelength conversion part including a second phosphor allowing for emission of light having a wavelength different to that of the first phosphor and formed as a sheet on the first wavelength conversion part. | 2012-12-06 |
20120305971 | LIGHT EMITTING DEVICE LENS, LIGHT EMITTING DEVICE MODULE INCLUDING LIGHT EMITTING DEVICE LENS AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE MODULE USING LIGHT EMITTING DEVICE LENS - A lens according to an embodiment of the present invention may include a first depression and a second depression having predetermined patterns in a lower portion of the lens, and a phosphor layer and the lens may be collectively formed by disposing the lens after spraying a phosphor rather than separately forming the phosphor on the LED chip during a manufacture of the LED module. Accordingly, a production tolerance, and the like of an LED module may be removed to improve yield, and a manufacturing process of the LED module may be simplified. A lens may have an upper portion formed in advance in one of a hemispherical shape, an oval shape, and a batwing shape having a concave central portion, thereby implementing a customized lens according to a predetermined application. | 2012-12-06 |
20120305972 | LIGHT EMITTING DIODE DEVICE WITH LUMINESCENT MATERIAL - The invention provides a light emitting diode device comprising a light emitting diode arranged on a substrate and a wavelength converting element. The wavelength converting element contains a luminescent material a Mn | 2012-12-06 |
20120305973 | LIGHT-EMITTING DEVICE AND SURFACE LIGHT SOURCE DEVICE USING THE SAME - To provide a light emitting device which emits high-luminance, uniform white light with reduced variations in luminance, a light emitting element | 2012-12-06 |
20120305974 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device comprises a first nitride semiconductor layer comprising a flat top surface and a plurality of concave regions from the flat top surface, a reflector within the concave regions of the first semiconductor layer, and a second semiconductor layer on the first semiconductor layer. | 2012-12-06 |
20120305975 | Dissipation Module For A Light Emitting Device And Light Emitting Diode Device Having The Same - A light emitting diode device is provided. The light emitting diode device comprises a composite substrate and a light emitting diode disposed on the composite substrate. The composite substrate comprises a first carbon fiber composite layer which is able to conduct heat rapidly in the direction of carbon fiber, such that the heat generated from the light emitting diode module can be dissipated rapidly. | 2012-12-06 |
20120305976 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - A light emitting device package is disclosed. The light emitting device package includes a body, first and second lead frames disposed on the body, and a light emitting device connected to the first and second lead frames, wherein at least one of the first and second lead frames includes first and second regions having different thicknesses. | 2012-12-06 |
20120305977 | INTERPOSER AND MANUFACTURING METHOD THEREOF - An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer. | 2012-12-06 |
20120305978 | LED LAMPS - A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to blue region that is close to that of daylight. Also, the chip pair can be used to provide an RGB lamp or a red-amber-green traffic lamp. The active regions of both chips can be less than 50 microns away from a heat sink. | 2012-12-06 |
20120305979 | LIGHT-EMITTING DIODE, METHOD FOR MANUFACTURING THE SAME, AND LIGHT-EMITTING DIODE LAMP - The present invention provides a light-emitting diode that includes two electrodes provided on a light-emitting surface, and exhibits high light extraction efficiency and high-brightness. The present invention relates to a light-emitting diode ( | 2012-12-06 |
20120305980 | LED LAMPS - A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to blue region that is close to that of daylight. Also, the chip pair can be used to provide an RGB lamp or a red-amber-green traffic lamp. The active regions of both chips can be less than 50 microns away from a heat sink. | 2012-12-06 |
20120305981 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - A method of manufacturing an OLED display includes: forming an organic light emitting element on a first substrate; forming, on the organic light emitting element, a thin film encapsulation layer that seals the organic light emitting element with the first substrate; providing a second substrate; forming a flexible protection layer on the second substrate; attaching the first substrate and the second substrate to each other; and separating the second substrate from the flexible protection layer. | 2012-12-06 |
20120305982 | OPTICAL SEMICONDUCTOR SEALING MATERIAL - The present invention provides an optical semiconductor sealing material comprising a radically polymerized polymer of a methacrylate ester having an alicyclic hydrocarbon group containing 7 or more carbon atoms, e.g. an adamantyl group, a norbornyl group, or a dicyclopentanyl group; and an optical semiconductor sealing material comprising a radically polymerized polymer of 50 to 97 mass % of the methacrylate ester and 3 to 50 mass % of acrylate ester having a hydroxyl group. The optical semiconductor sealing material of the present invention is highly transparent and stable to UV light and thus does not undergo yellowing. In addition, the material exhibits excellent compatibility between heat resistance and refractive index, does not undergo deformation or cracking during heating processes such as reflow soldering, and shows high processability. The material can be preferably used as a sealing material for light-emitting elements and light-receiving elements of optical semiconductor devices (semiconductor light-emitting devices). | 2012-12-06 |
20120305983 | METHOD FOR PRODUCING GROUP-III NITRIDE SEMICONDUCTOR CRYSTAL, GROUP-III NITRIDE SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR LIGHT EMITTING DEVICE - The method for producing a group III nitride semiconductor crystal comprises preparing a seed crystal having a non-polar plane followed by growing a group III nitride semiconductor from the non-polar plane in a vapor phase, wherein the growing includes growing the group III nitride semiconductor so as to extend in the +C-axis direction of the seed crystal. A group III-V nitride semiconductor crystal having high quality and a large-area non-polar plane can be obtained by the method. | 2012-12-06 |
20120305984 | SCR/MOS CLAMP FOR ESD PROTECTION OF INTEGRATED CIRCUITS - An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad. | 2012-12-06 |
20120305985 | POWER SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF TRENCH IGBTS - A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures. | 2012-12-06 |
20120305986 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a wafer; a plurality of convex structures formed on the wafer, in which every two adjacent convex structures are separated by a cavity in a predetermined pattern and arranged in an array, and the cavity between every two adjacent convex structures is less than 50 nm in width; and a first semiconductor film formed on the plurality of convex structures, in which a part of the first semiconductor film is spaced apart from the wafer. | 2012-12-06 |
20120305987 | LATERAL TRENCH MESFET - A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench. | 2012-12-06 |
20120305988 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate; a plurality of convex structures formed on the substrate, in which every two adjacent convex structures are separated by a cavity; a plurality of floated films, in which each floated film is formed between the every two adjacent convex structures and connected with tops of the every two adjacent convex structures, the floated films are partitioned into a plurality of sets, a channel layer is formed on a convex structure between the floated films in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and an isolation portion is set between two adjacent sets of floated films; and a gate stack formed on each channel layer. | 2012-12-06 |
20120305989 | METHOD TO PREVENT SURFACE DECOMPOSITION OF III-V COMPOUND SEMICONDUCTORS - A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor. | 2012-12-06 |
20120305990 | METHODS AND APPARATUS TO REDUCE LAYOUT BASED STRAIN VARIATIONS IN NON-PLANAR TRANSISTOR STRUCTURES - The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming isolation structures in strained semiconductor bodies of non-planar transistors while maintaining strain in the semiconductor bodies. | 2012-12-06 |
20120305991 | DEVICE HAVING SERIES-CONNECTED HIGH ELECTRON MOBILITY TRANSISTORS AND MANUFACTURING METHOD THEREOF - A manufacturing method of a device having series-connected HEMTs is presented. Transistors are formed on a substrate and integratedly serial-connected as an integrated device by interconnection wires. Therefore, the voltage of the device is the sum of the voltages across each transistors so that the device can have high breakdown voltage. | 2012-12-06 |
20120305992 | HYBRID MONOLITHIC INTEGRATION - The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the contamination issues related to the integration of different technologies, maintaining at the same time a good planarization of the structure. It further simplifies the fabrication process, allowing the growth of high quality III-V materials on (100) silicon substrates lowering the manufacturing cost. Moreover, differently from many prior art attempts, it does not require silicon on insulator technologies and/or other expensive process steps. This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices. | 2012-12-06 |
20120305993 | TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS - A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device. | 2012-12-06 |
20120305994 | SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING - Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide. | 2012-12-06 |
20120305995 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER - In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process. | 2012-12-06 |
20120305996 | SEMICONDUCTOR DEVICE - An area occupied by a circuit element having at least a capacitor and a transistor is reduced in a semiconductor device. In a semiconductor device including a first transistor, a second transistor, and a capacitor, the first transistor and the capacitor are provided over the second transistor. Then, a common electrode, which serves as one of a source and a drain of the first transistor and one electrode of the capacitor, is provided. In addition, the other electrode of the capacitor is provided over the common electrode. | 2012-12-06 |
20120305997 | Semiconductor Devices Having Recessed Channels - A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided. | 2012-12-06 |
20120305998 | HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY - In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array. | 2012-12-06 |
20120305999 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device capable of increasing an ON current with a reduced channel resistance, and also capable of stably and independently operating respective transistors, and a method of manufacturing the semiconductor device. A semiconductor device includes a fin portion located in a manner that a part of an active region protrudes from a bottom portion of a gate groove, a gate insulating film for covering the gate groove and a surface of the fin portion, a gate electrode which is embedded within a lower portion of the gate groove and formed so as to straddle the fin portion via the gate insulating film, a first diffusion region, a second diffusion region, and a carrier capture region provided in the surface of the fin portion. | 2012-12-06 |
20120306000 | Formation of Field Effect Transistor Devices - A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks. | 2012-12-06 |
20120306001 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. | 2012-12-06 |
20120306002 | ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF - This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate. | 2012-12-06 |
20120306003 | TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS - Disclosed is a MOSFET including at least one transistor cell. The at least one transistor cell includes a source region, a drain region, a body region and a drift region. The body region is arranged between the source region and the drift region and the drift region is arranged between the body region and the drain region. The at least one transistor cell further includes a compensation region arranged in the drift region and distant to the body region, a source electrode electrically contacting the source region and the body region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a coupling arrangement including a control terminal. The coupling arrangement is configured to electrically couple the compensation region to at least one of the body region, the source region, the source electrode and the gate electrode dependent on a control signal received at the control terminal. | 2012-12-06 |
20120306004 | SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor. | 2012-12-06 |
20120306005 | Trough channel transistor and methods for making the same - The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough. Regions of the semiconductor trough not directly beneath the gate electrode have a second conductivity type opposite to the first conductivity type provided in the substrate. | 2012-12-06 |
20120306006 | SEMICONDUCTOR POWER DEVICE - A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer. | 2012-12-06 |
20120306007 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface. | 2012-12-06 |
20120306008 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device. | 2012-12-06 |
20120306009 | INTEGRATION OF SUPERJUNCTION MOSFET AND DIODE - A semiconductor structure comprises a semiconductor layer of a first conductivity type, trenches extending into the semiconductor layer, and a conductive layer of a second conductivity type lining sidewalls and bottom of each trench and forming PN junctions with the semiconductor layer. A first plurality of the trenches are disposed in a field effect transistor region that comprises a body region of the first conductivity type, source regions of the second conductivity type in the body region, and gate electrodes isolated from the body region and the source regions by a gate dielectric. A second plurality of the trenches are disposed in a Schottky region that comprises a conductive material contacting mesa surfaces of the semiconductor layer between adjacent ones of the second plurality of the trenches to form Schottky contacts. The conductive material also contacts the conductive layer proximate an upper portion of the second plurality of the trenches. | 2012-12-06 |
20120306010 | DMOS TRANSISTOR HAVING AN INCREASED BREAKDOWN VOLTAGE AND METHOD FOR PRODUCTION - A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material. | 2012-12-06 |
20120306011 | Integrated Circuit With A Laterally Diffused Metal Oxide Semiconductor Device And Method Of Forming The Same - An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain. | 2012-12-06 |
20120306012 | Power Integrated Circuit Device With Incorporated Sense FET - In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET. | 2012-12-06 |
20120306013 | METAL OXIDE SEMICONDUCTOR OUTPUT CIRCUITS AND METHODS OF FORMING THE SAME - Metal oxide semiconductor (MOS) protection circuits and methods of forming the same are disclosed. In one embodiment, an integrated circuit includes a pad, a p-type MOS (PMOS) transistor, and first and second n-type MOS (NMOS) transistors. The first NMOS transistor includes a drain, a source and a gate electrically connected to the pad, a first supply voltage, and a drain of the PMOS transistor, respectively. The second NMOS transistor includes a gate, a drain, and a source electrically connected to a bias node, a second supply voltage, and a source of the PMOS transistor, respectively. The source of the second NMOS transistor is further electrically connected to a body of the PMOS transistor so as to prevent a current flowing from the drain of the PMOS transistor to the second supply voltage through the body of PMOS transistor when a transient signal event is received on the pad. | 2012-12-06 |
20120306014 | STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE - A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate. | 2012-12-06 |
20120306015 | CONTACTS FOR FET DEVICES - A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface. | 2012-12-06 |
20120306016 | DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE - A method includes forming a plurality of trenches in a pad film to form raised portions, and depositing a hard mask in the trenches and over the upper pad film. The method includes forming a plurality of fins including the raised portions and a second plurality of fins including the hard mask deposited in the trenches, each of which are separated by a deep trench. The method includes removing the hard mask on the plurality of fins including the raised portions and the second plurality of fins resulting in a dual height fin array. The method includes forming gate electrodes within each deep trench between each fin of the dual height fin array, burying the second plurality of fins and abutting sides of the plurality of fins including the raised portions. The plurality of fins including the raised portions electrically and physically isolate adjacent gate electrode of the gate electrodes. | 2012-12-06 |
20120306017 | WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS - An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET). | 2012-12-06 |
20120306018 | BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH - A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer. | 2012-12-06 |
20120306019 | FABRICATION OF DEVICES HAVING DIFFERENT INTERFACIAL OXIDE THICKNESS VIA LATERAL OXIDATION - A semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET. | 2012-12-06 |
20120306020 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them. | 2012-12-06 |
20120306021 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device is provided that includes a first pair of P channel field effect transistors (PFET) with a common source connected to a voltage contact and a gate connected to a drain of the other PFET and a pair of N channel field effect transistors (NFET) sized smaller than the first pair of PFETs with a drain connected to the drain of the respective PFET of the first pair of PFETs, a common source connected to a ground contact, and a gate connected to the drain of an opposite PFET of the first pair of PFETs. Additionally, a second pair of PFETs sized larger than the NFETs and approximately one-half that of the first pair of PFETS, each of the second pair of PFETs having a drain respectively coupled to a connection linking the respective drain of the NFET of the pair of NFETs to the drain of the PFET of the first pair of PFETs. Complementary bit lines are included, each of the complementary bit lines respectively connected to a source of the second pair of PFETs. Finally, a word line connected to a gate of each of the second pair of PFETs. A method for forming the semiconductor device is also disclosed. | 2012-12-06 |
20120306022 | Metal oxide semiconductor transistor layout with higher effective channel width and higher component density - The disclosure is a metal oxide semiconductor transistor layout with higher effective channel width and higher component density. The layout discloses a common drain region with straight cross pattern, a plurality of common drain regions with lattice pattern, a common source region with straight cross pattern, a plurality of common source regions with lattice pattern, a hybrid grating with common drain region with straight cross pattern and common source region with straight cross pattern. The layout can increase the component density and the effective channel width as compared to conventional layout. The invention is further with the advantages of lower cost and can be operated in higher power. | 2012-12-06 |
20120306023 | Device-Manufacturing Scheme for Increasing the Density of Metal Patterns in Inter-Layer Dielectrics - A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process. | 2012-12-06 |
20120306024 | Scalable Construction for Lateral Semiconductor Components having High Current-Carrying Capacity - The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode ( | 2012-12-06 |
20120306025 | Integrated Circuit Including Cross-Coupled Transistors with Two Transistors of Different Type Having Gate Electrodes Formed by Common Gate Level Feature with Shared Diffusion Regions on Opposite Sides of Common Gate Level Feature - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration. | 2012-12-06 |
20120306026 | REPLACEMENT GATE ELECTRODE WITH A TUNGSTEN DIFFUSION BARRIER LAYER - A tungsten barrier portion is employed in a replacement gate structure to block diffusion of material from a metal portion to a work function material portion. The tungsten barrier portion effectively functions as a diffusion barrier layer between the metal portion and the work function material portion so that the composition of the work function material portion is unaffected by anneal and/or usage of the field effect transistor including the replacement gate structure. Thus, the threshold voltage of the field effect transistor can remain stable throughout processing steps and usage in the field. | 2012-12-06 |
20120306027 | TRANSISTORS WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES PROVIDED BY AN OXIDIZING ETCH PROCESS - When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like. | 2012-12-06 |
20120306028 | SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF - A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided. | 2012-12-06 |
20120306029 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator. | 2012-12-06 |
20120306030 | BALANCING A MICROELECTROMECHANICAL SYSTEM - A method of balancing a microelectromechanical system comprises determining if a microelectromechanical system is balanced in a plurality of orthogonal dimensions, and if the microelectromechanical system is not balanced, selectively depositing a first volume of jettable material on a portion of the microelectromechanical system to balance the microelectromechanical system in the plurality of orthogonal dimensions. A jettable material for balancing a microelectromechanical system comprises a vehicle, and a dispersion of nano-particles within the vehicle, in which the total mass of jettable material deposited on the microelectromechanical system is equal to the weight percentage of nano-particles dispersed within the vehicle multiplied by the mass of jettable material deposited on the microelectromechanical system. A microelectromechanical system comprises a number of unbalanced structures, and a number of droplets of jettable material disposed on the unbalanced structures, in which the droplets of jettable material balance the unbalanced structures in a plurality of orthogonal dimensions. | 2012-12-06 |
20120306031 | SEMICONDUCTOR SENSOR DEVICE AND METHOD OF PACKAGING SAME - A semiconductor sensor die is packaged with a footed lid that has side walls and a top portion with a central hole. Gel material is dispensed into a cavity formed by the side walls such that it covers the die prior to attaching the lid top portion. | 2012-12-06 |
20120306032 | METHOD OF BONDING SEMICONDUCTOR SUBSTRATE AND MEMS DEVICE - Disclosed is a method for bonding semiconductor substrates, wherein an eutectic alloy does run off the bonding surfaces during the eutectic bonding. Also disclosed is an MEMS device which is obtained by bonding semiconductor substrates by this method. Specifically, a substrate ( | 2012-12-06 |
20120306033 | VIALESS MEMORY STRUCTURE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via. | 2012-12-06 |
20120306034 | Magnetoresistive Device - A magnetoresistive device having a magnetic junction including a first fixed magnetic layer structure, a second fixed magnetic layer structure, and a free magnetic layer structure, wherein the first second and free magnetic layer structures are arranged one over the other. The first second and free magnetic layer structures have respective magnetization orientations configured to orient in a direction at least substantially perpendicular to a plane defined by an interface between the free magnetic layer structure and either one of the first fixed magnetic layer structure or the second fixed magnetic layer structure. The respective magnetization orientations of the first and the second fixed magnetic layer structures are oriented anti-parallel to each other, and the first fixed magnetic layer structure is a static fixed magnetic layer structure having a switching field that is larger than a switching field of the free magnetic layer structure. | 2012-12-06 |
20120306035 | PROCESS FOR FABRICATING A BACKSIDE-ILLUMINATED IMAGING DEVICE AND CORRESPONDING DEVICE - An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material. | 2012-12-06 |
20120306036 | FLIP-CHIP PHOTODIODE - A photodiode is provided according to various embodiments. In some embodiments, the photodiode includes a substrate and an active region. The active region is configured to receive light through the substrate. In such a configuration, the substrate not only participates in the photodiode operation acts as a light filter depending on the substrate material. In some embodiments, the active region may include solder balls that may be used to couple the photodiode to a printed circuit board. In some embodiments, the active region is coupled face-to-face with the printed circuit board. | 2012-12-06 |
20120306037 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD - A photoelectric conversion device is provided which is capable of improving the light condensation efficiency without substantially decreasing the sensitivity. The photoelectric conversion device has a first pattern provided above an element isolation region formed between adjacent two photoelectric conversion elements, a second pattern provided above the element isolation region and above the first pattern, and microlenses provided above the photoelectric conversion elements with the first and the second patterns provided therebetween. The photoelectric conversion device further has convex-shaped interlayer lenses in optical paths between the photoelectric conversion elements and the microlenses, the peak of each convex shape projecting in the direction from the electro-optical element to the microlens. | 2012-12-06 |
20120306038 | Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region - A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias. | 2012-12-06 |
20120306039 | SUB-PIXEL NBN DETECTOR - A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area. | 2012-12-06 |
20120306040 | INSULATING METAL SUBSTRATE AND SEMICONDUCTOR DEVICE - An insulating metal substrate is used for a semiconductor device such as a solar cell. The substrate includes a metal base made of steel, iron-based alloy steel or titanium, an aluminum layer and an insulating layer obtained by anodizing aluminum. An alloy layer primarily made of an alloy of a composition expressed by Al | 2012-12-06 |
20120306041 | DETECTION DEVICE MANUFACTURING METHOD, DETECTION DEVICE, AND DETECTION SYSTEM - In a method of manufacturing a detection device including pixels on a substrate, each pixel including a switch element and a conversion element including an impurity semiconductor layer on an electrode, which is disposed above the switch element and isolated per pixel, the switch element and the electrode being connected in a contact hole formed in a protection layer and an interlayer insulating layer, which are disposed between the switch elements and the electrodes, the method includes forming insulating members over the interlayer insulating layer between the electrodes in contact with the interlayer insulating layer, forming an impurity semiconductor film covering the insulating members and the electrodes, and forming a coating layer covering an area of the protection layer where an orthographically-projected image of a portion of the electrode is positioned, the portion including a level difference within the contact hole. | 2012-12-06 |
20120306042 | MgS Solar-Blind UV Radiation Detector - A UV detector is designed to provide a photoresponse with a cutoff wavelength below a predetermined wavelength. The detector uses a sensor element having an active layer comprising a MgS component grown directly on a substrate. A thin layer metal layer is deposited over the active layer and forms a transparent Schottky metal layer. | 2012-12-06 |
20120306043 | JUNCTION BARRIER SCHOTTKY (JBS) WITH FLOATING ISLANDS - A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench. | 2012-12-06 |
20120306044 | Edge termination configurations for high voltage semiconductor power devices - This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench. | 2012-12-06 |
20120306045 | Active Tiling Placement for Improved Latch-Up Immunity - A semiconductor device includes CMP dummy tiles ( | 2012-12-06 |
20120306046 | Power Semiconductor Device with High Blocking Voltage Capacity - A power semiconductor device includes an active device region disposed in a semiconductor substrate, an edge termination region disposed in the semiconductor substrate between the active device region and a lateral edge of the semiconductor substrate and a trench disposed in the edge termination region which extends from a first surface of the semiconductor substrate toward a second opposing surface of the semiconductor substrate. The trench has an inner sidewall, an outer sidewall and a bottom. The inner sidewall is spaced further from the lateral edge of the semiconductor substrate than the outer sidewall, and an upper portion of the outer sidewall is doped opposite as the inner sidewall and bottom of the trench to increase the blocking voltage capacity. Other structures can be provided which yield a high blocking voltage capacity such as a second trench or a region of chalcogen dopant atoms disposed in the edge termination region. | 2012-12-06 |
20120306047 | CHIP-ON-FILM STRUCTURE FOR LIQUID CRYSTAL PANEL - The present invention provides a chip on film (COF) structure for a liquid crystal panel, which is disposed on an edge of a glass substrate of an array substrate of a liquid crystal panel. The COF structure comprises a plastic substrate, a metal layer, an adhesive layer, a driver chip and an insulating protection layer. The COF structures further comprises at least one groove, and the groove is disposed on the plastic substrate over the output terminals of the metal layer. The at least one groove of the present invention can prevent from deformation and damage of the glass substrate when the COF structure is assembled with the glass substrate of the array substrate, and it can reduce the brightness difference of the glass substrate in the thermally pressed regions. | 2012-12-06 |
20120306048 | ELECTRICALLY PROGRAMMABLE METAL FUSE - A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming. | 2012-12-06 |
20120306049 | METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE - A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material. | 2012-12-06 |
20120306050 | METHOD FOR IMPROVING PROMPT DOSE RADIATION RESPONSE OF MIXED-SIGNAL INTEGRATED CIRCUITS - A system and method for improving the prompt dose radiation response of mixed-signal integrated circuits is disclosed. An internal analog circuit inside a mixed-signal integrated circuit generates an internal analog reference voltage that has been used for various purposes in the integrated circuit. At least one external capacitor is added either internal or external to a device package of the integrated circuit. The external capacitor reduces any change in the internal reference voltage due to prompt dose radiation by stabilizing the internal reference voltage and thus improves prompt dose radiation response of mixed-signal integrated circuits. A much greater value of capacitance may be provided without increase in dielectric rupture suceptability or decrease in manufacturing yield which may be associated with added on-chip capacitance. This increased capacitance primarily reduce the amount of disturbance caused to the internal node during a prompt dose radiation event. | 2012-12-06 |
20120306051 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTORING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode. | 2012-12-06 |
20120306052 | SILICON WAFER AND METHOD OF MANUFACTURING THEREOF, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object of the present invention is to provide an epitaxial wafer on which dislocation is preventable even when a LSA treatment is performed in device processes. An epitaxial wafer according to the present invention includes a wafer | 2012-12-06 |
20120306053 | SOLUTION-BASED SYNTHESIS OF CsSnI3 - This invention discloses a solution-based synthesis of cesium tin tri-iodide (CsSnI | 2012-12-06 |
20120306054 | METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE - A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium. | 2012-12-06 |
20120306055 | METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE - A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium. | 2012-12-06 |
20120306056 | Semiconductor wafer and method of producing the same - A semiconductor wafer ( | 2012-12-06 |