49th week of 2013 patent applcation highlights part 53 |
Patent application number | Title | Published |
20130323873 | OPTICALLY TRIGGERED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME - A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body. | 2013-12-05 |
20130323874 | MANUFACTURE OF SOLAR CELL MODULE - A solar cell module is manufactured by coating and curing a curable silicone gel composition onto one surface of each of two panels except a peripheral region to form a cured silicone gel coating, providing a seal member ( | 2013-12-05 |
20130323875 | Methods of forming a through via structure - Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors. | 2013-12-05 |
20130323876 | IMAGE DEVICE AND METHODS OF FORMING THE SAME - A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region. A first patterned mask layer is formed over the pixel region to expose the periphery region. A plurality of first trenches is etched into the substrate in the periphery region. Each first trench, each first opening and each second opening are filled with a dielectric material. A second patterned mask layer is formed over the periphery region to expose the pixel region. The dielectric material in each second opening over the pixel region is removed. A plurality of dopants is implanted through each second opening to form various doped isolation features in the pixel region. | 2013-12-05 |
20130323877 | METHODOLOGY FOR FORMING PNICTIDE COMPOSITIONS SUITABLE FOR USE IN MICROELECTRONIC DEVICES - The present invention provides methods for making pnictide compositions, particularly photoactive and/or semiconductive pnictides. In many embodiments, these compositions are in the form of thin films grown on a wide range of suitable substrates to be incorporated into a wide range of microelectronic devices, including photovoltaic devices, photodetectors, light emitting diodes, betavoltaic devices, thermoelectric devices, transistors, other optoelectronic devices, and the like. As an overview, the present invention prepares these compositions from suitable source compounds in which a vapor flux is derived from a source compound in a first processing zone, the vapor flux is treated in a second processing zone distinct from the first processing zone, and then the treated vapor flux, optionally in combination with one or more other ingredients, is used to grow pnictide films on a suitable substrate. | 2013-12-05 |
20130323878 | LIQUID PRECURSOR INKS FOR DEPOSITION OF IN-SE, GA-SE AND IN-GA-SE - An ink includes a solution of selenium in ethylene diamine solvent and a solution of at least one metal salt selected from the group consisting of an indium salt or a gallium salt in at least one solvent including an organic amide. The organic amide can include dimethylformamide. The organic amide can include N-methylpyrrolidone. | 2013-12-05 |
20130323879 | COATING METHOD, AND METHOD OF FORMING ORGANIC LAYER USING THE SAME - A coating apparatus includes a stage supporting a coating target, a coating part on the stage, the coating part being configured to apply a coating material onto the coating target, and a heating source opposite to and spaced apart from the stage, the heating source being configured to supply heat to the coating target after application of the coating material onto the coating target. | 2013-12-05 |
20130323880 | PROCESS AND MATERIALS FOR MAKING CONTAINED LAYERS AND DEVICES MADE WITH SAME - There is provided a process for forming a contained second layer over a first layer, including the steps: forming the first layer having a first surface energy; treating the first layer with a priming material to form a priming layer; exposing the priming layer patternwise with radiation resulting in exposed areas and unexposed areas; developing the priming layer to effectively remove the priming layer from the unexposed areas resulting in a first layer having a pattern of developed priming layer, wherein the pattern of developed priming layer has a second surface energy that is higher than the first surface energy; and forming the second layer by liquid depositions on the pattern of developed priming layer on the first layer. The priming material has at least one unit of Formula I | 2013-12-05 |
20130323881 | VAPOR DEPOSITION DEVICE, VAPOR DEPOSITION METHOD, AND ORGANIC EL DISPLAY DEVICE - Vapor deposition particles ( | 2013-12-05 |
20130323882 | VAPOR DEPOSITION PARTICLE EMITTING DEVICE, VAPOR DEPOSITION APPARATUS, VAPOR DEPOSITION METHOD - A vapor deposition particle injection device ( | 2013-12-05 |
20130323883 | DEVICE WITH THROUGH-SILICON VIA (TSV) AND METHOD OF FORMING THE SAME - A method includes forming an opening extending from a top surface of a silicon substrate into the silicon substrate to a predetermined depth. The method further includes forming an insulation structure on the silicon substrate along the sidewalls and the bottom of the opening and forming a conductive layer on the insulation structure to fill the opening. A first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm. | 2013-12-05 |
20130323884 | THREE DIMENSIONAL MICROELECTRONIC COMPONENTS AND FABRICATION METHODS FOR SAME - Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer. | 2013-12-05 |
20130323885 | METHOD OF MANUFACTURING HIGH-CAPACITY SEMICONDUCTOR PACKAGE - A method of manufacturing a high-capacity semiconductor package includes preparing a leadframe not comprising a chip mount area and comprising only a lead on a tape; attaching an interposer on a center area of the leadframe; stacking semiconductor chips stepwise on a first surface of the interposer; performing a first wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; performing a first molding process so as to encapsulate a top surface of the leadframe, the semiconductor chips, and wires; detaching a tape from the leadframe and turning the leadframe on which the first molding process has been performed upside down; stacking semiconductor chips on a second surface of the interposer; performing a second wire bonding process so as to connect the semiconductor chips, the lead, and the interposer; and performing a second molding process so as to encapsulate a bottom surface of the leadframe, the semiconductor chips, and wires. | 2013-12-05 |
20130323886 | Semiconductor Molding Chamber - A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. | 2013-12-05 |
20130323887 | Thyristor-Based Memory Cells, Devices and Systems Including the Same and Methods for Forming the Same - Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F | 2013-12-05 |
20130323888 | PROCESS FOR FABRICATING A TRANSISTOR COMPRISING NANOSCALE SEMICONDUCTOR FEATURES USING BLOCK COPOLYMERS - A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features. | 2013-12-05 |
20130323889 | METHOD OF FABRICATING PIXEL STRUCTURE - The present invention provides a pixel structure including a substrate, a patterned electrode disposed on the substrate, a first insulating layer disposed on the patterned electrode, a common electrode disposed on the first insulating layer, a second insulating layer disposed on the common electrode, and a drain disposed on the second insulating layer. The first insulating layer has a first through hole, and the second insulating layer has a second through hole. The drain includes a first portion electrically connected to the patterned electrode via the first through hole and the second through hole, and a second portion extending onto the common electrode. The common electrode is coupled with the patterned electrode to form a first storage capacitor and is coupled with the second portion to form a second storage capacitor. | 2013-12-05 |
20130323890 | Aqua Regia and Hydrogen Peroxide HCl Combination to Remove Ni and NiPt Residues - A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate. | 2013-12-05 |
20130323891 | Integrated Circuit Device with Well Controlled Surface Proximity and Method of Manufacturing Same - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 2013-12-05 |
20130323892 | METHODS OF PERFORMING HIGHLY TILTED HALO IMPLANTATION PROCESSES ON SEMICONDUCTOR DEVICES - One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate. | 2013-12-05 |
20130323893 | Methods for Forming MOS Devices with Raised Source/Drain Regions - A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor. | 2013-12-05 |
20130323894 | Transistor and Method for Forming the Same - The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer. | 2013-12-05 |
20130323895 | DEVICES WITH NANOCRYSTALS AND METHODS OF FORMATION - Devices can be fabricated using a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites can be created on a surface of the substrate. The creation of the nucleation sites may include implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nano scale structures may be grown using the controllable distribution of nucleation sites to seed the growth of the nano scale structures. According to various embodiments, the nano scale structures may include at least one of nanocrystals, nanowires, or nanotubes. According to various nanocrystal embodiments, the nanocrystals can be positioned within a gate stack and function as a floating gate for a nonvolatile device. Other embodiments are provided herein. | 2013-12-05 |
20130323896 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction. | 2013-12-05 |
20130323897 | SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone. | 2013-12-05 |
20130323898 | METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER - A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process. | 2013-12-05 |
20130323899 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 2013-12-05 |
20130323900 | Strained MOS Device and Methods for Forming the Same - A semiconductor structure includes a semiconductor substrate having a top surface; a gate stack on the semiconductor substrate; and a stressor in the semiconductor substrate and adjacent the gate stack. The stressor comprises at least a first portion with a first top surface lower than the top surface of the semiconductor substrate. | 2013-12-05 |
20130323901 | CAPACITIVE ELEMENT, MANUFACTURING METHOD OF THE SAME, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A capacitive element, includes: an active region parted by an element isolation region formed in a semiconductor substrate; a first electrode formed of a diffusion layer in the active region; an insulating layer formed on the first electrode; and a second electrode formed on a planar surface of the first electrode via the insulating layer, wherein the second electrode is formed within the active region and within the first electrode in a planar layout. | 2013-12-05 |
20130323902 | Methods of Forming a Plurality of Capacitors - A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors. | 2013-12-05 |
20130323903 | Process for fabricating an integrated circuit having trench isolations with different depths - A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a FET by forming a channel, a source, and a drain of the field effect transistor in the silicon layer. | 2013-12-05 |
20130323904 | METHOD FOR FORMING INSULATING FILM - [Problem] To provide a method capable of forming an insulating film having homogeneous and high bulk density and less suffering defects. | 2013-12-05 |
20130323905 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench. | 2013-12-05 |
20130323906 | Method Of Manufacturing Thin-Film Bonded Substrate Used For Semiconductor Device - A method of manufacturing a thin-film bonded substrate used for semiconductor devices. The method includes the steps of epitaxially growing an epitaxial growth layer on a first substrate of a bulk crystal, cleaving the first substrate, thereby leaving a crystal thin film on the epitaxial growth layer, the crystal thin film being separated out of the first substrate, and bonding a second substrate to the crystal thin film, the chemical composition of the second substrate being different from the chemical composition of the first substrate. It is possible to preclude a conductive barrier layer of the related art, prevent a reflective layer from malfunctioning due to high-temperature processing, and essentially prevent cracks due to the difference in the coefficients of thermal expansion between heterogeneous materials that are bonded to each other. | 2013-12-05 |
20130323907 | ACTIVE CARRIER FOR CARRYING A WAFER AND METHOD FOR RELEASE - In the field of release and pickup of ultrathin semiconductor dies, there is provided an active carrier ( | 2013-12-05 |
20130323908 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, wherein the method comprises steps as follows: Firstly, a device wafer is provided and a patterned bonding layer is then formed within a scribe line region of the device wafer. Subsequently a handle wafer is bonded to the device wafer by the patterned bonding layer. Next, a dicing process is performed along the scribe line region in order to divide the device wafer into a plurality of dices and remove the patterned bonding layer simultaneously, whereby the divided dices can be separated from the handle wafer. | 2013-12-05 |
20130323909 | METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS HAVING LASERED FEATURES CONTAINING DOPANTS - A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness to form a thinned substrate; applying a dopant to the back side of the thinned substrate; and laser processing the back side of the thinned substrate to form a plurality of patterns of lasered features containing the dopant. The dopant can be selected to modify properties of the semiconductor substrate such as carrier properties, gettering properties, mechanical properties or visual properties. | 2013-12-05 |
20130323910 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING SYSTEM - A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate. | 2013-12-05 |
20130323911 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is disclosed. In the semiconductor device, a gate is formed to enclose a fin structure in a 6F | 2013-12-05 |
20130323912 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like. | 2013-12-05 |
20130323913 | DICHALCOGENOBENZODIPYRROLE COMPOUND - A dichalcogenobenzodipyrrole compound represented by the formula (1): | 2013-12-05 |
20130323914 | Methods for Depositing Amorphous Silicon - Methods for depositing an amorphous silicon layer on wafers are disclosed. A process wafer, a control wafer, and a dummy wafer may be loaded into a chamber where an amorphous silicon layer may be deposited on the process wafer. Afterwards, the process wafer and the control wafer may be removed from the chamber. The chamber and the dummy wafers are dry cleaned together. The dry cleaned dummy wafers are used in the next run for depositing amorphous silicon layer. The process may be controlled by a computer system issuing a control job comprising a first process job and a second process job, wherein the first process job is to deposit an amorphous silicon layer on the process wafer, and the second process job is to dry clean the chamber and the dummy wafer. | 2013-12-05 |
20130323915 | METHOD AND APPARATUS FOR FORMING SILICON FILM - A method of forming a silicon film includes a first film forming process, an etching process, a doping process, and a second film forming process. In the first film forming process, a silicon film doped with impurities containing boron is formed so as to embed a groove provided on an object to be processed. In the etching process, the silicon film formed in the first film forming process is etched. In the doping process, the silicon film etched in the etching process is doped with impurities containing boron. In the second film forming process, a silicon film doped with impurities containing boron is formed so as to embed the silicon film that is doped in the doping process. | 2013-12-05 |
20130323916 | PLASMA DOPING METHOD AND APPARATUS - A plasma doping apparatus which introduces a predetermined mass flow of gas from a gas supply device into a vacuum chamber while discharging the gas through an exhaust port by a turbo-molecular pump, which is an exhaust device in order to maintain the vacuum chamber under a predetermined pressure by a pressure adjusting valve. A high-frequency power source supplies high-frequency power of 13.56 MHz to a coil disposed in the vicinity of a dielectric window opposite a sample electrode in order to generate an inductively coupled plasma in the vacuum chamber. A sum of an area of an opening of a gas flow-off port opposed to a center portion of the sample electrode is configured to be smaller than that of an area of an opening of the gas flow-off port opposed to a peripheral portion of the sample electrode in order to improve the uniformity. | 2013-12-05 |
20130323917 | SELF-ALIGNED PATTERNING FOR DEEP IMPLANTATION IN A SEMICONDUCTOR STRUCTURE - Methods of forming self-aligned patterns for performing oppositely doped deep implantations in a semiconductor substrate are disclosed. The semiconductor substrate has implantation and non-implantation regions. The methods include forming a hardmask pattern for a first implantation with a first conductivity-type dopant, depositing an etch stop layer, filling trenches between the hardmask pattern with a sacrificial filler material having a higher wet etch resistance than the hardmask, removing a top portion of the sacrificial filler material and the etch stop layer over a top surface of the hardmask pattern, removing the hardmask pattern in the implantation region by wet etching, and performing a second ion implantation with a second conductivity type dopant opposite of the first conductivity type. | 2013-12-05 |
20130323918 | METHODS FOR ELECTRON BEAM PATTERNING - A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process. | 2013-12-05 |
20130323919 | METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES - A method of preventing contact metal from protruding into neighboring gate devices to affect work functions of the neighboring gate devices is provided includes forming a gate structure. Forming the gate structure includes forming a work function layer, and forming a gate metal layer having a void, wherein the work function layer surrounds the gate metal layer. The method further includes forming a contact plug having a contact metal directly on the gate metal layer of the first gate stack, wherein the contact metal protrudes into the void, and the work function layer prevents the contact metal from protruding into a second gate stack. | 2013-12-05 |
20130323920 | Method of fabricating a gate-all-around word line for a vertical channel dram - A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less. | 2013-12-05 |
20130323921 | METHOD OF MAKING AN INSULATED GATE SEMICONDUCTOR DEVICE AND STRUCTURE - In one embodiment, a trench shield electrode layer is separated from a trench gate electrode by an inter-electrode dielectric layer. A conformal deposited dielectric layer is formed as part of a gate dielectric structure and further isolates the trench shield electrode from the trench gate electrode. The conformal deposited dielectric layer is formed using an improved high temperature oxide (HTO) low pressure chemical vapor deposition (LPCVD) process. | 2013-12-05 |
20130323922 | SPLIT GATE MEMORY DEVICE WITH GAP SPACER - A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer. | 2013-12-05 |
20130323923 | METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING IMPROVED SPACERS - Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer. | 2013-12-05 |
20130323924 | METHODS OF FORMING A PATTERN IN A MATERIAL AND METHODS OF FORMING OPENINGS IN A MATERIAL TO BE PATTERNED - Methods of forming a pattern in a material and methods of forming openings in a material to be patterned are disclosed, such as a method that includes exposing first portions of a first material to radiation through at least two apertures of a mask arranged over the first material, shifting the mask so that the at least two apertures overlap a portion of the first portions of the first material, and exposing second portions of the first material to radiation through the at least two apertures. The first portions and the second portions will overlap in such a way that non-exposed portions of the first material are arranged between the first portions and second portions. The non-exposed or exposed portions of the first material may then be removed. The remaining first material may be used as a photoresist mask to form vias in an integrated circuit. The pattern of vias produced have the capability to exceed the current imaging resolution of a single exposure treatment. | 2013-12-05 |
20130323925 | PATTERN FORMING METHOD, MOLD AND DATA PROCESSING METHOD - According to one embodiment, a pattern forming method is disclosed. The method can include forming an insulating layer on a major surface of a substrate. The method can include forming first and second openings on the insulating layer. The first opening has a first length in a first direction along the major surface, and the second opening has a second length longer than the first length in the first direction. The method can include forming a first pattern in the first opening. The method can include forming a second pattern in the second opening. The method can include forming a self-assembled material film contacting the insulating layer, the first pattern and the second pattern. The method can include forming a third pattern with guidance of the second pattern. In addition, the method can include forming a fourth pattern contacting the first pattern based on the third pattern. | 2013-12-05 |
20130323926 | COMPOSITE MATERIAL, METHOD OF PRODUCING THE SAME, AND APPARATUS FOR PRODUCING THE SAME - Proposed are a composite material having a high adhesiveness, wherein non-penetrating pores that are formed in a silicone surface layer are filled up with a metal or the like without leaving any voids by using the plating technique and the silicone surface layer is coated with the metal or the like, and a method of producing the composite material. A composite material, which has a high adhesiveness between a second metal or an alloy of the second metal ( | 2013-12-05 |
20130323927 | MANUFACTURING METHOD OF CIRCUIT STRUCTURE - A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. The metal layer and the surface passivation layer are dipped into a modifier, and the modifier is selectively absorbed and attached to the surface passivation layer, so as to form a covering layer. The covering layer has a plurality of nanoparticles and covers the surface passivation layer. | 2013-12-05 |
20130323928 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND MASK - An improvement is achieved in the performance of a semiconductor device. A method of manufacturing the semiconductor device includes an exposure step of subjecting a resist film formed over a substrate to pattern exposure using EUV light reflected by the top surface of an EUV mask which is a reflection-type mask. In the exposure step, the EUV mask is held with the cleaned back surface thereof being in contact with a mask stage. In the EUV mask, the water repellency of the side surface thereof is higher than the water repellency of the top surface thereof. After the exposure step, the resist film subjected to the pattern exposure is developed to form a resist pattern. | 2013-12-05 |
20130323929 | METHOD FOR SELECTIVELY MODIFYING SPACING BETWEEN PITCH MULTIPLIED STRUCTURES - Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch. | 2013-12-05 |
20130323930 | Selective Capping of Metal Interconnect Lines during Air Gap Formation - Provided are methods and systems for forming air gaps in an interconnect layer between adjacent conductive lines. Protective layers may be selectively formed on exposed surfaces of the conductive lines, while structures in between the lines may remain unprotected. These structures may be made from a sacrificial material that is later removed to form voids. In certain embodiments, the structures are covered with a permeable non-protective layer that allows etchants and etching products to pass through during removal. When a work piece having a selectively formed protective layer is exposed to gas or liquid etchants, these etchants remove the sacrificial material without etching or otherwise impacting the metal lines. Voids formed in between these lines may be then partially filled with a dielectric material to seal the voids and/or protect sides of the metal lines. Additional interconnect layers may be formed above the processed layer containing air gaps. | 2013-12-05 |
20130323931 | DEVICE MANUFACTURING AND CLEANING METHOD - A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H | 2013-12-05 |
20130323932 | LAYER-LAYER ETCH OF NON VOLATILE MATERIALS USING PLASMA - A method for etching a metal layer, comprising plurality of cycles is provided. In each cycle, an etch gas comprising PF | 2013-12-05 |
20130323933 | Methods for Forming Microlenses - Methods for forming microlenses on a semiconductor substrate are provided. An inductively coupled plasma etch process using a process gas that includes a mixture of CF | 2013-12-05 |
20130323934 | DYE ADSORPTION DEVICE, DYE ADSORPTION METHOD AND SUBSTRATE TREATMENT APPARATUS - [Problem] To significantly reduce processing time of a step of adsorbing dye in a porous semiconductor layer on a substrate surface. | 2013-12-05 |
20130323935 | FILM FORMING METHOD AND APPARATUS - A method of forming a thin film on a surface of target objects in a vacuum-evacuable processing chamber by using a source gas and a reaction gas includes: forming a mixed gas by mixing the source gas and an inert gas in a gas reservoir tank, and supplying the mixed gas and the reaction gas into the processing chamber. | 2013-12-05 |
20130323936 | APPARATUS AND METHODS FOR RAPID THERMAL PROCESSING - Embodiments of the present invention provide apparatus and methods for performing rapid thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate. The apparatus includes a heating source disposed outside a chamber body and configured to provide thermal energy towards a processing volume. The substrate support defines a substrate supporting plane, and the substrate support is configured to support the substrate in the substrate supporting plane. The heating source includes a frame member having an inner wall surrounding an area large enough to encompass a surface area of the substrate, and a plurality of diode laser tiles mounted on the inner wall of the frame member. Each of the plurality of diode laser tiles is directed towards a corresponding area in the processing volume. | 2013-12-05 |
20130323937 | Combined Laser Processing System and Focused Ion Beam System - A processing system for forming a cross-section of an object. The processing system comprises a focused ion beam system for forming the cross-section from a pre-prepared surface region of the object and a laser and a light optical system for forming the pre-prepared surface region by laser ablation of a processing region of the object with a first and a second laser beam. The light optical system is configured to direct the first and the second laser beams onto common impingement locations of a common scanning line in the processing region for scanning the first laser beam and for scanning the second laser beam. For each of the impingement locations, an angle between a first incidence direction along an axis of the first laser beam and a second incidence direction along an axis of the second laser beam is greater than 10 degrees, | 2013-12-05 |
20130323938 | SWIVEL ADAPTOR - A device comprising a bottom portion providing a first contact and a second contact via an outer surface, an inner surface is conductive with the outer surface. The device comprises a bottom pressure pin, within the bottom portion, connected to the first contact and a top portion rotatably fixed to the bottom portion and comprising first and second connectors functionally exposed therethrough. The device comprises a printed circuit board (PCB), within the bottom portion, providing a first route to the first connector and a second route to the second connector. The PCB is fixably attached to the electrical connectors and the first route continuously contacts with the bottom pressure pin. The device comprises a radial pressure pin, fixably connected to the second route, that provides continuous connection with the second contact through the bottom portion's inner surface. A method of assembly of the device and a kit comprising the device. | 2013-12-05 |
20130323939 | COUPLING AND CONDUIT FOR CONSIST COMMUNICATION SYSTEM - A coupling for a communication conduit is disclosed for use with a train consist. The coupling may include a nipple configured for insertion within a fluid conduit, a flange configured to engage an end of the fluid conduit, a retention member configured to engage an outer surface of the fluid conduit, a first fitting extending from the flange away from the nipple, and, a retaining tab configured to retain a second fitting of another coupling in engagement with the first fitting. The coupling may further include a closure mechanism configured to close off an end of the first fitting and movable during engagement with the second fitting to open the end of the first fitting. | 2013-12-05 |
20130323940 | CONNECTORS AND ADAPTERS WITH AUTO-LATCHING FEATURES - Fiber optic connectors and adapters may be automatically secured and released via a management system. Such automation may inhibit accidental and/or unauthorized insertion of fiber optic connectors into adapter ports. The automation also may inhibit accidental and/or unauthorized removal of the fiber optic connectors from the adapter ports. | 2013-12-05 |
20130323941 | Magnetic Connector - Embodiments of magnetic connectors are disclosed. Embodiments show the use of magnetic connectors for power and/or signal bus coupling to electronic devices from support bases, stands, or cables. In some embodiments, spherical contacts, such as ball bearings, are pressed into firm contact with an electronic device by the use of conductive springs, which in turn electrically couple the spherical contacts to the bus lines. Contact arrangements are shown which allow rotation of the electronic device against an embodiment of magnetic connector. Arrangements of multiple magnets having differing polarities are shown when alignment of an electronic device in a particular orientation is required. | 2013-12-05 |
20130323942 | DEVICE AND METHOD FOR INTERCONNECTING ELECTRONIC SYSTEMS HAVING DIFFERENT REFERENCE POTENTIALS - A device is provided for interconnecting electronic systems having reference potentials separated by an alternating potential difference, the device includes a plurality of electrical connections that can electrically connect the electronic systems, and inductance coils arranged in series on the electrical connections, the inductance coils being electromagnetically coupled. Als provided is a method for interconnecting electronic systems. | 2013-12-05 |
20130323943 | SMART CARD SECURING MECHANISM AND ELECTRONIC DEVICE USING SAME - A smart card securing mechanism for securing two smart cards includes a base and a sliding member slidably received in the base. The sliding member accepts two smart cards in a tandem and partially overlapped manner, saving a considerable amount of internal space within an electronic device containing the smart card securing mechanism. | 2013-12-05 |
20130323944 | CONNECTOR - A connector includes a housing and terminal fittings attached to a printed circuit board. The terminal fittings form two terminal rows. In the terminal rows, one end parts of the terminal fittings are piled in a fitting plate part of the housing to which a mate side connector is fitted in a mutually parallel state and arranged in parallel with a surface of the printed circuit board. Central parts of the terminal fittings are bent. The other end parts are connected to a conductor pattern of the printed circuit board. In the other end parts of the terminal fittings, outward bent parts are provided which are bent outward in the direction of width of the housing. Tip ends of the other end parts of all the terminal fittings are arranged with spaces left between them along the direction of width of the housing. | 2013-12-05 |
20130323945 | FLEX TO FLEX CONNECTION DEVICE - A mechanical device for electrically connecting a first flexible assembly to a second flexible assembly comprises a wafer and a housing. The wafer has an insulator core and a plurality of wafer electrical connectors. The core has a first base side and an opposed second base side. The wafer electrical connectors include a first set of wafer electrical connector contacts exposed on the first base side and a second set of wafer electrical connector contacts exposed on the second base side. The wafer electrical connector contacts are adapted to electrically connect with each of the flexible assembly electrical contacts. The housing retains the wafer, the first flexible assembly terminal, and the second flexible assembly terminal in such a way that each of the first flexible assembly electrical contacts is removably secured and electrically connected to one of the wafer electrical connector contacts. | 2013-12-05 |
20130323946 | APPARATUS FOR ELECTRICALLY CONNECTING A FLEXIBLE CIRCUIT TO A RECEIVER - An electrical assembly combination includes (a) a receiver having a receiver housing and a plurality of receiver housing electrical contacts, and (b) a connector device comprising a connector housing capable of accepting and retaining a terminal end of a flexible assembly having a plurality of flexible assembly electrical contacts. The connector device is capable of being reversibly attached to the receiver housing such that each of the receiver housing electrical contacts is electrically connected to a flexible assembly electrical contact in a removable, non-permanent manner. | 2013-12-05 |
20130323947 | ELECTRICAL PLUG DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - An electrical plug device includes a housing that is formed with two receptacles, a positioning member that is disposed in the housing and that includes a base, a fixed arm unit and a flexible arm unit, and a plug member that includes a pivot rod and two plug prongs receivable in the receptacles. The base, the fixed arm unit and the flexible arm unit cooperatively define an engaging groove. The pivot rod includes a rod body pivotally received in the engaging groove and a protrusion protruding from the rod body. The plug prongs are respectively secured in position when respectively protruding out of the receptacles via detachable engagement of the protrusion with and detachable abutment of the rod body against the flexible arm unit. | 2013-12-05 |
20130323948 | ELECTRICAL CONNECTOR ASSEMBLY - A connector assembly has a base and a cover. The base has first base terminals and second base terminals for engaging an equipment member. The first and second base terminals include tabs at a first end thereof. The cover has cover terminals, with each cover terminal comprising a tab at first end and at least one receptacle at a second end thereof. The tabs of the cover terminals are configured to releasably engage a first mating electrical connector and the receptacles are configured to releasably engage the tabs of the first base terminals or the tabs of the second base terminals. The configuration of the first base terminals and the second base terminals allows alternate covers to be releasably mounted on the base as required. | 2013-12-05 |
20130323949 | RELEASE TAB FOR AN ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTOR COMPRISING SAID RELASE TAB - The present invention relates to a release tab ( | 2013-12-05 |
20130323950 | CONNECTOR ASSEMBLY WITH POLARITY CORRECTION/PROTECTION - A connector assembly for installing a device to a ceiling grid, the ceiling grid having conductors provided therein. The connector assembly includes a housing with contact arms mounted in the housing. Contact portions of the contact arms extend from the housing and are placed in electrical engagement with the conductors when the connector assembly is mated with the ceiling grid. Mounting members extend from the housing. Mounting sections of the mounting members are placed in mechanical engagement with the ceiling grid to provide a mechanical connection between the ceiling grid and the connector assembly. A polarity protection/correction member is provided in the housing. The polarity protection/correction member protects the device from failure or damage when the polarity orientation of the device does not match the polarity orientation of the conductors of the grid. | 2013-12-05 |
20130323951 | ADAPTOR FOR CONNECTING CONNECTORS WITH DIFFERENT INTERFACES - An adaptor, for connecting two electrical connectors with different interfaces, has a first connector, a second connector and a connecting means connecting the first connector and the second connector. The first connector includes a first insulating housing and first contacts received in the first insulating housing. The second connector includes a second insulating housing and second contacts received in the second insulating housing. The first connector has a pair of receiving openings. The first contacts have a first group of contacts and a second group of contacts. The first group of contacts and the second group of contacts are respectively received in the pair of receiving openings. | 2013-12-05 |
20130323952 | ELECTRICAL CONNECTOR RECEPTACLE FOR MOUNTING WITHIN AN EXPLOSION PROOF ENCLOSURE AND METHOD OF MOUNTING - An electrical connector receptacle for mounting within an explosion proof enclosure includes a flange portion having a first side, a second side and a centrally disposed aperture. Also included is a cylindrical member integrally formed with the flange portion and extending away from the first side. Further included is a plurality of apertures extending from the first side to the second side, wherein the plurality of apertures are configured to receive a mechanical fastener for mounting the electrical connector receptacle to a printed wiring board. Yet further included is an o-ring groove disposed within the first side and spaced radially outwardly from an outer surface of the cylindrical member. Also included is a plurality of mounting feet integrally formed with the flange portion and extending away from the second side to form an electrical bonding path to the printed wiring board. | 2013-12-05 |
20130323953 | LEVER CONNECTOR - A lever connector includes a first connector housing, a second connector housing that includes a distal fitting portion intended for a distal end of the first connector housing to be fittedly connected thereto, and is adapted to be attached to a connector attaching plate in a state of inserting the second connector housing through a connector attaching hole of the connector attaching plate, a lever adapted to fit the first connector housing into the second connector housing by a pivoting operation, and a grommet for ensuring a waterproofing property of an inside of the first connector housing. The lever includes a lever body, a pivoting connection portion, and a lever locking piece. The grommet is fitted and mounted on the lever and includes a lever covering portion, and a tubular. | 2013-12-05 |
20130323954 | ELECTRICAL CONNECTOR AND CONNECTOR SYSTEM - The invention relates to an electrical connector ( | 2013-12-05 |
20130323955 | CONNECTOR TERMINAL AND CARD EDGE TYPE CONNECTOR INCLUDING THIS CONNECTOR TERMINAL - A connector terminal includes: a main body section having a board-contacting-surface which is flat and capable of contacting a connecting conductor of a circuit board; and an elastic deforming section that is positioned on a side opposite to the board-contacting-surface in a thickness direction of the circuit board, and that can deform elastically in the thickness direction with respect to the main body section. | 2013-12-05 |
20130323956 | GROOVED CONNECTORS WITH RETAINING MECHANISMS - A connector is disclosing with a housing having a housing groove and a shaft with a pin groove. A spring may be located in either the housing groove or the pin groove. To prevent or limit the spring from popping out from the groove where it is positioned, a reduced entrance is provided. The connector may be used in a holding application, a latching application, or both a holding with latching application. | 2013-12-05 |
20130323957 | CONNECTOR TO FLEX ASSEMBLY - An electrical assembly connector for connecting a flexible assembly having a plurality of flexible assembly electrical contacts to a rigid assembly having a connector receptacle with a plurality of attachment element electrical contacts. The connector comprises an intermediary device configured to electrically connect the rigid assembly and the flexible assembly. The intermediary device has a plurality of connector electrical contacts. The intermediary device electrical contacts are exposed on a first base side and on a second base side of the intermediary device. The intermediary device electrical contacts exposed on the second base side are configured to mechanically and electrically couple to the flexible assembly electrical contacts, and the intermediary device electrical contacts exposed on the first base side are configured to electrically and mechanically couple to the attachment element electrical contacts. | 2013-12-05 |
20130323958 | CONNECTOR - A connector includes: a female terminal housing provided with a terminal receiving cavity receiving a female terminal; and a male terminal housing retaining a male terminal to be connected to the female terminal. The male and female terminal housings have first and second engagement portions. The male and female terminal housings are fitted in a first fitting position by the first engagement portion. The male and female terminal housings are fitted in a second fitting position by the second engagement portion. The first fitting position is a position in which the locking hole of the female terminal is engaged with the lance of the terminal receiving cavity, and in which the male terminal is not in sliding contact with the female terminal. The second fitting position is a position in which the male terminal is in sliding contact with the female terminal. | 2013-12-05 |
20130323959 | ELECTRONIC CONNECTOR MODULE HAVING AN IMPROVE RELEASING MECHANISM WITH A SIMPLE STRUCTURE - An electrical connector module for mating with a complementary connector module comprises a housing defining a channel formed on a top surface thereof and a mounting slot recessed downwardly from a bottom surface of the channel; a releasing mechanism received into the channel, the releasing mechanism defines a tab extending into the mounting slot, and an actuator formed on a front end thereof; and a resilient piece received into the mounting slot, the resilient piece having a front end abutting against a front inner surface of the mounting slot and a rear end abutting against the tab; the complementary connector module comprises a latching member locked in the front end of the channel and located above the actuator; the releasing mechanism moves forwardly, the actuator extends into a front end of the channel and raises up the latching member along a vertical direction. | 2013-12-05 |
20130323960 | EXTENSION APPARATUS FOR POWER OUTLET - An extension apparatus of a power outlet includes a main body and a socket. The main body includes a plug portion and an extension plug portion. The plug portion defines three through holes. The extension plug portion defines three blind holes. Three first metal pieces are mounted in the through holes. Three second metal pieces are mounted in the blind holes and coupled to the first metal pieces. The socket is plugged into the extension plug portion to be coupled to the plug portion. When a first plug is plugged into the plug portion, electrical power is fed to a second plug. | 2013-12-05 |
20130323961 | CABLE CONNECTOR ASSEMBLY WITH RELIABLE CONNECTION - A cable connector assembly includes a housing including a main portion and a mating portion extending forwardly from the main portion, a number of contacts received in the housing and including first contacts and second contacts; a number of first wires connecting with the first contacts; and a number of second wires connecting with the second contacts. Each first contact includes a first contacting section and a first termination section exposed beyond the housing. Each second contact includes a second contacting section and a second termination section exposed beyond the housing. The first termination section electrically connects with corresponding first wire via Insulation Displacement Connection (IDC). The second termination section electrically connects with corresponding second wire via soldering. | 2013-12-05 |
20130323962 | PLUG CONNECTOR - A plug connector includes an insulative body, a housing and a plurality of terminals, and electrically connects to an electrical cable in a manner of insulation-displacement. The insulative body defines a top piece having an external thread of a first screw portion in one end, and defines a plurality of inserting grooves disposed with the terminals. The housing defines an interior space communicating with the inserting grooves, and defines an inner thread of a second screw portion in one end. The interior space accommodates a holding block remaining an electrical conductor of the electrical cable bent out. The housing connects the insulative body with the inner thread to the external thread. | 2013-12-05 |
20130323963 | CAGE WITH A HEAT SINK MOUNTED ON ITS MOUNTING SIDE AND AN EMI GASKET WITH ITS FINGERS ELECTRICALLY CONNECTED TO THE MOUNTING SIDE - A cage assembly is provided for receiving a pluggable module. The cage assembly includes a cage having a front end, a mounting side, and an internal compartment. The front end is open to the internal compartment of the cage. The internal compartment is configured to receive the pluggable module therein through the front end. A heat sink is mounted to the mounting side of the cage. The heat sink has a module side that is configured to thermally communicate with the pluggable module. An electromagnetic interference (EMI) gasket extends along at least a portion of an interface between the mounting side of the cage and the module side of the heat sink. The EMI gasket includes electrically conductive spring fingers that are engaged with and electrically connected to the mounting side of the cage. | 2013-12-05 |
20130323964 | ELECTRICAL CONNECTOR ASSEMBLY HAVING ASSISTANT HEAT DISSIPATING DEVICE - An electrical connector assembly for use with an electronic package, includes an electrical connector having a plurality of contacts, and an assistant heat sink mounted upon the electrical connector and having an opening to allow the electronic package connecting with the contacts. | 2013-12-05 |
20130323965 | Power Adapter for RF Coaxial Cable and Method for Installation - An adapter for coupling a coaxial interface to a power conductor and method for interconnection may be provided as a body with a conductor junction dimensioned to couple with the power conductor and a mating surface dimensioned to couple with the coaxial interface. The conductor junction, an outer conductor contacting portion of the mating surface and an inner conductor contacting portion of the mating surface are electrically coupled together by the body. | 2013-12-05 |
20130323966 | COMPRESSION CONNECTOR FOR CABLES - A connector for cables has a plurality of components including a first connector structure, a second connector structure, and a conductive pin. The components cooperate to engage an end of a cable. | 2013-12-05 |
20130323967 | Male Coaxial Connectors Having Ground Plane Extensions - Coaxial connectors are provided that include a contact post that has a pedestal and a post extending therefrom. These connectors further include a ground plane extension that is separate from the contact post. The ground plane extension includes a first end that is positioned on a first side of the pedestal and a sidewall that extends from the first end of the ground plane extension. This sidewall extends beyond a second side of the pedestal that is opposite the first side. | 2013-12-05 |
20130323968 | COMPRESSION CONNECTOR FOR CABLES - A connector for cables has a plurality of connector members including a first connector member, a second connector member, and a conductive pin. The connector members cooperate to engage an end of a cable. | 2013-12-05 |
20130323969 | SOCKET FOR ELECTRONIC COMPONENTS - A socket for electronic components includes a shield plate assembly that is formed by combining first shield plates with second shield plates in the form of a lattice and has conductivity, and contact units electrically connected to electrode terminals of electronic components are disposed in openings of the lattice of the shield plate assembly so that the electrode terminals are electrically connected to the wiring of a wiring board. The shield plate assembly is formed in a shape where lines where openings of the lattice are lined up in a first direction are arranged side by side in a second direction orthogonal to the first direction, and the openings of the adjacent lines are formed so as to be shifted relative to the openings of the next lines in the first direction by a half of the length of the side of the opening that extends in the first direction. | 2013-12-05 |
20130323970 | CABLE ASSEMBLY WITH IMPROVED TERMINAL STRUCTURE - A cable assembly comprises: an insulative housing and a terminal module assembled to a rear end of the insulative housing. The terminal module comprises a plurality of pairs of differential signal terminals and a plurality of grounding terminals arranged long a widthwise direction thereof Each of terminal defining a mating portion, a body portion and a soldering portion. Mating portions of the signal and grounding terminals are located on a row, body portions and soldering portions of the signal and grounding terminals are located on two rows. There are at least one grounding terminal is intervened between two pairs of differential signal terminals to totally space apart the body portions and soldering portions of two adjacent pairs of differential signal terminals located on two rows. | 2013-12-05 |
20130323971 | CONNECTOR - A connector is fixable to an object such as a circuit board. The connector comprises a housing having a land extending long in a lengthwise direction, a power contact, a metal plate for protecting the connector from ESD, a shell (connection member) configured to be fixed and connected to the circuit board, and a coupling member coupling the metal plate and the shell with each other. The metal plate is inserted in and held by the land. The connector is thus configured so that a static electricity is grounded to the circuit board through the metal plate, the coupling member and the shell. Moreover, the power contact is locatable at an end of the land in the lengthwise direction so that it is possible to reduce the size of the connector. | 2013-12-05 |
20130323972 | SHIELD FOR AN ELECTRICAL CONNECTOR AND A METHOD OF MANUFACTURING THE SAME - A shield for an electrical connector comprises a conductive housing configured to enclose an exposed portion of at least one electrical connector. The shield further comprises at least one opening formed in the conductive housing configured to allow a corresponding mating portion of each of the at least one electrical connectors to be exposed. The shield further comprises and a plurality of conductive points located along at least one circumferential path within the conductive housing remote from the at least one opening. | 2013-12-05 |