49th week of 2008 patent applcation highlights part 62 |
Patent application number | Title | Published |
20080301319 | Methods, systems, and computer program products for providing accidental stack join protection - The subject matter described herein includes methods and systems for providing accidental stack join protection. According to one embodiment, a method includes connecting stacking ports of a first switch that is a member of a first stack and a second switch that is a member of a second stack and thereby joining the first and second stacks. The configurations of the first stack and of the second stack are detected and it is determined whether the detected configurations indicate a configuration mismatch between the first and second stacks. In response to determining that the detected configurations relate to a mismatch, the automatic joining of the first and second stacks is inhibited and the first and second stacks are allowed to continue switching traffic with their existing configurations. | 2008-12-04 |
20080301320 | Method And System For Managing Communication Protocol Data Based On MIME Types - Methods and systems are described for managing communication protocol data in a communication stack of an electronic device. One method includes providing a MIME type communication layer in a communication stack that comprises a plurality of communication layers and is operatively coupled to a network interface for receiving and sending data over a network. The MIME type communication layer receives a protocol frame that includes content in a payload, and an endpoint identifier associated with a recipient of the content, determines a MIME type associated with the content, identifies an element by parsing the content of the protocol frame based on the determined MIME type, and determines a data item corresponding to the identified element of the determined MIME type. The data item is provided to the recipient asociated with the endpoint identifier. wherein the recipient receives the data item without parsing the content of the protocol frame. | 2008-12-04 |
20080301321 | METHOD AND SYSTEM FOR COMMUNICATING WITH A DEVICE ATTACHED TO A COMPUTER USING ELECTRONIC MAIL MESSAGES - A method, system, and computer program product for communicating with machines connected to a network. Information sent to or from the machines is transmitted using electronic mail. The electronic mail may be transmitted over the Internet, but also may remain within a local or wide area network. When receiving electronic mail, the electronic mail message may be sent to a user who reads information regarding the purpose of the electronic mail message in the body of the message. When the user is satisfied that it is safe to perform the functions requested by the email, the user may execute a file which is attached to the incoming email message in order to perform the appropriate diagnostic or control operations. Alternatively, the incoming email message may contain a code or is sent to an address which causes automatic execution of the desired functions. In this embodiment, it may not be necessary for the user to manually perform any action in order to allow the appropriate processing to begin. Email messages may also be transmitted from the computer which is attached to the device which is being monitored or controlled and include information regarding the status or capabilities of the attached device. | 2008-12-04 |
20080301322 | NETWORK CONTROLLER, INFORMATION PROCESSING APPARATUS AND WAKE-UP CONTROL METHOD - According to one embodiment, a network controller includes a data register which stores first data indicative of a data pattern of an address resolution protocol request packet including a network address of an information processing apparatus, and second data indicative of a data pattern of a wake-up packet for waking up the information processing apparatus, a comparison unit configured to compare a data pattern of an incoming packet with the first data and the second data, while the information processing apparatus is in a sleep state, a transmission unit configured to send, if the data pattern of the incoming packet agrees with the first data, the address resolution protocol reply packet to the network, and a wake-up signal output unit configured to output, if the data pattern of the incoming packet agrees with the second data, a wake-up signal for instructing wake-up to the information processing apparatus. | 2008-12-04 |
20080301323 | SYNCHRONIZATION OF SIDE INFORMATION CACHES - In order to improve interactive compression using compression state information, the side information caches of communicating parties must be updated, or synchronized. The present invention is directed to a method of synchronizing side information databases within an interactive compression system comprising two communicating parties comprising the steps of transmitting, from the a first communicating party to the second communicating party, a device hierarchical node index; comparing the device hierarchical node index with a server hierarchical node index and then determining a shared hierarchical node index based on common entries in the two hierarchical node indexes. | 2008-12-04 |
20080301324 | Processor device and instruction processing method - A cache receives a request from an instruction execution unit, searches for necessary data, outputs the data to the instruction execution unit if there is a cache hit, and instructs a request storage unit to request a move-in of the data if a cache miss occurs. The request storage unit stores therein the request corresponding to the instruction of the cache while the requested process is being executed. A REQID assignment unit reads the request stored in the request storage unit, selects an unused REQID from a REQID table, and assigns the unused REQID to the read request. The REQID is an identification number of the request based on the number of requests set as the maximum number that can be received at a simultaneous time by a system controller of the response side. | 2008-12-04 |
20080301325 | Storage network system, managing apparatus managing method and program - A storage network system includes computers, storage systems, connection devices that control connection relations between the computers and the storage system, and a managing device that manages the computers, the storage system and the connection devices. The managing device includes a control section that specifies connection ports of the computers, the storage system and the connection devices that compose the storage network system. Further, the control device of the managing device displays on a display section a data traffic amount at each of the connection ports for each connection path from the computer to the storage system. | 2008-12-04 |
20080301326 | Detecting loss of communication with peripherals - Computer systems having operating systems that provide plug and play functionality for peripheral devices such as printers, web cameras, keyboards, mice and the like are known. These allow peripheral devices to be connected to the computer system in an ad hoc manner. However, if communication between a peripheral and such a computer system is lost during a time period when that computer system is shut down, no indication of this loss is given by the plug and play operating system. A method is described here for issuing error messages if communication between a peripheral and a computer system is lost. A persistent store is used to keep a record of peripherals in communication with the computer and this record is compared with detected information about presence of peripherals. The error messages may optionally be transferred to a remote management system via a communications network. | 2008-12-04 |
20080301327 | Direct Memory Access Transfer Completion Notification - Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field. | 2008-12-04 |
20080301328 | Method and system for improved communication between central processing units and input/output processors - A method and system for communicating information regarding input/output (IO) processing in a shared access to memory environment is disclosed. A central processing unit (CPU) and an input/output processor (IOP) are configured to write to and read from predetermined memory locations to manage the detection, performance, and completion of IOs. The CPU and the IOP may read from and write to memory as desired. | 2008-12-04 |
20080301329 | Data Transfer Apparatus and Data Transfer Method - A data transfer apparatus includes a processor, a main memory, and a DMAC connected to the main memory via a plurality of buses. The DMAC transfers data to the main memory by bypassing the processor, writes flag data “1” indicating completion of the data transfer processing in a completion status storage area of the main memory, and finally outputs an interrupt signal to the processor. In response to the interrupt signal, an interrupt handler refers to the completion status storage area, and when the flag data is written, reads the data in the main memory and erases the flag data in the completion status storage area. | 2008-12-04 |
20080301330 | USB HOST SYSTEM AND METHOD FOR TRANSFERRING TRANSFER DATA - A USB host system includes: a USB host module having a USB host function for performing USB transfer to/from a USB device; a different-function module having a predetermined function using transfer data that is to be an object of the USB transfer; at least one shared memory shared between the USB host module and the different-function module; and at least one dedicated memory exclusively used by the USB host module. At least part of management data for performing the USB transfer is stored in the dedicated memory. | 2008-12-04 |
20080301331 | Control method and computer system utilizing the same - A computer system comprising a memory module, a connection port, and a central processing unit (CPU) is disclosed. The memory module stores a main base input/output system (BIOS) comprising an auxiliary function. The connection port is capable of connecting an auxiliary module comprising at least one specific program. The CPU executes the main BIOS when the auxiliary function is de-activated. The CPU executes the specific program when the auxiliary function is activated. | 2008-12-04 |
20080301332 | METHOD FOR USING HOST AND STORAGE CONTROLLER PORT INFORMATION TO CONFIGURE PATHS BETWEEN A HOST AND STORAGE CONTROLLER - Provided is a method for using host and storage controller port information to configure paths between a host and storage controller. Information is gathered on ports on at least one host, ports on at least one storage controller managing access to storage volumes, and at least one fabric over which the at least one host and storage controller ports connect. For at least one host port and storage controller port, information is gathered on a connection metric related to a number of paths in which the port is configured and a traffic metric indicating Input/Output (I/O) traffic at the port. A determination is made of available ports for one host and storage controller that are available to provide paths between one host and storage controller. The connection and traffic metrics for the available host ports are processed to select at least one host port. The connection and traffic metrics for the available storage controller ports are processed to select at least one storage controller port. The at least one selected host and storage controller port pair are configured to provide at least one path enabling the host to communicate with the selected storage controller port to access at least one storage volume managed by the selected storage controller. | 2008-12-04 |
20080301333 | SYSTEM AND ARTICLE OF MANUFACTURE FOR USING HOST AND STORAGE CONTROLLER PORT INFORMATION TO CONFIGURE PATHS BETWEEN A HOST AND STORAGE CONTROLLER - Provided are a system and article of manufacture for using host and storage controller port information to configure paths between a host and storage controller. Information is gathered on ports on at least one host, ports on at least one storage controller managing access to storage volumes, and at least one fabric over which the at least one host and storage controller ports connect. For at least one host port and storage controller port, information is gathered on a connection metric related to a number of paths in which the port is configured and a traffic metric indicating Input/Output (I/O) traffic at the port. A determination is made of available ports for one host and storage controller that are available to provide paths between one host and storage controller. The connection and traffic metrics for the available host ports are processed to select at least one host port. The connection and traffic metrics for the available storage controller ports are processed to select at least one storage controller port. The at least one selected host and storage controller port pair are configured to provide at least one path enabling the host to communicate with the selected storage controller port to access at least one storage volume managed by the selected storage controller. | 2008-12-04 |
20080301334 | DISK CONTROL APPARATUS, DISK CONTROL METHOD, REMOTE DISK CONTROL APPARATUS, AND REMOTE DISK CONTROL METHOD - A disk control apparatus formats each track of a storage disk device in a short time. The disk control apparatus ( | 2008-12-04 |
20080301335 | Digital Display System With Media Processor And Wireless Audio - The present invention relates to a media processing system that comprises a bus for communicating digital signals thereon with a media processor connected to the bus, for processing signals supplied thereon. The system further has a display device connected to the bus for displaying digitized images thereon, received from the bus. The system has an audio transmitter connected to the bus, for wirelessly transmitting audio digital signals from the bus. The system further has a connectable memory for connecting to the bus and for supplying signals representing digitized images and audio digital signals to the bus. Finally the system has a receiver to receive encoded digitized images or audio digital signals for supplying the received signals to the bus for storage in the memory. | 2008-12-04 |
20080301336 | DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER - An apparatus and method for dynamically allocating memory between inbound and outbound paths of a networking protocol handler so as to optimize the ratio of a given amount of memory between the inbound and outbound buffers is presented. Dedicated but sharable buffer memory is provided for both the inbound and outbound processors of a computer network. Buffer memory is managed so as to dynamically alter what portion of memory is used to receive and store incoming data packets or to transmit outgoing data packets. Use of the present invention reduces throttling of data rate transmissions and other memory access bottlenecks associated with conventional fixed-memory network systems. | 2008-12-04 |
20080301337 | Memory Systems For Automated Computing Machinery - Memory systems are disclosed that include a memory controller; an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller. | 2008-12-04 |
20080301338 | Data transfer control device and electronic instrument - A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates an interface signal and outputs the generated interface signal to an interface bus; and an internal register in which is set timing information for specifying a timing at which a signal level of the interface signal output from the interface circuit changes. The interface circuit generates the interface signal, a signal level of which changes at a timing according to the timing information set in the internal register. | 2008-12-04 |
20080301339 | CONTROL DEVICE FOR A USB INTERFACE AND CONTROL METHOD THEREOF - A control device for a USB interface including at least one first terminal for inputting the data to be transmitted and at least one second terminal for the transmission of the packet data on a bus; the packet data include one end-of-packet signal. The USB interface includes one circuit for the data transmission on said at least one second terminal; the USB interface is adapted to receive as an input a signal for the activation of the transmission circuit when data are received from the at least one first terminal and the transmission circuit includes a bias circuit. The control device includes a circuit for the detection of an end-of packet signal on said bus and a control circuit adapted to activate the bias circuit of the transmission circuit if said end-of-packet signal is detected by said detection circuit. | 2008-12-04 |
20080301340 | Method for Data Transmission - A method for data transmission in a system is disclosed. The system includes a computer ( | 2008-12-04 |
20080301341 | Management Of Internal Operations By A Storage Device - A method enables a storage device to autonomously (i.e., without intervention of a host device) determines whether an integral sequence of commands, which is related to one or more storage commands issued by the host device, is in a certain state (i.e., it is “active” or “inactive”) or is transitioning from “active” state to “inactive” state, or from “inactive” state to “active” state. Depending on the determined state or transition, the storage device determines whether to refrain from executing Extra-Sequence (“ESQ”) operations and permit executing Intra-Sequence (“ISQ”) operations, or vice versa. | 2008-12-04 |
20080301342 | Device Directed Memory Barriers - Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features. | 2008-12-04 |
20080301343 | DEVICE FOR CONTROLLING COMMUNICATION BETWEEN A MODULE AND A TRANSMISSION BUS - The invention relates to a device for controlling communication between a module ( | 2008-12-04 |
20080301344 | SYSTEM FOR EXPANDABLY CONNECTING ELECTRONIC DEVICES - An exemplary system for expandably connecting electronic devices includes a master device, a first slave device, and a second slave device. The first and second slave device each has a control chip and an address setting module. The control chip includes a bus interface connected to the master device via a common bus. The address setting module has a counter unit. The master device sets a first address for the control chip and the counter unit of the first slave device, the counter unit of the first slave device calculates the first address and sends a calculated address to the control chip and the counter unit of the second slave device as a second address of the second slave device. The first address and the second address are different from each other, thus a plurality of slave devices can connected to the master device via a common bus. | 2008-12-04 |
20080301345 | MULTI-CHARACTER ADAPTER CARD - One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data. | 2008-12-04 |
20080301346 | MOTHER BOARD MODULE AND PERSONAL COMPUTER HOST USING THE SAME - A mother board module suitable for being disposed in a housing of a personal computer (PC) host is provided. The housing has expansion port openings at a rear wall of the housing. The mother board module includes a mother board, a sound card and a signal transmission cable. The mother board includes a circuit board and interface card slots. The interface card slots are juxtaposed on the circuit board and disposed corresponding to the expansion port openings respectively. The sound card has a fixing plate and audio jacks disposed thereon. Each of the audio jacks has a plug-in hole. The fixing plate is suitable for being removably fixed on one of the expansion port openings, which exposes the plug-in holes of the audio jacks beyond the rear wall. Two ends of the signal transmission cable are connected with the sound card and the circuit board respectively. | 2008-12-04 |
20080301347 | USB2.0 BI DIRECTIONAL AMPLIFIER - A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel. | 2008-12-04 |
20080301348 | DEVICE FOR CONTROLLING POINT-TO-POINT COMMUNICATION BETWEEN A MODULE AND TRANSMISSION BUS - The invention relates to a device for controlling point-to-point communication between a module ( | 2008-12-04 |
20080301349 | Semiconductor Memory Arrangement - A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units. | 2008-12-04 |
20080301350 | Method for Reassigning Root Complex Resources in a Multi-Root PCI-Express System - A system for reassigning root complex resources in a multi-root PCI express system identifies resources from a lower performing root complex port and reassigns those resources to the higher performing root complex. The system does not change the number of PCI Express lanes, the resources each root complex uses may be reassigned to allow those resources to be translated to available credits for an endpoint. For example, in one embodiment, two root complexes are configured as x8 root complexes with the root complex resources distributed across the two root complexes based upon the usage of the root complex resources. | 2008-12-04 |
20080301351 | COMMUNICATION METHOD OF HOST APPARATUS CAPABLE OF CONNECTING WITH DEVICE BY USING WIRELESS UNIVERSAL SERIAL BUS AND WIRELESS CONNECTION SYSTEM INCLUDING HOST APPARATUS AND DEVICE - A communication method of a host apparatus capable of connecting with a device by using a Wireless Universal Serial Bus (WUSB) includes operations of receiving a connection request signal from the device to be connected to the host apparatus, according to a determination of whether a request to perform an operation in the device occurs in the host apparatus, selectively responding to the connection request signal to connect the device thereto, and performing data communication with the device to perform the operation. According to the communication method, the host apparatus is connected to the device when the host apparatus uses the device, to improve effective and convenient use of the device. | 2008-12-04 |
20080301352 | BUS ARCHITECTURE - A system and method for implementing a bus. In one embodiment, the system includes a bus switch operative to couple to a bus, and a plurality of trace segments coupled to the bus switch, where the trace segments have different lengths. The bus switch is operative to connect one of the trace segments to the bus based on at least one system requirement, and the selected trace segment cancels signal reflections on the bus. | 2008-12-04 |
20080301353 | Boosting throughput of a computer file server - A software layer for boosting the throughput of a computer file server by reducing the number of required mechanical accesses to the physical storage is provided. The throughput boost is achieved through the combination of extending the data requests along the file path and inserting double-buffered paths in front of each file accessed. The software layer resides on top of the file system, where it can extend requests along the file path, work with network requests arriving over any network using any protocol, and work with any storage system attached to the server. The software layer can also be used in a server to accelerate requests made by local applications in the server or it may be used in any other computer to accelerate requests made by local applications that require data from local storage. | 2008-12-04 |
20080301354 | Multi-Processor Circuit with Shared Memory Banks - A plurality of processors ( | 2008-12-04 |
20080301355 | FLASH MEMORY INFORMATION READING/WRITING METHOD AND STORAGE DEVICE USING THE SAME - A flash memory information read/write method in which an external resource such as host, external memory, EEPROM, or external controller is used to read and update new flash memory information after fabrication of a flash memory device, enabling the new flash memory information to be written in a predetermined address in a flash memory module of the flash device by a controller of the flash memory device, so that every flash memory device that has an erroneous or damaged factory data or information is still usable, and the flash memory controller provider needs not to continuously develop new firmware controllers for different flash memories. | 2008-12-04 |
20080301356 | FAST WRITING NON-VOLATILE MEMORY - A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table. | 2008-12-04 |
20080301357 | NON-VOLATILE MEMORY WITH AUXILIARY ROTATING SECTORS - A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories. | 2008-12-04 |
20080301358 | Electronic device that Downloads Operational Firmware from an External Host - An electronic device comprises an interface unit, a control circuit and a microprocessor. The interface unit receives a first operational firmware from a host. The control circuit transfers the first operational firmware to a memory. The microprocessor executes the first operational firmware which stored in the memory. The microprocessor controls operations of the electronic device according to the first operational firmware. And the control circuit is electrically coupled to a non-volatile memory which stores a second operational firmware for performing a specific function also performed by the first operational firmware. | 2008-12-04 |
20080301359 | Non-Volatile Memory and Method With Multi-Stream Updating - In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead. | 2008-12-04 |
20080301360 | Random Access Memory for Use in an Emulation Environment - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures. | 2008-12-04 |
20080301361 | Dedicated flow manager between the processor and the random access memory - The invention proposes a flow manager between the main processor and the random access memory that improves performances and security with a memory access management interface processor positioned in interface between the main processor and the random access memory, this memory access management interface processor selecting the relevant flow characteristics with which it feeds an interface dedicated storage unit, the interface dedicated storage unit being only accessible by the memory access management interface processor, the embodiment of this invention may be either hardware or logic. | 2008-12-04 |
20080301362 | Content addressable memory address resolver - Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison. | 2008-12-04 |
20080301363 | VIRTUAL TAPE LIBRARY DEVICE - A storage device system comprises interfaces connected to computers, a plurality of magnetic disks, and a control device that controls the plurality of magnetic disks. When a command from one of the computers instructing a tape library device to load a magnetic tape into a tape device is received by one of the interfaces, the control device selects a storage region that is managed as a virtual tape from among storage regions of the magnetic disks. When one of the interfaces receives an access request from the computer to the tape device, the control device controls to access the storage region selected. | 2008-12-04 |
20080301364 | CACHING OF MICROCODE EMULATION MEMORY - A processor includes a cache hierarchy including a level-1 cache and a higher-level cache. The processor maps a portion of physical memory space to a portion of the higher-level cache, executes instructions, at least some of which comprise microcode, allows microcode to access the portion of the higher-level cache, and prevents instructions that do not comprise microcode from accessing the portion of the higher-level cache. The first portion of the physical memory space can be permanently allocated for use by microcode. The processor can move one or more cache lines of the first portion of the higher-level cache from the higher-level cache to a first portion of the level-1 cache, allow microcode to access the first portion of the first level-1 cache, and prevent instructions that do not comprise microcode from accessing the first portion of the first level-1 cache. | 2008-12-04 |
20080301365 | Storage unit and circuit for shaping communication signal - The present invention relates to a storage unit comprising: a channel control portion for receiving a data input/output request; a cache memory for storing data; a disk control portion for performing input/output processing on data in accordance with the data input/output request; and a plurality of disk drives for storing data, wherein at least two of the disk drives input data to and output it from the disk control portion at different communication speeds. Further, the storage unit has a plurality of communication paths provided to connect at least one of the disk drives in such a manner as to constitute a loop defined by the FC-AL fiber channel standards, so that the communication speeds can be set differently for these different communication paths. | 2008-12-04 |
20080301366 | RAID SYSTEM AND DATA TRANSFER METHOD IN RAID SYSTEM - There is provided a novel storage system in which the number of signal lines will not increase even if the number of storage devices to be connected in a RAID system increases, and a novel data transfer method to enable a high-speed data transfer even when the transfer rate of the IDE device side is low. A RAID system ( | 2008-12-04 |
20080301367 | WAVEFORM CACHING FOR DATA DEMODULATION AND INTERFERENCE CANCELLATION AT A NODE B - The present patent application discloses a method and apparatus for using external and internal memory for cancelling traffic interference comprising storing data in an external memory; and processing the data samples on an internal memory, wherein the external memory is low bandwidth memory; and the internal memory is high bandwidth on board cache. The present method and apparatus also comprises caching portions of the data on the internal memory, filling the internal memory by reading the newest data from the external memory and updating the internal memory; and writing the older data back to the external memory from the internal memory, wherein the data is incoming data samples. | 2008-12-04 |
20080301368 | Recording controller and recording control method - Upon retrieving, after occurrence of replacement of a first cache, move out (MO) data that is a write back target, a second cache determines, based on data that is set in a control flag of a register, whether a new registration process of move in (MI) data with respect to a recording position of the MO data is completed. Upon determining that the new registration process is not completed, the second cache cancels the new registration process to ensure that a request of the new registration process is not output to a pipeline. | 2008-12-04 |
20080301369 | PROCESSING OF SELF-MODIFYING CODE IN MULTI-ADDRESS-SPACE AND MULTI-PROCESSOR SYSTEMS - A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page of primary code stored in a memory storage unit. The central processing unit may execute cached instructions from the cache until a serialization operation is executed. The central processing unit may check in a message queue for a notification message indicating potential storing to the page. If the notification message is present in the message queue, cached instructions from the page are invalidated. | 2008-12-04 |
20080301370 | Memory Module - A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive a data signal and an output to provide an amplified data signal. The memory component comprises an input to receive the amplified data signal, wherein the data item is stored in the memory component in dependence on a level of the received amplified data signal. | 2008-12-04 |
20080301371 | Memory Cache Control Arrangement and a Method of Performing a Coherency Operation Therefor - A memory cache control arrangement for performing a coherency operation on a memory cache comprises a receive processor for receiving an address group indication for an address group comprising a plurality of addresses associated with a main memory. The address group indication may indicate a task identity and an address range corresponding to a memory block of the main memory. A control unit processes each line of a group of cache lines sequentially. Specifically it is determined if each cache line is associated with an address of the address group by evaluating a match criterion. If the match criterion is met, a coherency operation is performed on the cache line. If a conflict exists between the coherency operation and another memory operation the coherency means inhibits the coherency operation. The invention allows a reduced duration of a cache coherency operation. The duration is further independent of the size of the main memory address space covered by the coherency operation. | 2008-12-04 |
20080301372 | Memory access control apparatus and memory access control method - A memory access control apparatus includes an MIB for storing information on a plurality of requests and processing the requests in parallel. Upon receipt of a memory access request, the MIB selects a request for a data block to be processed corresponding to the same set of a data block to be processed in response to the memory access request, and outputs a WAY assigned to the selected request to a replace-WAY selecting unit. The replace-WAY selecting unit excludes the WAY output from the MIB, and selects a WAY to be assigned to the memory access request based on a predetermined algorithm. | 2008-12-04 |
20080301373 | TECHNIQUE FOR CACHING DATA TO BE WRITTEN TO MAIN MEMORY - A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory. | 2008-12-04 |
20080301374 | STRUCTURE FOR DYNAMIC LIVELOCK RESOLUTION WITH VARIABLE DELAY MEMORY ACCESS QUEUE - A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes. These processes include dynamically configuring the delay queue within the processor into one of two different configurations and changing the sequence and timing of handling memory access instructions, based on the specific configuration of the delay queue. | 2008-12-04 |
20080301375 | Method, Apparatus, and Program to Efficiently Calculate Cache Prefetching Patterns for Loops - A mechanism is provided that identifies instructions that access storage and may be candidates for catch prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, data gathering, and validation. In the normal mode, the instruction merely performs the function specified in the software runtime environment. An instruction in unexecuted mode, upon the next execution, is placed in data gathering mode. When an instruction in the data gathering mode is encountered, the mechanism of the present invention collects data to discover potential fixed storage access patterns. When an instruction is in validation mode, the mechanism of the present invention validates the presumed fixed storage access patterns. | 2008-12-04 |
20080301376 | Method, Apparatus, and System Supporting Improved DMA Writes - A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation. | 2008-12-04 |
20080301377 | DATA PROCESSING SYSTEM, CACHE SYSTEM AND METHOD FOR UPDATING AN INVALID COHERENCY STATE IN RESPONSE TO SNOOPING AN OPERATION - A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requestor that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor. | 2008-12-04 |
20080301378 | TIMESTAMP BASED TRANSACTIONAL MEMORY - A hardware implemented transactional memory system includes a mechanism to allow multiple processors to access the same memory system. A set of timestamps are stored that each correspond to a region of memory. A time stamp is updated when any memory in its associated region is updated. For each memory transaction, the time at which the transaction begins is recorded. Write operations that are part of a transaction are performed by writing the data to temporary memory. When a transaction is to be recorded, the hardware automatically commits the transaction by determining whether the timestamps associated with data read for the transaction are all prior to the start time for the transaction. In this manner, the software need not check the data for all other processes or otherwise manage collision of data with respect to different processes. The software need only identify which reads and writes are part of a transaction. | 2008-12-04 |
20080301379 | Shared memory architecture - Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes. | 2008-12-04 |
20080301380 | Data Processor - To provide editing processing that can shorten a data stream editing processing time. | 2008-12-04 |
20080301381 | DEVICE AND METHOD FOR CONTROLLING COMMANDS USED FOR FLASH MEMORY - A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a command represented by the received information from the system memory, and generating an interrupt representing that all the commands are received, when receiving of substantially all the commands represented by the received information is completed. | 2008-12-04 |
20080301382 | Storage system construction managing device and construction management method - The device of the present invention manages changes in the construction of a storage system in a unified manner, and optimally disposes resources. The servers are logically divided into a plurality of virtual servers, the switches are logically divided into a plurality of zones, and the storage devices are logically divided into a plurality of virtual storage devices. The respective logical devices are respectively managed by respective managing parts. These respective managing parts are connected to a managing device via a network used for management. The managing device re-disposes resources in application program units on the basis of the load states of the respective resources in the storage system. | 2008-12-04 |
20080301383 | Multiple access for parallel turbo decoder - A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding. | 2008-12-04 |
20080301384 | Logging and Storing of a Sequence of Image Frame Data for Optimal Recovery After Power Failure - A method of logging and storing of a sequence of acquired X-ray image frame data in an X-ray imaging lab includes logging and updating image frame data related information in a non-volatile memory on a real-time basis upon completion of storage of each image frame data and deleting the logged information upon completion of storage of the sequence of X-ray image frames. | 2008-12-04 |
20080301385 | STORAGE CONTROLLER AND CONTROL METHOD FOR THE SAME - An object of the invention is to provide a storage controller and control method that can efficiently and easily prevent reduced data I/O processing performance due to an imbalance between loads on controllers. In the storage controller and control method for providing, to a host computer, logical volumes created in a storage area provided by a storage device and controlling data I/O to/from the logical volumes, the state of loads on the control units for controlling data I/O to/from the logical volumes is monitored, and a control unit allocated to a logical volume is changed to another control unit to equalize loads on the control units. | 2008-12-04 |
20080301386 | REMOTE COPY SYSTEM AND REMOTE COPY CONTROL METHOD - Providing a remote copy system for performing remote copy between a plurality of sites each constituted by a plurality of storage subsystems, wherein even if sub-data volumes at the remote site belong to the different storage subsystems, the update order of data copied from the main site to these sub-data volumes can be maintained in these sub-data volumes. Pieces of update data for a plurality of primary data volumes at the main site are sequenced and collectively stored in a common primary journal volume, the pieces of update data in the primary journal volume are remote-copied to a sub-journal volume shared by a plurality of storage subsystems at the remote site, the pieces of update data in the sub-journal volume are sorted in a time order and allocated to a plurality of sub-data volumes belonging to different storage subsystems to be written therein. | 2008-12-04 |
20080301387 | METHOD AND ARRANGEMENT FOR SECURING USER-DEFINABLE DATA OF A FRANKING MACHINE - In a method for data backup of a franking machine in which, in a data backup step, a connection is established between the franking machine and a remote data center via a communication network, data stored in the franking machine are transmitted to the data center as backup data in a transmission step, and the backup data are stored in the data center in a storage step. The backup data include user-definable configuration data of the franking machine that are definable by the user of the franking machine for configuration of the franking machine. | 2008-12-04 |
20080301388 | INFORMATION PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM - An information processing apparatus includes a restriction section, an acquisition section and a change section. The restriction section restricts maximum amount of stored data to be stored in each of information storage area in response to a reference value predetermined to each of information storage area. The acquisition section acquires relevant information about the stored data stored in each of the information storage area. The change section that changes the reference value determined to each of the information storage areas based on the acquired relevant information. | 2008-12-04 |
20080301389 | MEMORY-PROTECTION METHOD AND APPARATUS - A memory-protection method and apparatus is provided that can protect a memory that is used by components in a real time operating system environment (RTOS). The memory-protection method includes requesting access to a first memory region that a first component uses when the first component is called to execute a first task in a real time operating system, and permitting the first task to access the first memory region with reference to a task list that includes information on tasks which are permitted to access the first memory region. | 2008-12-04 |
20080301390 | System and method for managing addresses in a computing system - A method for retrieving and managing addresses is provided. The steps may include of receiving, at a first buffer of m buffers, a request for an address; obtaining the address from a corresponding first register of the m registers; sending the address, received by said obtaining, to a destination; storing the address, received by the obtaining, in the first buffer; and clearing the contents of a second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of said first buffer, wherein m is a positive integer. | 2008-12-04 |
20080301391 | METHOD AND APPARATUS FOR MODIFYING A BURST LENGTH FOR SEMICONDUCTOR MEMORY - A method and apparatus for performing a burst access operation for a memory device. The method includes receiving a burst access command for the burst access operation and receiving a burst length modifying value for the burst access operation. A modified burst length is generated from a pre-programmed burst length using the burst length modifying value. The modified burst length is used for the burst access operation without changing the pre-programmed burst length. The burst access operation is performed with the modified burst length. | 2008-12-04 |
20080301392 | SYSTEM AND DEVICE HAVING ALTERNATIVE BIT ORGANIZATION - A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is commonly connected to the first and second memory devices via a command/address bus, and is connected to the first memory device via a data bus separate from the command/address bus and having an upper half and a lower half. However, the CPU is connected to the second memory device via only the upper half of the data bus. | 2008-12-04 |
20080301393 | APPARATUS AND METHOD OF PROCESSING DATA OF NON-VOLATILE MEMORY - The invention relates to an apparatus and method of processing data of a non-volatile memory, and more particularly, to an apparatus and method of processing data of a non-volatile memory that is capable of applying a writing unit operation to a plurality of sectors. | 2008-12-04 |
20080301394 | Method And A System To Determine Device Criticality During SAN Reconfigurations - A method, a system and a computer program for determining device criticality during SAN reconfiguration operations comprising the steps of building the SAN connectivity graph and mapping the reconfiguration on SAN connectivity graph; locating the affected host systems; and determining the device criticality for each of the affected host systems. The hosts systems may also be provided with impact analysis agents to generate device criticality on host systems and a central agent to aggregate the device criticality from impact analysis agent and provide feedback to data center administrator. | 2008-12-04 |
20080301395 | SOFTWARE DEVELOPMENT FOR PARALLEL PROCESSING SYSTEMS - Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device is identified and allocated for storage of data associated with the user-entered data declaration. | 2008-12-04 |
20080301396 | DYNAMIC LOGICAL MAPPING - Dynamic logical mapping (“DLM”) provides a virtual layer interposed between a host and a data storage library. Residing on the library, DLM creates a data storage map that records and manages the relationship between a storage cartridge's physical address and that cartridge's mapping to a logical address. During runtime of the data storage library, DLM manages the physical to logical address mapping of each storage cartridge so as to optimize efficiency and speed of the data storage library. | 2008-12-04 |
20080301397 | Method and arrangements for utilizing NAND memory - A method of utilizing NAND type memory is disclosed herein. Operating system type instructions executable by a processor can be stored in a NAND based memory. The instructions can have logical addresses that can be utilized by the processor to fetch the operating system instructions. The method can store address conversions in the NAND based memory, where the address conversions can relate logical addresses to a physical address. At least one validity flag can be assigned to the address conversions. The processor can perform a direct read of the operating system instructions from the NAND based memory in response to a first setting of a validity flag and the processor can perform an indirect read of the operating system instructions by fetching an address conversion from the NAND based memory in response to a second setting of the at least one validity flag. | 2008-12-04 |
20080301398 | LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES - Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed. | 2008-12-04 |
20080301399 | PREFETCHING APPARATUS, PREFETCHING METHOD AND PREFETCHING PROGRAM PRODUCT - The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a program, includes: a history recorder, for recording a history for a plurality of data readings issued by the program while performing data reading; a prefetching generator, for generating a plurality of prefetchings that correspond to the plurality of data readings recorded in the history; a prefetching process determination unit, for determining, based on the history, the performance order for the plurality of prefetchings; and a prefetching unit, for performing, when following the determination of the performance order the program is executed, the plurality of prefetchings in the performance order. | 2008-12-04 |
20080301400 | Method and Arrangement for Efficiently Accessing Matrix Elements in a Memory - The invention relates to a method for accessing matrix elements, wherein accesses to two matrix elements that are adjacent in a row or in a column of a matrix and that are each specified by a respective relative address (a | 2008-12-04 |
20080301401 | Processor - A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit. | 2008-12-04 |
20080301402 | Method and System for Stealing Interrupt Vectors - A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In response to copying the operating system interrupt handlers into the reserved space in the allocated block of memory, custom interrupt handlers from the kernel module are copied over the operating system interrupt handlers in the interrupt vector memory location. The custom interrupt handlers after being copied into the interrupt vector memory location handle all interrupts received by the operating system. | 2008-12-04 |
20080301403 | SYSTEM FOR INTEGRITY PROTECTION FOR STANDARD 2N-BIT MULTIPLE SIZED MEMORY DEVICES - An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data. | 2008-12-04 |
20080301404 | METHOD FOR CONTROLLING AN ELECTRONIC CIRCUIT AND CONTROLLING CIRCUIT - A method for controlling an electronic circuit including selecting at least one pre-stored generating rule from a plurality of pre-stored generating rules according to which a message which is to be transmitted to the electronic circuit for carrying out a controlling function to control the electronic circuit is to be generated, and generating the message according to the at least one selected generating rule. | 2008-12-04 |
20080301405 | SYSTEM AND METHOD FOR AUTOMATICALLY SEGMENTING AND POPULATING A DISTRIBUTED COMPUTING PROBLEM - The initial partitioning of a distributed computing problem can be critical, and is often a source of tedium for the user. A method is provided that automatically segments the problem into fixed sized collections of original program cells (OPCs) based on the complexity of the problem specified, and the combination of computing agents of various caliber available for the overall job. The OPCs that are on the edge of a collection can communicate with OPCs on the edges of neighboring collections, and are indexed separately from OPCs that are within the ‘core’ or inner non-edge portion of a collection. Consequently, core OPCs can iterate independently of whether any communication occurs between collections and groups of collections (VPPs). All OPCs on an edge have common dependencies on remote information (i.e., their neighbors are all on the same edge of a neighboring collection). | 2008-12-04 |
20080301406 | SYSTEM AND METHOD FOR ALLOCATING COMMUNICATIONS TO PROCESSORS IN A MULTIPROCESSOR SYSTEM - In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific | 2008-12-04 |
20080301407 | Resolving A Layer 3 Address In A Processor System With A Unified IP Presence - Resolving a Layer 3 address includes maintaining an address resolution table at each slave processor of a number of slave processors. The slave processors have a master processor, and the master processor and the slave processors are associated with a unified address. An address resolution table includes one or more Layer 2-Layer 3 address mappings. An address resolution request requesting a Layer 2 address corresponding to a Layer 3 address is sent from a slave processor. The address resolution request uses the unified address. An address resolution response comprising the Layer 2 address is received at the master processor. The master processor sends the response to the slaves. | 2008-12-04 |
20080301408 | SYSTEM COMPRISING A PLURALITY OF PROCESSORS AND METHOD OF OPERATING THE SAME - A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables. | 2008-12-04 |
20080301409 | SCHEDULING THREADS IN A PROCESSOR - The invention provides a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of those instructions defining a memory access operation. The processor comprises: a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer; an instruction issue stage for issuing instructions from the instruction buffers; and a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage. The memory access stage comprises: detecting logic adapted to detect whether a memory access operation is defined in each issued instruction; and instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected. | 2008-12-04 |
20080301410 | Processor Configured for Operation with Multiple Operation Codes Per Instruction - A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given instruction. Thus, the same instruction is produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. The assignment of multiple operation codes to a given instruction may occur in conjunction with the design of the processor, and dynamic selection of a particular one of those operation codes may be performed in conjunction with assembly of code for execution by the processor. | 2008-12-04 |
20080301411 | INVERTING DATA ON RESULT BUS TO PREPARE FOR INSTRUCTION IN THE NEXT CYCLE FOR HIGH FREQUENCY EXECUTION UNITS - A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit. | 2008-12-04 |
20080301412 | High speed multiplexer - According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate. | 2008-12-04 |
20080301413 | Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing - A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline, wherein the length of the pipeline stages and the order of the stages varies from time to time and from application to application, admirably handling the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like with unprecedented performance, cost and power savings, and with full application flexibility. | 2008-12-04 |
20080301414 | Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture - Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described. | 2008-12-04 |
20080301415 | INFORMATION PROCESSING SYSTEM - An information processing system includes a first processor that accesses a first memory, a second processor that accesses a second memory, and a data transfer unit for executing data transfer between the first memory and the second memory. The first processor executes functions of translating an instruction out of instructions included in the program except a memory access instruction into an instruction for the second processor and translating the memory access instruction into an instruction sequence containing a call instruction of the program to transfer the access data on the first memory to the second memory via a data transfer unit. | 2008-12-04 |
20080301416 | SYSTEM AND PROGRAM PRODUCT OF DOING PACK UNICODE Z SERIES INSTRUCTIONS - Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a byte-by-byte fashion as a way to provide superior performance in the face of the usual challenges facing the execution of emulated data processing machine instructions as opposed to native instructions. | 2008-12-04 |
20080301417 | System and Method for Debugging of Computer - The present invention relates to debugging of computer programs, and in particular to bi-directional debugging. | 2008-12-04 |
20080301418 | TRACING COMMAND EXECUTION IN A PARALLEL PROCESSING SYSTEM - Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory. | 2008-12-04 |