49th week of 2008 patent applcation highlights part 46 |
Patent application number | Title | Published |
20080299713 | Thin film transistor (TFT) and flat panel display including the TFT and their methods of manufacture - A Thin Film Transistor (TFT) reduces interconnection resistance of source/drain electrodes, prevents contamination from an active layer, reduces contact resistance between a pixel electrode and the source/drain electrodes, smoothly supplies hydrogen to the active layer and has high mobility, on-current characteristics, and threshold voltage characteristics. The TFT includes an active layer having a channel region and source/drain regions, a gate electrode supplying a signal to the channel region, source/drain electrodes respectively connected to the source/drain regions and including at least one of Ti, a Ti alloy, Ta, and a Ta alloy; and an insulating layer interposed between the source/drain electrodes and the active layer and including silicon nitride. | 2008-12-04 |
20080299714 | Planar Combined Structure of a Bipolar Junction Transistor and N-type/P-type Metal Semiconductor Field-Effect Transistors and Method for Forming the Same - A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. | 2008-12-04 |
20080299715 | Method of Fabricating Self Aligned Schotky Junctions For Semiconductors Devices - A method of fabricating a self-aligned Schottky junction ( | 2008-12-04 |
20080299716 | DISTRIBUTED HIGH VOLTAGE JFET - A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET. | 2008-12-04 |
20080299717 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE - A semiconductor device ( | 2008-12-04 |
20080299718 | DAMASCENE PROCESS HAVING RETAINED CAPPING LAYER THROUGH METALLIZATION FOR PROTECTING LOW-K DIELECTRICS - A method of forming single or dual damascene interconnect structures using either a via-first or trench first approach includes the steps of providing a substrate surface having an etch-stop layer thereon, a low-k dielectric layer on the etch-stop layer, and a dielectric capping layer on the low-k dielectric layer. In the single damascene process using trench pattern, a trench is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the via-first process, using a via pattern, the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the trench first process, using the via pattern the via is etched through the capping layer, the low-k dielectric layer and the etch-stop layer to reach the substrate surface. In the single damascene or either via-first or trench-first dual damascene embodiment, the capping layer is retained over the low-k dielectric layer on top surfaces of the trench into the metal processing, generally including CMP processing, wherein the CMP process removes at least a portion, and in one embodiment the entire, capping layer. | 2008-12-04 |
20080299719 | MOSFET-type semiconductor device, and method of manufacturing the same - A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a gate insulating film, source and drain regions formed at the both ends of the semiconductor layer, a first metal-semiconductor compound layer formed on one of the side walls of each of source and drain regions of the semiconductor layer, and a second metal-semiconductor compound layer having a different composition and Shottky barrier height from that of the first metal-semiconductor compound layer on the other side wall of each of source and drain regions of the semiconductor layer. | 2008-12-04 |
20080299720 | STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION - A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used. | 2008-12-04 |
20080299721 | CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) TECHNOLOGY - A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region. | 2008-12-04 |
20080299722 | Manufacturing method for forming a recessed channel transistor, method for forming a corresponding integrated semiconductor memory device and corresponding self-aligned mask structure - The present invention provides a method for forming a recessed channel transistor comprising the steps of:
| 2008-12-04 |
20080299723 | METHODS FOR FORMING CAPACITOR STRUCTURES - A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor. | 2008-12-04 |
20080299724 | METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR - A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects. | 2008-12-04 |
20080299725 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices comprises forming an semiconductor layer of the first conduction type on a substrate of the first conduction type; forming an anti-oxidizing layer on the surface of the semiconductor layer of the first conduction type, the anti-oxidizing layer having an aperture only through a region for use in formation of a guard ring layer of the second conduction type; forming the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type through implantation of ions into a surface where said anti-oxidizing layer is formed; forming an oxide layer at least in the aperture; forming a base layer of the second conduction type adjacent to the guard ring layer of the second conduction type in the surface of the semiconductor layer of the first conduction type; and forming a diffused layer of the first conduction type through implantation of ions into the base layer of the second conduction type. | 2008-12-04 |
20080299726 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is elaborated. The photomask has a compensation pattern that compensates a deformation of a photo resist pattern caused by photo interference and a deformation of the ion implantation region diffused by heat treatment. Therefore extending direction of the gate electrode and the outer edge of the column region are substantially parallel. | 2008-12-04 |
20080299727 | Vertical trench gate transistor semiconductor device and method for fabricating the same - A first region functioning as a transistor includes a drain region, a body region formed over the drain region, a source region formed over the body region and a trench formed through the body region and having a gate electrode buried therein. A source region is formed over the body region extending in a second region. The source region forming an upper edge of the trench is rounded. | 2008-12-04 |
20080299728 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which readily etches the unreacted portion of the metal film and the sidewall spacer while hardly etching the device isolation region, resistance-reduced portions of the gate electrode and resistance-reduced portions of the source and drain regions. | 2008-12-04 |
20080299729 | METHOD OF FABRICATING HIGH VOLTAGE MOS TRANSISTOR DEVICE - A substrate is provided, and a sacrificial pattern having an opening partially exposing a high voltage device region is formed on the substrate. Subsequently, a gate oxide layer is formed in the opening, and the sacrificial pattern is removed. A gate electrode, and two heavily doped regions are formed. Than, a salicidation process is carried out to form salicides on the surface of the gate electrode and the heavily doped regions. | 2008-12-04 |
20080299730 | METAL OXYNITRIDE AS A pFET MATERIAL - A compound metal comprising MO | 2008-12-04 |
20080299731 | ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE - A nonvolatile storage cell, integrated circuit (IC) including the cells and method of manufacturing the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer. | 2008-12-04 |
20080299732 | METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS - A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor. | 2008-12-04 |
20080299733 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS IN A MATERIAL LAYER TO BE ETCHED - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation process is performed to create an ion-implanted portion in the material layer. An etch process adapted to remove the ion-implanted portion at a greater etch rate than other portions of the material layer is performed. | 2008-12-04 |
20080299734 | Method of manufacturing a self-aligned fin field effect transistor (FinFET) device - A method of manufacturing a self-aligned fin FET (FinFET) device is disclosed, in which, an insulating layer of a shallow trench isolation is etched back to partially expose sidewalls of the semiconductor substrate surrounded by the shallow trench isolation, and the sidewalls of the semiconductor substrate are then isotropically etched, allowing the semiconductor substrate to form into a relatively thin fin structure for forming a three-dimensional gate structure having three faces. | 2008-12-04 |
20080299735 | METHODS FOR FORMING A TRANSISTOR - Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity. | 2008-12-04 |
20080299736 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost. | 2008-12-04 |
20080299737 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma is decreased by forming an element having an LDD structure according to a manufacturing method of a semiconductor device using a hard mask. Covering the substrate by an electrically conductive film allover, the density of electric charge accumulated in a gate electrode in the plasma process such as anisotropic etching can be reduced, and the degradation due to plasma process can be reduced. | 2008-12-04 |
20080299738 | METHOD FOR FORMING INDUCTOR ON SEMICONDUCTOR SUBSTRATE - An inductor formed on a semiconductor substrate is provided in the present invention. The inductor includes a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer includes at least one insulator slot, and each insulator slot is encompassed in the metal layer. | 2008-12-04 |
20080299739 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing the plurality of silicon substrates to degas the oxide species in the first insulating film, and oxidizing the surface of the plurality of silicon substrates in a batch process after annealing the silicon substrates. | 2008-12-04 |
20080299740 | METHOD FOR FORMING STI STRUCTURE - A method for forming a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate, having a trench-like opening therein exposing a portion of the substrate. A thermal oxidation process is performed to the substrate. An anisotropic etching process is performed using the patterned mask layer as a mask to form a trench in the substrate, and then the trench is filled with an insulating material. | 2008-12-04 |
20080299741 | Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation - An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide. | 2008-12-04 |
20080299742 | Method for manufacturing SOI wafer - There is disclosed a method for manufacturing an SOI wafer comprising: a step of implanting at least one of a hydrogen ion and a rare gas ion into a donor wafer to form an ion implanted layer; a step of bonding an ion implanted surface of the donor wafer to a handle wafer; a step of delaminating the donor wafer at the ion implanted layer to reduce a film thickness of the donor wafer, thereby providing an SOI layer; and a step of etching the SOI layer to reduce a thickness of the SOI layer, wherein the etching step includes: a stage of performing rough etching as wet etching; a stage of measuring a film thickness distribution of the SOI layer after the rough etching; and a stage of performing precise etching as dry etching based on the measured film thickness distribution of the SOI layer. There can be provided A method for manufacturing an SOI wafer having high film thickness uniformity of an SOI layer with excellent productivity. | 2008-12-04 |
20080299743 | Manufacturing method of semiconductor device - To provide a semiconductor device with high performance and low cost and a manufacturing method thereof. A first region including a separated (cleavage) single-crystal semiconductor layer and a second region including a non-single-crystal semiconductor layer are provided over a substrate. It is preferable that laser beam irradiation be performed to the separated (cleavage) single-crystal semiconductor layer in an inert atmosphere, and laser beam irradiation be performed to the non-single-crystal semiconductor layer in an air atmosphere at least once. | 2008-12-04 |
20080299744 | Manufacturing method of semiconductor substrate and semiconductor device - It is an object of the present invention to obtain a large-sized SOI substrate by providing a single-crystal silicon layer over a large-sized glass substrate in a large area. After a plurality of rectangular single-crystal semiconductor substrates each provided with a separation layer are aligned over a dummy substrate and both of the substrates are fixed with a low-temperature coagulant, the plurality of single-crystal semiconductor substrates are bonded to a support substrate; the temperature is raised up to a temperature, at which the low-temperature coagulant does not to have a bonding effect, so as to isolate the dummy substrate and the single-crystal semiconductor substrates; heat treatment is performed to separate part of the single-crystal semiconductor substrates, along a boundary of the respective separation layers; and single-crystal semiconductor layers are provided over the support substrate. | 2008-12-04 |
20080299745 | WAFER SEPARATING METHOD - A wafer separating method including a laminated member removing step for partially removing a laminated member of a wafer along streets by applying a laser beam to the wafer along the streets, and a cutting step for cutting a substrate of the wafer along the streets after the laminated member removing step. The laminated member removing step includes a first laser processing step for applying a first laser beam along two parallel lines spaced apart from each other in each street, the first laser beam being capable of passing through the laminated member and having an absorption wavelength to the substrate, thereby heating the substrate to generate two cracks in the laminated member by thermal shock so that the two cracks extend along the two parallel lines in each street; and a second laser processing step for applying a second laser beam to a region between the two cracks in the laminated member, the second laser beam having an energy density higher than that of the first laser beam, thereby removing the region between the two cracks in the laminated member to expose the substrate along each street. | 2008-12-04 |
20080299746 | Semiconductor Substrate Fabrication Method - A semiconductor substrate fabrication method according to the first aspect of this invention is characterized by including a preparation step of preparing an underlying substrate, a stacking step of stacking, on the underlying substrate, at least two multilayered films each including a peeling layer and a semiconductor layer, and a separation step of separating the semiconductor layer. | 2008-12-04 |
20080299747 | METHOD FOR FORMING AMORPHOUSE SILICON FILM BY PLASMA CVD - A method includes introducing a silicon-containing source gas and a dilution gas to a reactor to deposit an amorphous silicon film on a substrate by plasma CVD; and adjusting a compressive film stress to 300 MPa or less and a uniformity of film thickness within the substrate surface to ±5% or less of the amorphous silicon film depositing on the substrate as a function of a flow rate of the source gas, a flow rate of the dilution gas, and a pressure of the reactor which are used as control parameters. | 2008-12-04 |
20080299748 | Group III-V Crystal - Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film ( | 2008-12-04 |
20080299749 | CLUSTER ION IMPLANTATION FOR DEFECT ENGINEERING - A method of semiconductor manufacturing is disclosed in which doping is accomplished by the implantation of ion beams formed from ionized molecules, and more particularly to a method in which molecular and cluster dopant ions are implanted into a substrate with and without a co-implant of non-dopant cluster ion, such as a carbon cluster ion, wherein the dopant ion is implanted into the amorphous layer created by the co-implant in order to reduce defects in the crystalline structure, thus reducing the leakage current and improving performance of the semiconductor junctions. Dopant ion compounds of the form A | 2008-12-04 |
20080299750 | MULTIPLE MILLISECOND ANNEALS FOR SEMICONDUCTOR DEVICE FABRICATION - A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time. | 2008-12-04 |
20080299751 | SCHOTTKY DIODE AND METHOD THEREFOR - In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance. | 2008-12-04 |
20080299752 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - Provided is a fabrication method of a semiconductor device having an improved production yield. | 2008-12-04 |
20080299753 | Peripheral Gate Stacks and Recessed Array Gates - Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array. | 2008-12-04 |
20080299754 | Methods for forming MOS devices with metal-inserted polysilicon gate stack - A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a metal-containing layer on the gate dielectric; and forming a composite layer over the metal-containing layer. The step of forming the composite layer includes forming an un-doped silicon layer substantially free from p-type and n-type impurities; and forming a silicon layer adjoining the un-doped silicon layer. The step of forming the silicon layer comprises in-situ doping a first impurity. (or need to be change to: forming a silicon layer first & then forming un-doped silicon layer) The method further includes performing an annealing to diffuse the first impurity in the silicon layer into the un-doped silicon layer. | 2008-12-04 |
20080299755 | METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING A CHLORINE CURED TUNNEL OXIDE LAYER - Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure. | 2008-12-04 |
20080299756 | METHOD AND APPARATUS FOR PLATING A SEMICONDUCTOR PACKAGE - A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices. | 2008-12-04 |
20080299757 | Wafer structure and method for fabricating the same - A wafer structure and a method for fabricating the same are provided. First, a wafer having a pad and a first protection layer with a first opening is provided. Next, a second protection layer with a second opening is formed on the first protection layer. Part of the pad and the first protection layer are exposed from the openings. The edges of the openings construct a step structure. Following that, an adhesion layer is formed on the pad, the step structure and the second protection layer. Afterwards, a photo-resist layer with a third opening is formed on the adhesion layer. Then, a barrier layer is electroplated onto part of the adhesion layer. Further, a wetting layer is formed on the barrier layer, and then the photo-resist layer and part of the adhesion layer exposed outside the barrier layer are removed. Finally, a solder layer is printed onto the wetting layer. | 2008-12-04 |
20080299758 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A high-density N-type diffusion layer | 2008-12-04 |
20080299759 | Method to form a via - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 2008-12-04 |
20080299760 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that of the silicon-based insulating film is | 2008-12-04 |
20080299761 | Interconnection process - An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole. | 2008-12-04 |
20080299762 | Method for forming interconnects for 3-D applications - A method for forming an interconnect, comprising (a) providing a substrate ( | 2008-12-04 |
20080299763 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - After a first insulating film is formed on a substrate, a wiring groove is formed in the first insulating film, and then a wire is formed inside the wiring groove. Subsequently, a protection film is formed on the first insulating film and on the wire, and then a hard mask film is formed on the protection film. After that, the hard mask film is patterned. Subsequently, the protection film and the first insulating film are partially removed using the patterned hard mask film to form an air gap groove, and then a second insulating film is formed to close an upper portion of the air gap groove for forming an air gap. | 2008-12-04 |
20080299764 | Interconnection having dual-level or multi-level capping layer and method of forming the same - An interconnection having a dual-level and multi-level capping layer and a method of forming the same. The interconnection may include an interlayer dielectric layer with a groove formed therein, a metal layer formed within the groove, a metal compound layer on the metal layer, a first barrier layer on the interlayer dielectric layer, and a second barrier layer on both the metal compound layer and the first barrier layer. | 2008-12-04 |
20080299765 | Method of Fabricating a Structure for a Semiconductor Device - There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapour deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via. | 2008-12-04 |
20080299766 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing. | 2008-12-04 |
20080299767 | Method for Forming a Semiconductor Device Having a Salicide Layer - A method for forming a semiconductor device and selectively forming a salicide layer is described. In one embodiment, the method includes depositing a metal layer over a semiconductor substrate having a first area and a second area, wherein the first area and the second area include silicon, removing the metal layer over the second gate electrode, and reacting the metal layer with the first area to form a salicide layer over the first area. In one embodiment, the first area and the second area include a first gate electrode and a second gate electrode, respectively. | 2008-12-04 |
20080299768 | MANUFACTURING METHOD OF SUBSTRATE WITH THROUGH ELECTRODE - A manufacturing method of a substrate with through electrodes, comprising a substrate having through holes, and through electrodes received in the through holes, includes a through electrode formation step of forming the through electrodes on a support plate, a substrate formation step of forming the substrate, a through electrode reception step of stacking the substrate on the support plate | 2008-12-04 |
20080299769 | SEMICONDUCTOR FABRICATION METHOD SUITABLE FOR MEMS - A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film. | 2008-12-04 |
20080299770 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 2008-12-04 |
20080299771 | METHODS OF MAKING THIN FILM TRANSISTORS COMPRISING ZINC-OXIDE-BASED SEMICONDUCTOR MATERIALS AND TRANSISTORS MADE THEREBY - A method of making a thin film transistor comprising a thin film semiconductor element comprised of a transparent zinc-oxide-based semiconductor material, wherein spaced apart first and second contacts in contact with said material are position on either side of a channel in the thin film semiconductor element such that the elongated sides of the channel are aligned with an underlying gate structure. The method can be accomplished while maintaining the substrate temperature at no more than 300° C. during fabrication. | 2008-12-04 |
20080299772 | Methods of fabricating electronic devices using direct copper plating - The present invention relates to methods and structures for the metallization of semiconductor devices. One aspect of the present invention is a method of forming a semiconductor device having copper metallization. In one embodiment, the method includes providing a patterned wafer having a diffusion barrier for copper; depositing a copperless seed layer on the diffusion barrier effective for electrochemical deposition of gapfill copper. The seed layer is formed by a conformal deposition process and by a nonconformal deposition process. The method further includes electroplating copper gapfill onto the seed layer. Another aspect of the invention includes electronic devices made using methods and structures according to embodiments of the present invention. | 2008-12-04 |
20080299773 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes. | 2008-12-04 |
20080299774 | PITCH MULTIPLICATION USING SELF-ASSEMBLING MATERIALS - Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate. | 2008-12-04 |
20080299775 | GAPFILL EXTENSION OF HDP-CVD INTEGRATED PROCESS MODULATION SIO2 PROCESS - Methods are disclosed for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. A high-density plasma is formed from the silicon-containing gas, the oxygen-containing gas, and the fluent gas. A first portion of the silicon oxide film is deposited using the high-density plasma at a deposition rate between 900 and 6000 Å/min and with a deposition/sputter ratio greater than 30. The deposition/sputter ratio is defined as a ratio of a net deposition rate and a blanket sputtering rate to the blanket sputtering rate. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched. A second portion of the silicon oxide film is deposited over the etched portion of the silicon oxide film. | 2008-12-04 |
20080299776 | FREQUENCY DOUBLING USING SPACER MASK - A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask. | 2008-12-04 |
20080299777 | Silicon nitride film dry etching method - A silicon nitride film is dry etched by reactive ion etching using a mixed gas including a fluorine gas and an oxygen gas. | 2008-12-04 |
20080299778 | Silicon film dry etching method - A silicon film is dry etched by parallel plate type dry etching using a mixed gas including a fluorine gas and a chlorine gas. | 2008-12-04 |
20080299779 | SYSTEMS AND METHODS FOR CONTROLLING THE EFFECTIVE DIELECTRIC CONSTANT OF MATERIALS USED IN A SEMICONDUCTOR DEVICE - Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars. | 2008-12-04 |
20080299780 | Method and apparatus for laser oxidation and reduction - A method and apparatus using electromagnetic radiation and gas to create oxidation and reduction reactions on a device, such as a semiconductor wafer surface. In one embodiment, a scanned laser and gas may be employed in a number of oxidation and/or reduction reactions in a single system without using multiple pieces of equipment, corrosive chemicals and gases, high temperature and pressure chamber environments, waste treatment processes, and/or extra process steps typically required in existing processes. | 2008-12-04 |
20080299781 | METHOD OF FORMING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same. | 2008-12-04 |
20080299782 | Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds - The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR | 2008-12-04 |
20080299783 | SYSTEMS AND METHODS FOR PROCESSING SEMICONDUCTOR STRUCTURES USING LASER PULSES LATERALLY DISTRIBUTED IN A SCANNING WINDOW - Systems and methods process structures on or within a semiconductor substrate using a series of laser pulses. In one embodiment, a deflector is configured to selectively deflect the laser pulses within a processing window. The processing window is scanned over the semiconductor substrate such that a plurality of laterally spaced rows of structures simultaneously pass through the processing window. As the processing window is scanned, the deflector selectively deflects the series of laser pulses among the laterally spaced rows within the processing window. Thus, multiple rows of structures may be processed in a single scan. | 2008-12-04 |
20080299784 | APPARATUS AND METHOD FOR THERMALLY TREATING SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING WAFER FROM WARPING - A thermal treatment apparatus and method for processing a wafer are provided. The thermal treatment apparatus includes a process chamber for thermally treating the wafer, a heating unit for heating the wafer in the process chamber, and a gas supply unit for supplying a gas and controlling a gas pressure differently by sections of the wafer. The heating unit is provided in at least one of the upper side and the lower side of the process chamber. The heating unit includes a plurality of heater blocks capable of controlling a temperature for sections of the wafer. | 2008-12-04 |
20080299785 | Eccentric polygonal main lead flexible connector assembly - In one embodiment the present invention is a Flexible Connector Assemblies (FCA) | 2008-12-04 |
20080299786 | Sucking cover - A sucking cover inserted into an electric connector with terminals received therein includes a sucking portion and an insertion portion. The sucking portion has a sucking surface at the front and a catching surface at the rear. A plane sucking area is formed as a portion of the sucking surface. The sucking surface is parallel with a bottom plate of the electric connector mounted on a PCB. The catching surface is against the top of the electric connector when the sucking cover is inserted into the electric connector. The inserted portion projected from the catching surface has an inserted wall and ribs. While the inserted portion is inserted into an inserted slot of the electric connector, the electric connector can be moved while the sucked cover is moved. In SMT, this action will improve the effective of the electric connector located in a PCB. | 2008-12-04 |
20080299787 | Light emitting diode module for lighting - Provided is an LED module for lighting, which includes a printed circuit board (PCB); at least one or more LED elements mounted on the PCB; and a waterproof agent surrounding terminals between the PCB and the LED elements, which are exposed on mounting surface of the LED elements. | 2008-12-04 |
20080299788 | PLASTIC CARD PROVIDED WITH ELECTRICAL CONTACTS - The inventive plastic card ( | 2008-12-04 |
20080299789 | CIRCUIT DEVICE AND MANUFACTURING METHOD THEREFOR - A circuit device is made smaller in higher. The circuit device includes a wiring substrate, a first circuit element, and a second circuit element. The circuit substrate includes an insulating resin layer, a wiring layer provided on a main surface of the insulating resin layer, and a wiring layer provided on the other main surface of the insulating resin layer. The wiring layer includes first interconnectors to which the first circuit element connects, and wiring portions. The film thickness of the first interconnector is made thinner than that of the wiring portion. The wiring layer includes second interconnectors and wiring portions. The first interconnectors and the second interconnectors are connected through the medium of conductors. | 2008-12-04 |
20080299790 | METHOD OF ATTACHING ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT ATTACHING TOOL - An electronic component attaching tool suitable for an external shape of a semiconductor device is prepared. The electronic component attaching tool has a function of aligning a position of the semiconductor device to an IC socket. The electronic component attaching tool is mounted on the standard surface that is formed on the IC socket substantially regardless of the external shape of the semiconductor device. The semiconductor device is then aligned and attached to the IC socket by using the electronic component attaching tool, and the electronic component attaching tool is removed from the IC socket. Another electronic component attaching tool suitable for an external shape of another semiconductor device is prepared, and the same procedure as the above is performed to align and attach this semiconductor device to the same type IC socket. | 2008-12-04 |
20080299791 | Socket connector with improved base - An electrical connector ( | 2008-12-04 |
20080299792 | Burn-in socket having loading plate with uneven seating surface - A burn-in socket for receiving an IC package includes a base defining an opening for loading the IC package. A loading plate is mounted within the base. The loading plate has a seating surface with a number of holes defined therein. A contact socket is located under the loading plate. A number of contacts are received in the contact socket. Each contact has one end extending into the hole in the seating surface of the loading plate for contact with a solder ball of the IC package. The seating surface comprises at least one lower plane and at least one upper plane. At least the upper plane is formed with the holes. | 2008-12-04 |
20080299793 | Burn-in socket having pick-up arrangement for quickly pick-up IC package after IC package is tested - A burn-in socket for receiving an IC package ( | 2008-12-04 |
20080299794 | Electrical card connector assembly - An electrical card connector assembly includes an electrical card connector ( | 2008-12-04 |
20080299795 | Electrical connector with improved housing - An electrical connector ( | 2008-12-04 |
20080299796 | ELECTRICAL CONNECTOR - An electrical connector includes a socket and a plug. In the socket, plural first connectors are provided in parallel, and substantially U-shaped press-fitting portions are assembled so as to cross over opening edge portions of a socket body. In the plug, plural second connectors are provided in parallel, and substantially U-shaped press-fitting portions are assembled so as to cross over opening edge portions of a plug body. The plug body has a planar shape which can be fitted in the opening edge portions of the socket body. Particularly, a free end portion of the press-fitting portion of the second connector located in the opening edge portion of the plug body is engaged with a position regulating recess formed in a bottom surface of the plug body. | 2008-12-04 |
20080299797 | Electrical connector having an improved frame - An electrical connector adapted for connection an Integrated Circuit (IC) chip to a printed circuit board (PCB) includes an insulating housing having a plurality of passageways, a plurality of contacts received in the passageways and a frame moveable assembled on the housing to allow the IC chip to be inserted therein. The frame includes a first and second side walls parallel to each other and a third side wall connecting with ends of the first and second side walls without a sidewall opposite the third wall, thereby a hatch is defined opposite to the third wall. | 2008-12-04 |
20080299798 | Electrical junction box - An electrical junction box, which is assembled by first inserting a circuit board assembly into a primary housing via an opening of the primary housing, and after that inserting a secondary housing into the primary housing, includes a connector block that has a projection that widens the opening that has been narrowed. A plurality of ribs are formed on front and rear walls of the thin primary housing from the side of the opening in an insertion direction of the circuit board assembly. A concave groove formed between a pair of the projections engages with the rib of the front wall. The ribs on the rear wall are close to a circuit board of the circuit board assembly. The connector block has protuberances that abut against the ribs. | 2008-12-04 |
20080299799 | Electric junction box - The electric junction box includes: a wiring board; a connector block having a body part and terminals, the terminal penetrating through a bottom wall of the body part and one end part of the terminal being electrically connected to the wiring board; a case which is arranged above the bottom wall of the body part, has holes each of which allows an opposite end part of the terminal to pass therethrough so as to expose the terminal, and receives the wiring board and the connector block therein; and a drain part provided on an inner surface of the case so that water, which enters into the case from the hole and is drained from the connector block, moves downward along the inner surface of the case and is drained outside the case. | 2008-12-04 |
20080299800 | Electric junction box - It is object of the present invention to provide an electric junction box that can effectively drain liquid away therefrom. | 2008-12-04 |
20080299801 | Temperature-activated self-extending surface mount attachment structures - A surface mount component (for example, an electrical connector) includes a connector body portion and a plurality of temperature-activated self-extending surface mount attachment structures (TASESMAS). During a reflow solder process, amounts of solder within the connector melt. Surface and interfacial tensions of structures within the connector cause the TASESMAS structures to extend away from the connector body portion and toward an object (for example, a printed circuit board) to which the surface mount component is to be surface mount soldered. Each TASESMAS may self-extend a different amount to accommodate nonplanarities in the surface to which the component is to be surface mounted. When the component cools after reflow soldering, the amounts of solder solidify thereby fixing the TASESMAS structures in their extended positions. | 2008-12-04 |
20080299802 | BGA socket having extensible solder ball so as to compensate warpage connector housing - A solder ball is adapted for a ball grid array socket and comprises a core portion ( | 2008-12-04 |
20080299803 | Electrical card connector with a grounding plate - An electrical card connector includes an insulative header ( | 2008-12-04 |
20080299804 | PIVOT DISPLAY - A mobile electronic device including two planar panels that are typically suspended from one another and can assume a retracted position in which they substantially overlap one another and assume an extended position in which the panels do not completely overlap one another. In the extended position an additional portion of the elements of the user interface is exposed. | 2008-12-04 |
20080299805 | Connector of a double-sided connection type with a flexible internal mechanism - In a connector to be connected by press contact in a connecting direction, plural contacts are coupled to a first frame having two principal surfaces opposite to each other in the connecting direction. A second frame is coupled to the first frame and guides the first frame in a specific direction perpendicular to the connecting direction. Each of the contacts includes an insulating elastic member and a conductor combined with the elastic member. The conductor includes portions protruding from the principal surfaces, respectively. | 2008-12-04 |
20080299806 | Electrical card connector - An electrical card connector for receiving at least two electrical cards, comprises: an insulating housing; a shielding shell substantially enclosing the insulating housing; a front row of terminals and a rear row of terminals received in the insulating housing; an ejector receiving in one side of the insulating housing for ejecting two cards; wherein the front row of terminals are for connecting with one kind of electrical card and the front and the rear row of terminals together are for connecting with the other kind of electrical card. | 2008-12-04 |
20080299807 | Card connector - A card connector ( | 2008-12-04 |
20080299808 | ELECTRONIC DEVICE - An electronic device electrically connected to an external electronic component is provided. The electronic device comprises first conductors for contacting the external electronic component and a base. The base has holes with second conductors disposed on inner walls thereof and an elastic body having terminal receiving holes for receiving the first conductors. The first and second conductors and the elastic body are disposed at appropriate positions. When the external electronic device presses and contacts the first conductors, the elastic body is forced to deform, and the first conductors are made to move to contact the second conductors. As the elastic body has good elasticity, the first conductors after being compressed can contact the second conductors of the base, and thus soldering is not required, which facilitates the electrical connection to a chip module. | 2008-12-04 |
20080299809 | SMARTCONNECT FLASH CARD ADAPTER - A multi-memory media adapter having a port, a surface, and a set of contact pins adapted to connect to different types of flash cards. Signals are mapped to the contact pins depending upon the type of flash card. In one embodiment, a controller has signal lines connected to an interconnection means which connects wires, cables or traces to the sets of contact pins. Signals are mapped on the signal lines depending upon the type of flash card inserted. | 2008-12-04 |
20080299810 | Burn-in-socket having slider arrangments - A burn-in socket for receiving an IC package includes a base, a platform located within the base for loading the IC package, a number of contacts arranged in the base for connecting with the IC package, a cover movably mounted upon the base, and at least one slider arrangement actuated by the cover. The slider arrangement comprises a first rod pivotally connected to the cover, a slider capable of abutting against the IC package, and a second rod with one end pivotally connected to the first rod and the other end pivotally connected to the slider. | 2008-12-04 |
20080299811 | Power inlets and power connectors - In one embodiment, the power inlet has three terminals disposed in co-planar parallel alignment in a cavity of a housing of limited height as well as an asymmetrically located projection for polarization purposes. The power connector has three female contacts disposed in co-planar parallel alignment in a housing for mating with the terminals in the power inlet as well as an asymmetrically disposed groove for receiving the projection of the power inlet. A latching device has resilient arms that slide into the interior of the power inlet housing and lock at the ends in openings in the sides of the power inlet housing. | 2008-12-04 |
20080299812 | CONNECTOR - If resilient locking pieces ( | 2008-12-04 |