49th week of 2008 patent applcation highlights part 16 |
Patent application number | Title | Published |
20080296712 | Assembling Two Substrates by Molecular Adhesion - The invention relates to an assembly method to enable local electrical bonds between zones located on a face of a first substrate and corresponding zones located on a face of a second substrate, said faces being located facing each other, at least one of the substrates having a surface topography, characterised in that the method comprises steps consisting of:
| 2008-12-04 |
20080296713 | Image Sensor with Color Filters and Method of Manufacturing the Same - An image sensor with color filters capable of minimizing a distance through which incident light reaches photodiodes and flattening the color filters by minimizing step heights among color filters, and a method of manufacturing the same are provided. In the image sensor with the color filters, a metal is doped into an interlayer insulating SiO | 2008-12-04 |
20080296714 | Wafer level package of image sensor and method for manufacturing the same - Provided is a wafer level package of an image sensor capable of simply and easily packaging an image sensor in a packaging process, and a method for manufacturing the same. The wafer level package of an image sensor includes a lower substrate including an image sensor, a conductive pattern coupled to the image sensor, and a plurality of vias coupled to the conductive pattern; a micro lens array film having a plurality of micro lenses corresponding to the image sensor, the micro lenses being formed on the lower substrate; and a sealing line surrounding the image sensor while being spaced apart from the image sensor and being in contact with an upper substrate. The wafer level package may be useful to have an electrical connection structure using vias without any need to a bonding wire, an electrode pad and an electrode lead in the conventional wafer level package since a packaging process is carried out by bonding a wafer for an upper substrate with a plurality of the vias being provided in a wafer for a lower substrate | 2008-12-04 |
20080296715 | Semiconductor device and optical device module having the same - In a solid-state imaging device | 2008-12-04 |
20080296716 | Sensor semiconductor device and manufacturing method thereof - A sensor semiconductor device and a manufacturing method thereof are disclosed. The method includes: providing a light-permeable carrier board with a plurality of metallic circuits; electrically connecting the metallic circuits to a plurality of sensor chips through conductive bumps formed on the bond pads of the sensor chips, wherein the sensor chips have been previously subjected to thinning and chip probing; filling a first dielectric layer between the sensor chips to cover the metallic circuits and peripheries of the sensor chips; forming a second dielectric layer on the sensor chips and the first dielectric layer; forming grooves between the sensor chips for exposing the metallic circuits such that a plurality of conductive traces electrically connected to the metallic circuits can be formed on the second dielectric layer; and singulating the sensor chips to form a plurality of sensor semiconductor devices. The present invention overcomes the drawbacks of breakage of trace connection due to a sharp angle formed at joints, poor electrical connection and chip damage due to an alignment error in cutting from the back of the wafer, as well as an increased cost due to multiple sputtering processes for forming traces. | 2008-12-04 |
20080296717 | Packages and assemblies including lidded chips - A lidded chip is provided which includes a chip having a major surface and a plurality of first chip contacts exposed at the major surface. A lid overlies the major surface. A chip carrier is disposed between the chip and the lid, the chip carrier having an inner surface confronting the major surface and an outer surface confronting the lid. A plurality of first carrier contacts of the chip carrier are conductively connected to the first chip contacts. A plurality of second carrier contacts extend upwardly at least partially through the openings in the lid. | 2008-12-04 |
20080296718 | Semiconductor device and optical device module having the same - A solid-state imaging device | 2008-12-04 |
20080296719 | Infrared detector and manufacturing method thereof - An infrared detector comprises: first and second container members bonded to each other along an annular bonding portion to define a vacuum-sealed inner space, where the second container member has an infrared-transmissive property; an infrared detecting element disposed in the inner space; a first annular metallization layer formed on the bonding portion of the first container member; a second annular metallization layer formed on the bonding portion of the second container member; a solder metal for air-tightly bonding the first metallization layer and the second metallization layer; and a third metallization layer formed in a vicinity of one of the first and second metallization layers such that the third metallization layer overlaps the other of the first and second metallization layers at least partly. | 2008-12-04 |
20080296720 | BACKSIDE-ILLUMINATED IMAGING DEVICE AND MANUFACTURING METHOD OF THE SAME - A backside-illuminated imaging device, which performs imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light and reading out the electric charges from a front side of the semiconductor substrate, is provided and includes: a back-side layer including an back-side element on the back side of the semiconductor substrate; a front-side layer including an front-side element on the front side of the semiconductor substrate; a support substrate above the front-side layer; a spacer, one end of which comes in contact with the front-side layer and the other end of which comes in contact with the support substrate, to form a space having a uniform distance between the semiconductor substrate and the support substrate; and an adhesive filled in at least a part of the space between the surface-side element formation layer and the support substrate. | 2008-12-04 |
20080296721 | Junction Barrier Schottky Diode with Dual Silicides and Method of Manufacture - An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well. | 2008-12-04 |
20080296722 | JUNCTION BARRIER SCHOTTKY DIODE - A junction barrier Schottky diode has an N-type well having surface and a first impurity concentration; a p-type anode region in the surface of the well, and having a second impurity concentration; and an N-type cathode region in the surface of the well and horizontally abutting the anode region, and having a third impurity concentration. A first N-type region vertically abuts the anode and cathode regions, and has a fourth impurity concentration. An ohmic contact is made to the anode and a Schottky contact is made to the cathode. The fourth impurity concentration is less than the first, second and third impurity concentrations. | 2008-12-04 |
20080296723 | Semiconductor device - Provided is a semiconductor device that is capable of suppressing occurrence of a crystal defect in an elongated circuit region formed in an SOI substrate. Low-voltage transistor regions are separated, by multiple inner isolation layers, into multiple sub-regions. For this reason, the length of the longitudinal direction of the sub-regions is reduced, even though the low-voltage transistor regions are extremely elongated, for example. This configuration can suppress occurrence of a crystal defect in the low-voltage transistor regions in the longitudinal direction thereof, although such defect may occur due to the difference in thermal expansion or thermal contraction between a semiconductor layer in the low-voltage transistor regions, and the element isolation layers. | 2008-12-04 |
20080296724 | Semiconductor substrate and manufacturing method of semiconductor device - To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH | 2008-12-04 |
20080296725 | SEMICONDUCTOR COMPONENT AND METHOD FOR FABRICATING THE SAME - A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate. | 2008-12-04 |
20080296726 | Fuse Structure for Maintaining Passivation Integrity - A fuse structure ( | 2008-12-04 |
20080296727 | Programmable poly fuse - According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction. | 2008-12-04 |
20080296728 | SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS - A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier. | 2008-12-04 |
20080296729 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole. | 2008-12-04 |
20080296730 | Semiconductor device - A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion. | 2008-12-04 |
20080296731 | ENHANCED ON-CHIP DECOUPLING CAPACITORS AND METHOD OF MAKING SAME - An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via. | 2008-12-04 |
20080296732 | METHODS OF ISOLATING ARRAY FEATURES DURING PITCH DOUBLING PROCESSES AND SEMICONDUCTOR DEVICE STRUCTURES HAVING ISOLATED ARRAY FEATURES - Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features. | 2008-12-04 |
20080296733 | SEMICONDUCTOR WAFER ASSEMBLY AND METHOD OF PROCESSING SEMICONDUCTOR WAFER - A semiconductor wafer assembly includes a disk-shaped semiconductor wafer including on a face side thereof a flat area having a plurality of semiconductor devices formed thereon and a beveled surface disposed around the flat surface, and a circular adhesive film bonded to a reverse side of the semiconductor wafer. The adhesive film is bonded only to an area of the reverse side which is coextensive with the flat area. | 2008-12-04 |
20080296734 | MICROCHIP AND METHOD OF MANUFACTURING MICROCHIP - A microchip formed by joining a first substrate having at least one recess on its surface and a second substrate, wherein small projections of 0.5 to 30 μm in height are formed on at least a part of the surface having the recess of the first substrate, and a coating formed of a surface processing agent is provided on at least a part of the surface having the small projections formed thereon, as well as a method of manufacturing the microchip, are provided. A microchip allowing easy inspection of the state of application or state of adhesion of liquid material such as a surface processing agent, and allowing accurate optical measurement without causing disturbance such as fluorescence, can be provided. | 2008-12-04 |
20080296735 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In the present invention, a first circuit pattern | 2008-12-04 |
20080296736 | METHOD FOR REDUCING MICROLOADING IN ETCHING HIGH ASPECT RATIO STRUCTURES - A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once. | 2008-12-04 |
20080296737 | Methods for Manufacturing a Structure on or in a Substrate, Imaging Layer for Generating Sublithographic Structures, Method for Inverting a Sublithographic Pattern, Device Obtainable by Manufacturing a Structure - One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps | 2008-12-04 |
20080296738 | GaAs semiconductor substrate and fabrication method thereof - A GaAs semiconductor substrate includes a surface layer. When an atomic ratio is to be calculated using a 3d electron spectrum of Ga atoms and As atoms measured at the condition of 10° for the photoelectron take-off angle θ by X-ray photoelectron spectroscopy, the structural atomic ratio of all Ga atoms to all As atoms (Ga)/(As) at the surface layer is at least 0.5 and not more than 0.9, the ratio of As atoms bound with O atoms to all Ga atoms and all As atoms (As—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35, and the ratio of Ga atoms bound with O atoms to all Ga atoms and all As atoms (Ga—O)/{(Ga)+(As)} at the surface layer is at least 0.15 and not more than 0.35. Accordingly, there is provided a GaAs semiconductor substrate having a surface cleaned to an extent allowing removal of impurities and oxides at the surface by at least thermal cleaning of the substrate. | 2008-12-04 |
20080296739 | Method of forming a thin film structure and stack structure comprising the thin film - Provided is a method of forming a thin film structure and a stack structure comprising the thin film. The method may include forming a crystalline Al | 2008-12-04 |
20080296740 | Method of manufacturing semiconductor device, and semiconductor device - A method for manufacturing a semiconductor device is provided that can reduce warping of manufactured products after the formation of a final protective film. The method includes, in a semiconductor device having a semiconductor substrate provided with wiring and a final protective film formed on the wiring, forming a first protective film on the wiring, forming a second protective film having tensile stress on the first protective film, and removing the first protective film and the second protective film from contact regions of the wiring. | 2008-12-04 |
20080296741 | SEMICONDUCTOR DEVICE - Passivation films including first and second layers (first passivation film) are formed on a GaAs substrate (semiconductor substrate). A SiN film (second passivation film) is formed on the passivation films as a top layer passivation film by a catalytic chemical vapor deposition. The SiN film formed by catalytic chemical vapor deposition has a lower degree of hygroscopicity than that of a conventional SiN film formed by plasma chemical vapor deposition. | 2008-12-04 |
20080296742 | SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THEREOF - A semiconductor device having silicon-oxide-nitride-oxide-silicon (SONOS) structure that overcomes spatial limitations which trap charges by not utilizing a flat, planar structure of the ONO film including a charging trap layer, thereby making it possible to improve reliability for data preserving characteristic of a SONOS device. | 2008-12-04 |
20080296743 | Semiconductor device and method for fabricating the same - The present invention relates to a semiconductor device, and a method for fabricating a semiconductor device, which involves an oxide-nitride-oxide stack in a silicon-oxide-nitride-oxide-silicon device. Barrier characteristics of an upper blocking dielectric layer and/or a lower tunneling dielectric layer on upper and lower sides of a charge trapping dielectric layer are improved, so as to maintain holding characteristics of charges trapped in the charge trapping dielectric layer, making it possible to improve reliability of a semiconductor device containing the same. | 2008-12-04 |
20080296744 | Integrated Circuit - According to one embodiment, an integrated circuit includes an internal circuit and a resin layer which covers the internal circuit. A radio wave absorbing material is mixed in the resin layer. | 2008-12-04 |
20080296745 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIP AND ANTENNA - A semiconductor device comprises a lead frame, an antenna formed at a predetermined position on the lead frame, and a semiconductor chip. The semiconductor chip is mounted on an island of the lead frame through a spacer. | 2008-12-04 |
20080296746 | LEAD FRAME AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - The present invention includes a plurality of mounting portions on which a semiconductor element is mounted, a plurality of electrodes to which the semiconductor elements that are mounted on each of the mounting portions are electrically connected, a corner portion which connects the plurality of mounting portions and which has a hanging lead piece that supports the mounting portions and an electrode connection piece that connects the plurality of electrodes, and a half-blanking portion that has a concave portion formed in a thickness direction of the lead frame and a protrusion formed at a position corresponding to the concave portion, and which is covered with a sealing resin material that seals the semiconductor element. A stress-dispersing portion for dispersing stress that arises, when the half-blanking portion is formed, is provided in the corner portion. | 2008-12-04 |
20080296747 | Micromechanical component having thin-layer encapsulation and production method - A micromechanical component having a substrate and having a thin-layer, as well as having a cavity which is bounded by the substrate and the thin-layer, at least one gas having an internal pressure being enclosed in the cavity. The gas phase has a non-atmospheric composition. A method for producing a micromechanical component having a substrate and having a thin-layer encapsulation, as well as having a cavity which is bounded by the substrate and the thin-layer encapsulation. The method has the steps of positioning a polymer in a cavity, closing the cavity and generating a gas phase of non-atmospheric composition in the cavity by decomposing at least a part of the polymer. An internal pressure is generated, which may be higher than the process pressure when the cavity is closed. | 2008-12-04 |
20080296748 | Transmission line stacking - A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first and second conductors extending toward the first contact, these conductors being connected to one another adjacent the first contact. The conductive path is connected to the first contact, and can provide signal routing from the periphery of the unit to the contact without the need for long stubs. A package may include a plurality of such units, which may be stacked on one another with the redistribution conductive pads of the various units connected to one another. | 2008-12-04 |
20080296749 | Package stacking through rotation - A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second bond windows, and first and second sets of package contacts exposed at diagonally opposite corner regions of the top face, wherein the first and second sets conductively connected to the chip contacts. There is also a microelectronic element adjacent to the bottom face of the dielectric element, as well as bond wires extending through the first and second bond windows to conductively connect the microelectronic element to the chip contacts. | 2008-12-04 |
20080296750 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor chip having a photoelectric conversion function and conductor connecting with the semiconductor chip electrically. The semiconductor chip is sealed by resin. The resin comprises a first sealing resin, second sealing resin and third sealing resin. The second sealing resin has transparency for optical signal to the semiconductor chip and seals one side of the conductor. The third sealing resin seals the other side of the conductor and has a linear thermal expansion coefficient and thickness which may restrain at least a part of flexion of the conductor caused by the linear thermal expansion of the second sealing resin. The first sealing resin seals at least a part of the conductor, is sandwiched between the second sealing resin and the third sealing resin, and has a linear thermal expansion coefficient which may restrain at least a part of the linear thermal expansion of the second sealing resin. | 2008-12-04 |
20080296751 | Semiconductor package - A semiconductor package is revealed, primarily comprising a substrate, a chip disposed on the substrate, and an encapsulant to encapsulate the chip. The substrate has a plurality of dimples formed in its top surface thereof without penetrating through the substrate and located at a non-wiring region outside a chip mounting region. Therefore, without changing the appearance of the semiconductor package, the diffusion path of moisture and the adhesive strength between the encapsulant and the substrate can be increased to achieve functions of anti-humidity and anti-delamination. | 2008-12-04 |
20080296752 | SUBSTRATE WITH PIN, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PRODUCT - A semiconductor product is constructed of a wiring substrate in which pads for pin connection are formed, and a substrate with pins in which pins are disposed. The substrate with the pins is formed so that one end of the pin is exposed to one surface of a resin substrate formed by resin molding and the other end of the pin extends from the other surface of the resin substrate and one end of the pin is bonded to a pad of the wiring substrate through a conductive material. | 2008-12-04 |
20080296753 | MOLDED CERAMIC SURFACE MOUNT PACKAGE - The surface mount package is assembled from a ceramic base which is imprinted on its upper and lower surfaces with conductive patterns for attachment of and connection to an electronic or electromechanical device, a molded dielectric layer for forming a cavity and a seal ring. The molded dielectric is formed by aligning a dielectric preform with the base, positioning the seal ring on top of the preform, then applying a mold over the layers to shape the dielectric during a firing process that fuses the base, preform and seal ring to create a hermetic seal. The preform is of sufficient thickness that the electronic device will be fully contained within the cavity when placed into the completed package. | 2008-12-04 |
20080296754 | APPARATUS TO MINIMIZE THERMAL IMPEDANCE USING COPPER ON DIE BACKSIDE - A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress. | 2008-12-04 |
20080296755 | Semiconductor device - A semiconductor includes a board, a semiconductor element mounted on the board, an electronic component, with the semiconductor element, mounted on the board, a heat radiation member provided so as to face the board, the heat radiation member configured to radiate heat of the semiconductor element, and a thermal connecting member being configured to thermally connect the heat radiation member and the semiconductor element. A metal material is used as the thermal connecting member, and an adhesion preventing member is provided so as to be separated from the electronic component, the adhesion preventing member being configured to prevent the metal material molten and flowing at a heating time being adhered to the electronic component. | 2008-12-04 |
20080296756 | HEAT SPREADER COMPOSITIONS AND MATERIALS, INTEGRATED CIRCUITRY, METHODS OF PRODUCTION AND USES THEREOF - Near net shape heat spreader components are disclosed that comprise at least one pressure-treated powder material. Heat spreaders are also described that include at least one near net shape heat spreader component, and at least one additional part. Methods of forming heat spreaders are also described that include: a) forming a base portion comprising a pressure-treated powder material and having a first surface comprising a perimeter region surrounding a heat-receiving surface; b) forming a frame portion comprising a second material; and c) joining the base portion and the frame portion. | 2008-12-04 |
20080296757 | Fluid spreader - A fluid spreader includes a first surface, wherein the first surface has at least one channel that continuously or discontinuously extends to an outer periphery of the first surface, allowing fluid to flow easily and thereby reducing the thickness of the fluid between the fluid spreader and another device or component. | 2008-12-04 |
20080296758 | Protection and Connection of Devices Underneath Bondpads - A circuit structure and a method for reducing stresses on semiconductor devices fabricated underneath bondpads include metal layers with a lattice planar configuration which spreads forces applied such as during wafer test probing or during wire bonding. Easing electrical connectivity among circuit elements and maintaining circuit performance is also carried out using the lattice. The lattice has metal strips which may connect circuit elements together or which may connect to a reference voltage source. The metal layer and bondpad corners and edges are formed preferentially without acute angles. | 2008-12-04 |
20080296759 | SEMICONDUCTOR PACKAGES - A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via. | 2008-12-04 |
20080296760 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SAME - A semiconductor apparatus includes a semiconductor device having electrodes on its opposed frontside and backside, respectively, a first external electrode connected to the electrode at the frontside, the first external electrode having a first major surface generally parallel to the frontside of the semiconductor device, and a first side surface generally perpendicular to the first major surface, and a second external electrode having a second major surface generally parallel to the backside of the semiconductor device, a second side surface generally perpendicular to the second major surface, and a projection protruding perpendicular to the second major surface and connected to the electrode at the backside, The first side surface of the first external electrode and the second side surface of the second external electrode serve as mount surfaces. The semiconductor device is located between the first external electrode and the second external electrode. | 2008-12-04 |
20080296761 | Cylindrical Bonding Structure and method of manufacture - A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder. | 2008-12-04 |
20080296762 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section. | 2008-12-04 |
20080296763 | Multi-Die Wafer Level Packaging - A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. | 2008-12-04 |
20080296764 | Enhanced copper posts for wafer level chip scale packaging - An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint. | 2008-12-04 |
20080296765 | Semiconductor element and method of manufacturing the same - A semiconductor element ( | 2008-12-04 |
20080296766 | REDUCED INDUCTANCE IN BALL GRID ARRAY PACKAGES - Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within the BGA package is in the wire bonds that couple the set of contacts to the IC. The techniques described herein shorten the wire bonds in order to reduce the amount of parasitic inductance. The techniques include extending traces from a subset of the contacts inward into the BGA package toward the IC mounted. The wire bonds then couple the traces to the IC, thereby electrically coupling the subset of contacts to the IC. The presence of the traces substantially reduces lengths of the wire bonds relative to wire bonds that directly couple the set of contacts to the IC. | 2008-12-04 |
20080296767 | Composition for cleaning semiconductor device - A sulfur-containing detergent composition for cleaning a semiconductor device having an aluminum wire, wherein the sulfur-containing detergent composition is capable of forming a protective film containing a sulfur atom on a surface of an aluminum film in a protective film-forming test; a semiconductor device comprising a protective film containing a sulfur atom on a surface of an aluminum wire, wherein sulfur atom is contained within a region of at least 5 nm in its thickness direction from the surface of the protective film; and method for manufacturing a semiconductor device, comprising the step of contacting an aluminum wire of the semiconductor device with the sulfur-containing detergent composition as defined above, thereby forming a sulfur-containing protective film on the surface of the aluminum wire. The semiconductor device can be suitably used in the manufacture of electronic parts such as LCD, memory and CPU. Especially, the semiconductor device is suitably used in the manufacture of a highly integrated semiconductor with advanced scale-down. | 2008-12-04 |
20080296768 | Copper nucleation in interconnects having ruthenium layers - A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process. | 2008-12-04 |
20080296769 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a line layer containing Cu (copper), an inter layer dielectric formed on the line layer, a via hole formed in the inter layer dielectric on the line layer, a first barrier layer formed on the line layer in the via hole, a second barrier layer formed on the first barrier layer and on a sidewall of the via hole, and a conductive layer formed on the second barrier layer and containing Al (aluminum). | 2008-12-04 |
20080296770 | Semiconductor device - A semiconductor device of the present invention includes a semiconductor substrate; a diffusion layer formed about a surface of the semiconductor substrate; a first conductive layer formed on the semiconductor substrate, and an insulating layer formed on the semiconductor substrate after the first conductive layer and the diffusion layer are formed, and a second conductive layer formed on the insulating layer, and a first contact formed in the insulating layer, connecting the first conductive layer to the second conductive layer, and a second contact formed in the insulating layer, connecting the first conductive layer to the diffusion layer. In addition, a part of the diffusion layer extends to a lower portion of the first contact. | 2008-12-04 |
20080296771 | METHODS OF FABRICATING SILICON CARBIDE POWER DEVICES BY AT LEAST PARTIALLY REMOVING AN N-TYPE SILICON CARBIDE SUBSTRATE, AND SILICON CARBIDE POWER DEVICES SO FABRICATED - A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described. | 2008-12-04 |
20080296772 | Semicondutor device - A semiconductor device according to the present invention includes: a lower wire having copper as a main component; an insulating film formed on the lower wire; an upper wire formed on the insulating film; a tungsten plug penetrating through the insulating film and formed of tungsten for electrically connecting the lower wire and the upper wire; and a barrier layer interposed between the lower wire and the tungsten plug; and the barrier layer including a tantalum film contacting the lower wire and a titanium nitride film contacting the tungsten plug. | 2008-12-04 |
20080296773 | POWER SEMICONDUCTOR DEVICE WITH IMPROVED HEAT DISSIPATION - A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and a surface adjacent the electrode contact area, a dielectric layer disposed above the surface; an intermediate oxide layer disposed above the dielectric layer, a current conducting metallization layer disposed above the intermediate oxide layer; and at least one contact element vertically extending from the dielectric layer through the intermediate oxide layer to the metallization layer above the surface adjacent the electrode contact area, the at least one contact element having a heat conductivity that is higher than that of the intermediate oxide layer. | 2008-12-04 |
20080296774 | ARRANGEMENT INCLUDING A SEMICONDUCTOR DEVICE AND A CONNECTING ELEMENT - An integrated circuit and an arrangement including a semiconductor device and a connecting element and method for producing such an arrangement is disclosed. One embodiment provides a semiconductor element having a first contact face and a second contact face. The first contact face and the second contact face extend in a first lateral direction. An electrically conductive connecting element which has a third contact face electrically contacts the semiconductor element. The connecting element includes a trench system. A first trench of this trench system extends from the third contact face into the connecting element. | 2008-12-04 |
20080296775 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region. | 2008-12-04 |
20080296776 | Method of Manufacturing Electrical Conductors for a Semiconductor Device - A method of manufacturing an electrical conductor for a semiconductor device having one or more layers includes etching from a first surface to a second surface of at least one layer of the device to form a channel having a wall extending from the first surface to the second surface. The channel defines a gap extending from the first surface to the second surface. An insulating layer is provided on the channel wall. Conductive material is patterned on the channel wall to form multiple separate electrical conductors, which are insulated from material of the at least one layer by the insulating layer, thereon, such that the gap that extends from the first surface to the second surface is maintained. A corresponding semiconductor device is also provided. | 2008-12-04 |
20080296777 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and reducing production cost. The semiconductor device according to the present invention has a low dielectric constant film having a dielectric constant of not less than 2.7. In the low dielectric constant film and the like, materials (e.g., a first dummy pattern, a second dummy pattern) with a larger hardness than that of the low dielectric constant film are formed at a part under a pad part. | 2008-12-04 |
20080296778 | Interconnection Structure and Integrated Circuit - A method of manufacturing an integrated circuit and an interconnection structure includes forming a conductive portion along a first direction and conductive lines along a second direction. | 2008-12-04 |
20080296779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aimed at providing a semiconductor device improved in reliability of bonding and yield of products, even when semiconductor chips having through electrodes are used, the semiconductor device of the present invention has a substrate; a stack placed on the substrate, and composed of a plurality of semiconductor chips (first semiconductor chip and second semiconductor chip), each having through electrodes, stacked while placing bumps connected to the through electrodes in between; and a reinforcing chip (semiconductor chip) provided on the stack specifically on the surface thereof opposite to the substrate-side surface, or between the substrate and the stack, wherein thickness of the reinforcing chip is larger than the thickest semiconductor chip out of the plurality of semiconductor chips. | 2008-12-04 |
20080296780 | MEMORY DEVICES INCLUDING SEPARATING INSULATING STRUCTURES ON WIRES AND METHODS OF FORMING - Wires included in integrated circuit devices can have separate insulating structures formed thereon. The separate insulating structures on the wires can surround respective cross sectional portions of the wires, which can function as “stand-offs” to prevent immediately neighboring wires (or other neighboring components) from shorting together to thereby allow a reduction in defects associated with devices having reduced pitch between the wires (or other components). | 2008-12-04 |
20080296781 | REDUCED-DIMENSION MICROELECTRONIC COMPONENT ASSEMBLIES WITH WIRE BONDS AND METHODS OF MAKING SAME - The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component. | 2008-12-04 |
20080296782 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer applied onto the carrier, an adhesive layer applied to the electrically insulating layer. A first semiconductor chip applied to the adhesive layer. | 2008-12-04 |
20080296783 | RESIN MOLDED SEMICONDUCTOR DEVICE - A semiconductor device includes a circuit board, a wiring part, a protective coating glass, and a resin part. The circuit board has an approximately rectangular shape. The protective coating glass is disposed on the circuit board and is arranged on an inside of the circuit board in such a manner that an outer-peripheral end of the protective coating glass is away from each of four sides of the circuit board at a first distance and is away from each of four corners of the circuit board at a second distance that is larger than the first distance. The resin part seals the circuit board, the wiring part, and the protective coating glass in such a manner that an outer-peripheral end portion of the circuit board that is located on an outside of the protective coating glass directly contact with the resin part. | 2008-12-04 |
20080296784 | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device - A semiconductor device is disclosed which includes a tab ( | 2008-12-04 |
20080296785 | Method of forming catalyst nanoparticles for nanowire growth and other applications - Methods for forming a predetermined pattern of catalytic regions having nanoscale dimensions are provided for use in the growth of nanowires. The methods include one or more nanoimprinting steps to produce arrays of catalytic nanoislands or nanoscale regions of catalytic material circumscribed by noncatalytic material. | 2008-12-04 |
20080296786 | Process for preparing alkali metal alkoxides - The invention relates to a process for preparing an alcoholic solution of an alkali metal alkoxide from alkali metal hydroxide and alcohol in a reaction column, the alcohol and the alkali metal hydroxide being conducted in countercurrent, which is characterized in that a reflux ratio of at least is established in the reaction column. | 2008-12-04 |
20080296787 | Gas Splattered Fluid Display - A fluid display includes a fluid source, a gas source, and a light source. The fluid source coherently emits fluid along a first trajectory. The gas source emits gas along a second trajectory that intersects the first trajectory. The light source is directed toward the intersection of the first trajectory and the second trajectory. The second trajectory may intersect the first trajectory at an oblique angle. The fluid source and/or the gas source may emit intermittently. The fluid source may emit a laminar jet or spherical fluid globules. The gas source may intermittently emit a gas vortex. The gas may be a flammable gas. The fluid may be water and the gas may be air. The fluid display may provide a “water sparkler” effect. | 2008-12-04 |
20080296788 | Bubble Generator - A bubble generator includes an air intake device, an air guide device, an aeration disc and a rotating device. The air guide device is partially immersed in liquid and guides air flowed into the air guide device through the air intake device toward the liquid. The aeration disc produces negative pressure by being rotated in the liquid and moving the liquid whereby air guided by the air guide device produces air bubbles in the liquid. The aeration disc comprises one or more blades that spin to create a vacuum of air moving downward through the air intake device and air guide device and into the liquid, and an arcuate wall that comprises one or more slots. | 2008-12-04 |
20080296789 | Fine Bubble Delivery For Potable Water, Wastewater, And Clean Water Treatment - A flexible tubing for fine bubble aeration is provided with an air passageway defined in part by an upper portion and a lower portion. The tubing can be made of a uniform weighted material with more material in the lower portion than in the upper portion. This makes the tubing self-orienting, in that it will tend to orient itself with micro-slits along the upper portion facing upward and the lower portion facing downward when submerged in a body of water. An automated, one-stage production line converts raw tubing material to a finished tubing product without the need for separate processing. A method of coiling the tubing places the micro-slits approximately 90° away from the surface of a spool hub, thereby avoiding a longitudinal arch in the tubing and ultimately preventing roll-over and improper slit orientation after installation in a water body. | 2008-12-04 |
20080296790 | INTAKE AIR AND CARBURETOR HEATING ARRANGEMENT FOR V-TWIN ENGINES - A V-twin engine having a crankcase and a pair of cylinders defining a V-space therebetween, wherein the V-space is substantially enclosed, and a carburetor is positioned within the V-space. An intake air preheating arrangement supplies heated intake air to the carburetor, and a carburetor heating arrangement heats the V-space and the carburetor which is positioned within the V-space. Each of the foregoing arrangements, used separately or in combination within one another, aids in preventing “freeze-up” of the carburetor during running of the engine in a cold environment. | 2008-12-04 |
20080296791 | Vaporizing apparatus and semiconductor processing system - A vaporizing apparatus for generating a process gas from a liquid material includes a vaporizing container defining a vaporizing space of the vaporizing apparatus; an injector connected to the vaporizing container to spray the liquid material in an atomized state into the vaporizing space; and a heater attached to the vaporizing container to heat the liquid material sprayed in the vaporizing space. The vaporizing apparatus further includes a gas delivery passage connected to the vaporizing container to output from the vaporizing space a generation gas generated from the liquid material; a filter disposed inside the gas delivery passage or between the gas delivery passage and the vaporizing space to trap mist contained in the generation gas; and an infrared irradiation mechanism configured to irradiate the filter with infrared rays. | 2008-12-04 |
20080296792 | Composite Light Guiding Device - A light guiding device ( | 2008-12-04 |
20080296793 | Lighting apparatus and display apparatus - The lighting apparatus includes a light source, a housing that contains the light source inside and has an exit port for outputting light from the light source, and an optical sheet that is placed in the exit port. The optical sheet includes a lens structure that is placed at a light exit side and aligns an output direction of incident light from the light source, a reflector that is placed at a light incident side and reflects light emitted by the light source, and a light transmitting opening that exists in the reflector and transmits incident light from the light source. The light transmitting opening is placed in a position deviated from an optical axis of the lens structure. The display apparatus includes the lighting apparatus. | 2008-12-04 |
20080296794 | Underwater Pelletizing Machine and Method of Extruding Foamed Thermoplastic Pellets - A pelletizing machine for forming pellets from extruded material includes an extruder having at least one exit port and a body defining a cutting chamber through which high-temperature liquid flows, flooding the cutting chamber. The exit port of the extruder opens into the cutting chamber, which includes a cutting section defining a flow path for liquid through the cutting section. A cutter in the cutting section of the cutting chamber is mounted for rotation about an axis generally perpendicular to the first direction and disposed for cutting the extruded material exiting the exit port into the pellets. The axis of rotation of the cutter is parallel to or coincident with the flow path of the cutting section. A method for forming pellets of thermoplastic material with a foaming agent is also disclosed. | 2008-12-04 |
20080296795 | Process to create decorative pattern in engineered stone - A pattern is created in an engineered stone by creating a void in an initial mineral particle/binder composition prior to curing and solidification of the binder. The void is filled with a separate mineral/binder composition and cured at the same time as the initial composition. | 2008-12-04 |
20080296796 | Method of manufacturing electronic device having resin-molded case and molding tool for forming resin-molded case - In a method of manufacturing an electronic device, an electronic element is disposed on a wiring plate that is electrically coupled with a connector terminal, a first surface of the wiring plate is covered with a first casing element and a second surface of the wiring plate is covered with a second casing element to form an electronic circuit part, the electronic circuit part is disposed in a case cavity of a molding tool, and a resin is filled into the case cavity to form the resin-molded case while keeping a state where a first pressure that pushes the first casing element toward the wiring plate and that changes with time is substantially equal to a second pressure that pushes the second casing element toward the wiring plate and that changes with time. | 2008-12-04 |
20080296797 | Particle blasting method and apparatus therefor - A block former comprises a portable device for compression forming of carbon dioxide particles into a non-homogenous block of carbon dioxide. The formed non-homogenous block can be used with carbon dioxide blasters that shave the formed block, and then eject the carbon dioxide shavings into a pneumatic jet as a blast media for cleaning surfaces. The block former further comprises a control system comprising a logic system of switches, valves, and timers to perform a timed sequence of events to form loose carbon dioxide particles into a non-homogenous block, to release compression on the block, and to eject the formed block from the block former. A single compression surface is provided to compress the carbon dioxide particles block, to release pressure on the block, and to eject the block from the block former device. The carbon dioxide particles used to form the non-homogeneous block can vary in size from snow to chunks or pellets. | 2008-12-04 |
20080296798 | Method of Making Lightweight High Performance Ceramic Material - A method of making a sintered ceramic composition includes the steps of: providing a powder that includes at least 50 wt. % boron carbide and 0.05 wt. % to 30 wt. % of at least one oxide selected from oxides of Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy Ho, Er, Tm, Yb, and Lu; milling the powder to form a milled powder; | 2008-12-04 |
20080296799 | Methods and Devices for the Production of Solid Filaments in a Vacuum Chamber - Disclosed are methods for producing a solid filament from a liquid in a vacuum chamber, comprising the following steps: a gas is liquefied in a heat exchanger apparatus to produce the liquid; and the liquid is delivered into the vacuum chamber via a supply duct and through a nozzle. Liquefying of the gas in the heat exchanger apparatus encompasses adjusting a p-T operating point of the liquid at which the liquid is transformed into the solid aggregate state and forms a collimated and stable jet after being discharged from the nozzle into the vacuum chamber. Also disclosed are nozzle arrangements for producing solid filaments in a vacuum. | 2008-12-04 |
20080296800 | Flyash Aggregate - Described in this specification is a formula for a light weight flyash aggregate for concretes, as well as the method for producing the aggregate and the facilities needed to produce the aggregate. The compaction and bonding of the flyash is facilitated by essentially pure fine washed sands, with the presence of a binding agent that is a caustic soda solution. | 2008-12-04 |
20080296801 | Conditioning Device For Plastic Items And Process - A device and process for conditioning plastic preforms ( | 2008-12-04 |
20080296802 | Method of manufacturing a golf ball - The present invention provides a method of manufacturing a golf ball having a core or a sphere composed of a core enclosed by an envelope layer over which core or sphere at least a first covering layer and a second covering layer are consecutively formed using at least two vertically separating two-part molds of differing size cavities, each mold being composed of a top half and a bottom half, that are installed in such a way that the top mold halves are horizontally rotatable together and the bottom mold halves are horizontally rotatable together. The method includes the steps of: (1) placing the core or sphere in the cavities of a first top mold half and a first bottom mold half and injection-molding a molding material so as to form the first covering layer over the core or sphere one hemisphere at a time; and (2) rotating a second top mold half or second bottom mold half having a cavity that is larger than the cavity of the first top mold half or first bottom mold half to a predetermined position, placing the core or sphere on which has been formed the first covering layer in the second top mold half or second bottom mold half, and injection-molding a molding material so as to form the second covering layer around the first covering layer one hemisphere at a time. By molding the covering layers one hemisphere at a time, two or more covering layers of differing thickness can be consecutively formed. Golf balls obtained in this way are of higher quality than conventionally manufactured balls and can be endowed, in particular, with an improved durability. | 2008-12-04 |
20080296803 | Nano-imprinting process - A nano-imprinting process is described, comprising: providing a substrate including an imprinting material layer covering a surface of the substrate; providing a mold including protruding features set on a surface of the mold covered with an anti-adhesion layer; forming a transferring material layer on a top surface of each protruding feature; embedding the transferring material layer into a first portion of the imprinting material layer; removing the mold and separating the mold and the transferring material layer simultaneously to transfer the transferring material layer into the first portion of the imprinting material layer and to expose a second portion of the imprinting material layer; using the transferring material layer as a mask to remove the second portion of the imprinting material layer and a portion of the substrate; and removing the first portion of the imprinting material layer and the transferring material layer. | 2008-12-04 |
20080296804 | SHAFT PROVIDED WITH A MAGNET FOR AN AIR FLOW RATE ADJUSTMENT VALVE IN AN INTERNAL COMBUSTION ENGINE - A manufacturing method of a shaft provided with a magnet for an air flow rate adjustment valve in an internal combustion engine; the method presents the steps of: arranging a first mold which negatively reproduces the shape of the shaft and determines the formation of a seat for the magnet; injecting a molten plastic material inside the mold in order to form the shaft provided with the seat for the magnet by injection molding; arranging a second mold which surrounds the seat for the magnet; and injecting a molten magnetic polymer in the second mold for forming the magnet by injection molding. | 2008-12-04 |
20080296805 | Hot Runner Melt Pre-Compression - Disclosed, amongst other things, is: an injection molding runner system, an injection molding method for operation of a runner system, and an injection molding machine amongst other things. The runner system includes a geometrically unbalanced melt distribution network and a means for pre-pressurizing of the molding material within the melt distribution network. | 2008-12-04 |
20080296806 | Hot Runner Melt Pre-Compression - Disclosed, amongst other things, is: an injection molding runner system, an injection molding method for operation of a runner system, and an injection molding machine amongst other things. The runner system includes a melt distribution network and a means for pre-pressurizing of the molding material within the melt distribution network. | 2008-12-04 |
20080296807 | SOLUTION CASTING APPARATUS AND SOLUTION CASTING METHOD - A casting die includes lip plates and inner deckle plates, each of which has a contact face. The contact faces form an outlet of the casing die. A distance between a ridge of the lip plate and that of the inner deckle plate is at most 9 μm. Further, nozzles are disposed so as to be close to the outlet. A casting dope is discharged from the outlet to a support, so as to form a dope bead between the outlet and a periphery of the support. The nozzles supply a solution to side edges of the dope bead. | 2008-12-04 |
20080296808 | Apparatus and Method for Producing Electrospun Fibers - An apparatus for making electrspun fibers comprises a collector that may be submerged in a coagulation bath. The collector may be automatically movable between a first position and a second position, wherein at least a portion of the collected fibers are submerged in a coagulation bath in the first position and spaced apart from the coagulation bath in the second position. The collector may be a rotating collector. A process for making electrospun fibers comprises electrospinning a dispersion and collecting a plurality of electrospun fibers, followed by submerging the collected fibers in a coagulation bath. | 2008-12-04 |
20080296809 | End Disk - A plastic end disk for a hollow-cylindrical filter element has an end face plastic layer and a neighboring plastic layer. The end face plastic layer is transparent for infrared radiation. The neighboring plastic layer is absorbent for infrared radiation. The plastic end disk is connected to a folded filter medium in that the end face plastic layer is trans-irradiated with an infrared radiation source, wherein the infrared radiation is absorbed in the neighboring plastic layer so that a portion of the neighboring plastic layer and a portion of the end face plastic layer are completely melted. The infrared radiation source is removed and the filter medium is pressed into a melted area of the end face plastic layer. The filter medium is secured in the pressed-in position in the end face plastic layer until a fixed connection of filter medium and end face plastic layer has been formed. | 2008-12-04 |
20080296810 | METHOD AND APPARATUS FOR CORRUGATING AND WINDING UP ROLLS OF PLASTIC FILM - A method and an apparatus for corrugating and winding up rolls of a plastic film. The plastic film is corrugated as it is continuously wound onto a roll, by a film drawing drum conformed with a plurality of longitudinally extending grooves to perform open-end corrugation or folds which extend crosswise the film; the plastic film is corrugated crosswise, causing the same film to penetrate into the grooves of the drawing drum by suction of air through a plurality of suction holes which open out into the grooves of the drum. | 2008-12-04 |
20080296811 | METHOD FOR PRODUCING DUCT - According to a method for producing a duct, a cylindrical preform, which opens at its both end portions in a longitudinal direction and has a central part, is formed. The central part is narrowed with respect to the both end portions. The central part has a smaller cross-sectional area than that of the both end portion. The preform is formed from a thermoplastic material, which increases in strength when stretched. Next, the preform is heated. Then, stretch blow molding is performed on the preform by stretching the preform in axial and radial directions thereof, such that the cross-sectional area of the central part becomes generally the same as that of the both end portion, or equal to or larger than that of the both end portion. The central part is narrowed to such an extent that it retains predetermined strength after performing the molding on the preform. | 2008-12-04 |