49th week of 2008 patent applcation highlights part 15 |
Patent application number | Title | Published |
20080296612 | Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate and in a semiconductor device - Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing ( | 2008-12-04 |
20080296613 | ESD PROTECTION DEVICES - An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path. | 2008-12-04 |
20080296614 | Mis-Type Field-Effect Transistor - A strained Si layer | 2008-12-04 |
20080296615 | FABRICATION OF STRAINED HETEROJUNCTION STRUCTURES - Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it. | 2008-12-04 |
20080296616 | Gallium nitride-on-silicon nanoscale patterned interface - A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate that is heated to a temperature in a range of about 300 to 800° C., and a first film is formed in compression overlying the Si substrate. The first film material may be InP, SiGe, GaP, GaAs, AlN, AlGaN, an AlN/graded AlGaN (Al | 2008-12-04 |
20080296617 | METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N MATERIALS - A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor. | 2008-12-04 |
20080296618 | P-GaN/AlGaN/AlN/GaN ENHANCEMENT-MODE FIELD EFFECT TRANSISTOR - An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel. | 2008-12-04 |
20080296619 | ADHESIVE BONDING WITH LOW TEMPERATURE GROWN AMORPHOUS OR POLYCRYSTALLINE COMPOUND SEMICONDUCTORS - Amorphous and polycrystalline III-V semiconductor including (Ga,As), (Al,As), (In,As), (Ga,N), and (Ga,P) materials were grown at low temperatures on semiconductor substrates. After growth, different substrates containing the low temperature grown material were pressed together in a pressure jig before being annealed. The annealing temperatures ranged from about 300° C. to 800° C. for annealing times between 30 minutes and 10 hours, depending on the bonding materials. The structures remained pressed together throughout the course of the annealing. Strong bonds were obtained for bonding layers between different substrates that were as thin as 3 nm and as thick as 600 nm. The bonds were ohmic with a relatively small resistance, optically transparent, and independent of the orientation of the underlying structures. | 2008-12-04 |
20080296620 | ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR FIN AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin. | 2008-12-04 |
20080296621 | III-nitride heterojunction device - A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof. | 2008-12-04 |
20080296622 | BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS - A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor. | 2008-12-04 |
20080296623 | BIPOLAR TRANSISTOR AND METHOD FOR MAKING SAME - A heterojunction bipolar transistor: The transistor may a collector layer, a base layer and an emitter layer. The transistor may include a dielectric material being disposed over the base layer. The base layer may be a SiGe base layer. | 2008-12-04 |
20080296624 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer. | 2008-12-04 |
20080296625 | Gallium nitride-on-silicon multilayered interface - A multilayer thermal expansion interface between silicon (Si) and gallium nitride (GaN) films is provided, along with an associated fabrication method. The method provides a (111) Si substrate and forms a first layer of a first film overlying the substrate. The Si substrate is heated to a temperature in the range of about 300 to 800° C., and the first layer of a second film is formed in compression overlying the first layer of the first film. Using a lateral nanoheteroepitaxy overgrowth (LNEO) process, a first GaN layer is grown overlying the first layer of second film. Then, the above-mentioned processes are repeated: forming a second layer of first film; heating the substrate to a temperature in the range of about 300 to 800° C.; forming a second layer of second film in compression; and, growing a second GaN layer using the LNEO process. | 2008-12-04 |
20080296626 | NITRIDE SUBSTRATES, THIN FILMS, HETEROSTRUCTURES AND DEVICES FOR ENHANCED PERFORMANCE, AND METHODS OF MAKING THE SAME - The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors. | 2008-12-04 |
20080296627 | Nitride semiconductor device and method of manufacturing the same - In the nitride semiconductor device using the silicon substrate, the metal electrode formed on the silicon substrate has both ohmic contact property and adhesion, so that the nitride semiconductor device having excellent electric properties and reliability is obtained. The nitride semiconductor device includes a silicon substrate ( | 2008-12-04 |
20080296628 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING SAME - A semiconductor integrated circuit includes at least one first circuit portion and at least one second circuit portion. The first circuit portion includes a first interconnect or a diffusion layer formed by exposure using a high-precision mask. The second circuit portion includes a second interconnect or a diffusion layer formed by exposure using a first low-precision mask having a lower precision than the high-precision mask. | 2008-12-04 |
20080296629 | Solid-state imaging device, method of manufacturing the same, and imaging apparatus - A solid-state imaging device includes a semiconductor substrate; a first conductive region of the semiconductor substrate; a first conductive region on an upper surface side of the first conductive region of the semiconductor substrate; a second conductive region below the first conductive region on the upper surface side of the first conductive region of the semiconductor substrate. The solid-state imaging device further includes a photoelectric conversion region including the first conductive region located on the upper surface side of the first conductive region of the semiconductor substrate and the second conductive region and a transfer transistor transferring charges accumulated in the photoelectric conversion region to a readout region; and a pixel including the photoelectric conversion region and the transfer transistor. The first conductive region, which is included in the photoelectric conversion region, extends to the lower side of a sidewall of a gate electrode of the transfer transistor. | 2008-12-04 |
20080296630 | CMOS image sensor and pixel of the same - A pixel of an image sensor includes a gate insulation layer formed over a substrate doped with first-type impurities, a transfer gate formed over the gate insulation layer, a photodiode formed in the substrate at one side of the transfer gate, and a floating diffusion node formed in the substrate at the other side of the transfer gate, wherein the transfer gate has a negative bias during a charge integration cycle. | 2008-12-04 |
20080296631 | METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING THE SAME - A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention. | 2008-12-04 |
20080296632 | Stress-Enhanced Performance Of A FinFet Using Surface/Channel Orientations And Strained Capping Layers - Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs. | 2008-12-04 |
20080296633 | ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER - An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure. | 2008-12-04 |
20080296634 | STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS - The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region. | 2008-12-04 |
20080296635 | Semiconductor device with strain - A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region. | 2008-12-04 |
20080296636 | Devices and integrated circuits including lateral floating capacitively coupled structures - According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage. Further aspects of the invention relate to device integration, efficient fabrication of field shaping regions and device isolation features using the same mask for both, and improved device structures. | 2008-12-04 |
20080296637 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern. | 2008-12-04 |
20080296638 | Semiconductor device and method of manufacturing the same - A semiconductor device includes an active pattern on a substrate, the active pattern including a protrusion with a lower surface on the substrate and an upper surface opposite the lower surface, a width of the protrusion gradually decreasing from the lower surface to the upper surface, the upper surface of the protrusion being sharp and defining a first active region of the active pattern along a first direction, isolation layer patterns on the substrate in recesses at both sides of the active pattern, the isolation layer patterns exposing the first active region, a gate structure on the first active region and on the isolation layer patterns, the gate structure extending along a second direction, the first and second directions being perpendicular to each other, and source/drain regions under the first active region at both sides of the gate structure. | 2008-12-04 |
20080296639 | Semiconductor image sensor array device, apparatus comprising such a device and method for operating such a device - A plural line CMOS sensor array device is provided with sensor cells arranged in a matrix of coordinate-wise rows and columns. Each cell comprises a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photosensitive area and the output node. Along at least a first coordinate direction adjacent cells are functionally configured as mutually mirror-symmetric structures in that their proximate output nodes are facing each other and are arranged for separately feeding a respective output channel. | 2008-12-04 |
20080296640 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD FOR MAKING SAME, AND IMAGE PICKUP APPARATUS - Disclosed herein is a solid-state image pickup device which includes: a light-receiving unit for photoelectric conversion of incident light; and a charge transfer unit of an n-channel insulating gate type configured to transfer a signal charge photoelectrically converted in the light-receiving unit; wherein the charge transfer unit has an insulating film formed on a transfer electrode and having a negative fixed charge. | 2008-12-04 |
20080296641 | Multi-well CMOS image sensor and methods of fabricating the same - Provided is a multi-well CMOS image sensor and a method of fabricating the same. The multi-well CMOS image sensor may include a plurality of photodiodes vertically formed in a region of a substrate, an n+ wall that vertically connects an outer circumference of the photodiodes, and a floating diffusion region that is connected to the photodiodes on a side of the n+ wall to receive charges from the photodiodes, wherein a p-type region is formed between the floating diffusion region and the n+ wall, and the plurality of photodiodes have a multi-potential well structure. | 2008-12-04 |
20080296642 | PHOTODIODE AND PHOTO IC USING SAME - The present invention provides a photodiode comprising a first silicon semiconductor layer formed over an insulating layer, a second silicon semiconductor layer formed over the insulating layer, having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, a low-concentration diffusion layer which is formed in the second silicon semiconductor layer and in which an impurity of either one of a P type and an N type is diffused in a low concentration, a P-type high-concentration diffusion layer which is formed in the first silicon semiconductor layer and in which the P-type impurity is diffused in a high concentration, and an N-type high-concentration diffusion layer which is opposite to the P-type high-concentration diffusion layer with the low-concentration diffusion layer interposed therebetween and in which the N-type impurity is diffused in a high concentration. | 2008-12-04 |
20080296643 | SOLID STATE IMAGE SENSING DEVICE - A solid state image sensing device in which many pixels are disposed in a matrix on a two-dimensional plane comprises a plurality of light receiving devices disposed in such a way that a center interval may periodically change in a column direction and/or a row direction, and a plurality of micro-lenses, for collecting an incident light of each light receiving device, wherein a center interval periodically changes in accordance with the periodic change of the center interval of the light receiving device. | 2008-12-04 |
20080296644 | CMOS IMAGE SENSORS AND METHODS OF FABRICATING SAME - A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region and the electrically conductive gate. The gate insulating region includes a nitridated insulating layer extending to an interface with the electrically conductive gate and a substantially nitrogen-free insulating layer extending to an interface with the semiconductor channel region. The nitridated insulating layer may be a silicon oxynitride (SiON) layer. | 2008-12-04 |
20080296645 | Solid-state imaging device and manufacturing method thereof - A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to that of a source region and a drain region of the transistor. A part of a gate electrode of the transistor protrudes toward the element separation region side beyond an active region of the transistor. An insulating film having a thickness substantially the same as that of a gate insulating film of the gate electrode of the transistor is formed on the element separation region continuing from a part thereof under the gate electrode of the transistor to a part thereof continuing from the part under the gate electrode of the transistor. | 2008-12-04 |
20080296646 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate; a transistor that is formed on the semiconductor substrate; a ferroelectric capacitor including a bottom electrode that is formed above the semiconductor to be connected with the transistor, a ferroelectric film that is formed on the bottom electrode, and a top electrode that is formed on the ferroelectric film; a first reaction preventing film that covers a lower side surface of the ferroelectric capacitor; and a second reaction preventing film that covers an upper side surface and a top surface of the ferroelectric capacitor. | 2008-12-04 |
20080296647 | Semiconductor memory device and manufacturing method thereof - The present invention provides a semiconductor memory device comprising a semiconductor substrate formed of a support substrate, an insulating film formed over the support substrate and a semiconductor layer formed over the insulating film; a MOSFET having a source layer and a drain layer both formed in the semiconductor layer of a transistor forming area set to the semiconductor substrate, and a channel region provided between the source and drain layers; a MOS capacitor having a capacitor electrode which is formed in the semiconductor layer of a capacitor forming area set to the semiconductor substrate and in which an impurity of the same type as the source layer is diffused; and a device isolation layer which insulates and separates between the semiconductor layer formed with the MOSFET and the semiconductor layer formed with the MOS capacitor, wherein the capacitor electrode of the MOS capacitor is formed in polygon and slanting faces enlarged toward the insulating film are provided therearound, and wherein a floating gate electrode is provided which extends from over a channel region of the MOSEFT to over corners of ends on the MOSFET side, of the capacitor electrode and which is opposite to the channel region and the capacitor electrode with a gate insulating film interposed therebetween. | 2008-12-04 |
20080296648 | FIN MEMORY STRUCTURE AND METHOD FOR FABRICATION THEREOF - A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure. | 2008-12-04 |
20080296649 | SEMICONDUCTOR DEVICE EMPLOYING BURIED INSULATING LAYER AND METHOD OF FABRICATING THE SAME - A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate. | 2008-12-04 |
20080296650 | High-k dielectrics with gold nano-particles - A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor. | 2008-12-04 |
20080296651 | SEMICONDUCTOR DEVICE - A disclosed semiconductor device comprises a non-volatile memory cell including a PMOS write transistor and an NMOS read transistor. The PMOS write transistor includes a write memory gate oxide film formed on a semiconductor substrate and a write floating gate of electrically-floating polysilicon formed on the write memory gate oxide film. The NMOS read transistor includes a read memory gate oxide film formed on the semiconductor substrate and a read floating gate of electrically-floating polysilicon formed on the read memory gate oxide film. The write floating gate and the read floating gate are electrically connected to each other. The PMOS write transistor is configured to perform writing in the non-volatile memory cell, and the NMOS read transistor is configured to perform reading from the non-volatile memory cell. | 2008-12-04 |
20080296652 | SPLIT GATE FLASH MEMORY CELL WITH BALLISTIC INJECTION - A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region. | 2008-12-04 |
20080296653 | Semiconductor memory - A semiconductor memory device of an aspect of the present invention comprises a plurality of memory cell transistors arranged in a memory cell array, a select transistor which is disposed in the memory cell array and which selects the memory cell transistor, and a peripheral circuit transistor provided in a peripheral circuit which controls the memory cell array, the memory cell transistor including a gate insulating film provided on a semiconductor substrate, a floating gate electrode provided on the gate insulating film, a between-storage-layer-and-electrode insulating film which is provided on the floating gate electrode and through which the amount of passing charge is greater than that through the gate insulating film during the application of an electric field in write and erase operations of the semiconductor memory, and a control gate electrode on the between-storage-layer-and-electrode insulating film. | 2008-12-04 |
20080296654 | Non-volatile memory device and method for fabricating the same - A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate. | 2008-12-04 |
20080296655 | MULTI-TIME PROGRAMMABLE MEMORY AND METHOD OF MANUFACTURING THE SAME - A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer. | 2008-12-04 |
20080296656 | SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films. | 2008-12-04 |
20080296657 | Non-Volatile Memory Devices and Methods of Manufacturing Non-Volatile Memory Devices - A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction. | 2008-12-04 |
20080296658 | PROCESS FOR MANUFACTURING A MEMORY DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND COMPRISING NANOCRISTAL MEMORY CELLS AND CMOS TRANSISTORS - An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide. | 2008-12-04 |
20080296659 | Nand Flash Memory Array Having Pillar Structure and Fabricating Method of the Same - The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs. | 2008-12-04 |
20080296660 | LOW RESISTIVITY CONDUCTIVE STRUCTURES, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FORMING SAME - A conductive structure and method for making same is disclosed and includes a first nucleation layer formed by performing a cyclic deposition process on a substrate, a second nucleation layer formed on the first nucleation layer by a CVD process, and a bulk metal layer formed on the second nucleation layer. | 2008-12-04 |
20080296661 | INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC | 2008-12-04 |
20080296662 | Discrete Trap Memory (DTM) Mediated by Fullerenes - A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps. | 2008-12-04 |
20080296663 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a first gate insulator, a first gate electrode, a second gate insulator, and a second gate electrode. Regarding the thickness of the second gate insulator, the thickness of the insulator, on a first edge of the first gate electrode in the word-line direction, and the thickness of the insulator, on a second edge of the first gate electrode in the word-line direction, are larger than, the thickness of the insulator, on the upper surface of the first gate electrode, the thickness of the insulator, on the first side of the first gate electrode in the word-line direction, and the thickness of the insulator, on the second side of the first gate electrode in the word-line direction. | 2008-12-04 |
20080296664 | INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES - A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device. | 2008-12-04 |
20080296665 | MASK FOR MANUFACTURING TFT, TFT, AND MANUFACTURING THEREOF - A mask comprises a channel region half-exposure mask structure, a drain mask structure, and a source mask structure, wherein the channel region half-exposure mask structure comprises a channel region peripheral half-exposure mask structure, which extends from a portion that corresponds to a channel region of the TFT and is outside the portion. According to the present invention, problems such as a connection of the source/drain and a disconnection of the active layer in the channel region can be effectively prevented. | 2008-12-04 |
20080296666 | SEMICONDUCTOR DEVICE INCLUDING AN EMBEDDED CONTACT PLUG - A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions. The source/drain regions are formed by thermal diffusion of impurities from the impurity-containing contact plugs toward the active area, | 2008-12-04 |
20080296667 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a fin active region with a tapered side surface, a gate electrode that has a side surface covering portion covering a part of the side surface of the fin active region and a top surface covering portion covering a part of a top surface of the fin active region, and a source region and drain region formed in the fin active region. In at least a part of the side surface covering portion of the gate electrode, the width is wider at its bottom than at its top. Control of electric field by the gate electrode is improved. Punch-through is thus prevented. | 2008-12-04 |
20080296668 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner. | 2008-12-04 |
20080296669 | SYSTEM AND METHOD FOR MAKING A LDMOS DEVICE WITH ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type. | 2008-12-04 |
20080296670 | Semiconductor Devices Including Transistors Having a Recessed Channel Region and Methods of Fabricating the Same - Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein. | 2008-12-04 |
20080296671 | SEMICONDUCTOR MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers ( | 2008-12-04 |
20080296672 | TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect. | 2008-12-04 |
20080296673 | Double gate manufactured with locos techniques - This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of the bottom insulation attached to sidewalls of the trench extending above a top surface of the bottom trench-filling segment. | 2008-12-04 |
20080296674 | TRANSISTOR, INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - A transistor, an integrated circuit and a method of forming an integrated circuit is disclosed. One embodiment includes a gate electrode. The gate electrode is disposed in a gate groove formed in a semiconductor substrate and includes a conductive carbon material. | 2008-12-04 |
20080296675 | SEMICONDUCTOR DEVICE - The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors. | 2008-12-04 |
20080296676 | SOI FET With Source-Side Body Doping - An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device. | 2008-12-04 |
20080296677 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND DATA PROCESSING SYSTEM - A semiconductor device is provided with a silicon pillar formed substantially perpendicularly to a main surface of a substrate, a gate electrode covering side surface of the silicon pillar via a gate insulation film, a conductive layer provided on an upper part of the silicon pillar, a cylindrical sidewall insulation film intervening between the conductive layer and the gate electrode so as to insulate therebetween. An inner wall of the side wall insulation film is in contact with the conductive layer, and an outer wall of the side wall insulation film is in contact with the gate electrode. | 2008-12-04 |
20080296678 | METHOD FOR FABRICATING HIGH VOLTAGE DRIFT IN SEMICONDUCTOR DEVICE - A drift of a high voltage transistor formed using an STI (shallow trench isolation). The method for forming a high voltage drift of a semiconductor device can include forming a pad insulating film on a semiconductor substrate having a high voltage well; and then opening a region of the semiconductor substrate by patterning a portion of the pad insulating film; and then etching the opened region of the semiconductor substrate to form a trench; and then forming a first drift in the semiconductor substrate by performing a first ion implantation process using the patterned pad insulating film as a mask; and then forming a device isolation film by gap-filling a device isolation material in the trench; and then removing the patterned pad insulating film and then forming a gate electrode overlapping a portion of the device isolation film; and then forming a second drift connected to the first drift by performing a second ion implantation process in a region of the semiconductor substrate exposed by the gate electrode. | 2008-12-04 |
20080296679 | Lateral high-voltage transistor with vertically-extended voltage-equalized drift region - A lateral high-voltage device in which conductive trench plates are inserted across the voltage-withstand region, so that, in the on state, the current density vectors have less convergence. This can help reduce on-resistance. | 2008-12-04 |
20080296680 | METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING DOPING A FIN - A method of making an integrated circuit including doping a fin is disclosed. The method includes providing a substrate having at least one fin of a semiconductor material and carrying out a gas-phase doping of the at least one fin. | 2008-12-04 |
20080296681 | CONTACT STRUCTURE FOR FINFET DEVICE - In accordance with an embodiment, a FinFET device includes: one or more fins, a dummy fin, a gate line, a gate contact landing pad, and a gate contact element. Each of the fins extends in a first direction above a substrate. The dummy fin extends in parallel with the fins in the first direction above the substrate. The gate line extends in a second direction above the substrate, and partially wraps around the fins. The gate contact landing pad is positioned adjacent to or above the dummy fin and electrically coupled to the gate line. The gate contact element is electrically coupled to the gate contact landing pad and is positioned to the top surface thereof. | 2008-12-04 |
20080296682 | MOS STRUCTURES WITH REMOTE CONTACTS AND METHODS FOR FABRICATING THE SAME - MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors. | 2008-12-04 |
20080296683 | CARBON NANOTUBE HAVING IMPROVED CONDUCTIVITY, PROCESS OF PREPARING THE SAME, AND ELECTRODE COMPRISING THE CARBON NANOTUBE - Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes are provided | 2008-12-04 |
20080296684 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a semiconductor film provided on the insulating film. The semiconductor substrate includes a region of a first current path including at least one diode, the semiconductor film includes a region of a second current path including at least one diode, the first current path and the second current path are connected in parallel to each other, the region of the first current path includes at least part of an area directly below the region of the second current path, and the first current path has a higher resistance than the second current path. | 2008-12-04 |
20080296685 | ANALOG SWITCH - An analog switch having a low capacitance is achieved. Potentials of input/output terminals of the analog switch and a well potential and a gate potential of an NMOS switching device are operated in synchronization via level shift buffers, thereby cancelling parasitic capacitances present between these elements. | 2008-12-04 |
20080296686 | CIRCUIT BOARD AND DISPLAY APPARATUS - A circuit board includes a transparent circuit substrate, at least one die and at least one electrostatic discharge (ESD) protection circuit. The transparent circuit substrate has a patterned conducting layer. The die is disposed on the transparent circuit substrate and has at least one input/output (I/O) electrical connecting pad. The ESD protection circuit is disposed on the transparent circuit substrate, and the ESD protection circuit is electrically connected with the I/O electrical connecting pad of the die through the patterned conducting layer. A display apparatus including the circuit board is also disclosed. | 2008-12-04 |
20080296687 | FIELD-EFFECT TRANSISTOR (FET) WITH EMBEDDED DIODE - A Field-Effect Transistor (FET) is provided that includes a first portion and a second portion separated from the first portion by a gap. The FET further includes at least one diode embedded within the gap between the first and second portions. | 2008-12-04 |
20080296688 | ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES - An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to V | 2008-12-04 |
20080296689 | Nanotube dual gate transistor and method of operating the same - A nanotube dual gate transistor and associated method of use are provided. The nanotube dual gate transistor includes a substrate, a nanotube material, a source conductor and a drain conductor, a top gate and a back gate. The nanotube material is formed over the substrate having a nanotube channel with a first end and a second end. The source conductor is coupled to the first end of the nanotube channel and the drain conductor is coupled to the second end of the nanotube channel. The back gate is formed under one or more of the devices for receiving a DC signal for establishing a desired optimal operational state of the device(s). The top gate is formed over the nanotube channel for receiving an AC signal for high frequency operation of the device(s) with low gate capacitance. | 2008-12-04 |
20080296690 | Metal interconnect System and Method for Direct Die Attachment - Provided herein is an exemplary embodiment of a semiconductor chip for directly connecting to a carrier. The chip includes a metal layer applied to a top surface of the chip; a passivation layer applied over the metal layer such that portions of the passivation layer is selectively removed to create one or more openings (“bond pads”) exposing portions of the metal layer and one or more solderable metal contact regions formed on each of the one or more openings. The solderable metal contact regions electrically connect to the carrier when the chip is positioned face down on the carrier, supplied with a thin layer of solder and heated. | 2008-12-04 |
20080296691 | Layout methods of integrated circuits having unit MOS devices - A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types. | 2008-12-04 |
20080296692 | TECHNIQUE FOR STRAIN ENGINEERING IN SILICON-BASED TRANSISTORS BY USING IMPLANTATION TECHNIQUES FOR FORMING A STRAIN-INDUCING LAYER UNDER THE CHANNEL REGION - By incorporating a semiconductor species having the same valence and a different covalent radius compared to the base semiconductor material on the basis of an ion implantation process, a strain-inducing material may be positioned locally within a transistor at an appropriate manufacturing stage, thereby substantially not contributing to overall process complexity and also not affecting the further processing of the semiconductor device. Hence, a high degree of flexibility may be provided with respect to enhancing transistor performance in a highly local manner. | 2008-12-04 |
20080296693 | ENHANCED TRANSISTOR PERFORMANCE OF N-CHANNEL TRANSISTORS BY USING AN ADDITIONAL LAYER ABOVE A DUAL STRESS LINER IN A SEMICONDUCTOR DEVICE - By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor. | 2008-12-04 |
20080296694 | Semiconductor Device with Field Plate and Method - A method of making a semiconductor device includes forming shallow trench isolation structures ( | 2008-12-04 |
20080296695 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor is provided. The semiconductor device includes a transistor, a first strain layer and a second strain layer on a substrate. The first strain layer is configured at the periphery of the transistor. The second strain layer covers the transistor and a region exposed by the first strain layer. The stress provided by the second strain layer is different from that by the first strain layer. | 2008-12-04 |
20080296696 | Semiconductor Devices Including Doped Metal Silicide Patterns and Related Methods of Forming Such Devices - Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate. | 2008-12-04 |
20080296697 | Programmable semiconductor interposer for electronic package and method of forming - Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of said interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in said standard interposer to an integrated circuit die encapsulated in said electronic package. Methods of forming said programmable semiconductor interposer and said electronic package are also illustrated. | 2008-12-04 |
20080296698 | METHOD FOR SUPPRESSING LAYOUT SENSITIVITY OF THRESHOLD VOLTAGE IN A TRANSISTOR ARRAY - A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout | 2008-12-04 |
20080296699 | SEMICONDUCTOR DEVICE IN PERIPHERAL CIRCUIT REGION USING A DUMMY GATE - A semiconductor device in a peripheral circuit region includes a semiconductor substrate having a plurality of active areas which are disposed distantly from each other; a gate pattern including at least one gate disposed on the active area; a dummy gate disposed between the active areas and first and second pads; first and second pads connected to both sides of the gate and the dummy gate, respectively; and a first wiring formed so as to be in contact with at least one of the first and second pads. | 2008-12-04 |
20080296700 | METHOD OF FORMING GATE PATTERNS FOR PERIPHERAL CIRCUITRY AND SEMICONDUCTOR DEVICE MANUFACTURED THROUGH THE SAME METHOD - A method for forming gate patterns for a semiconductor device includes defining a cell array region and a peripheral region on a substrate. A layout is defined in a peripheral region. The layout comprises patterns having a plurality of fingers that extend along a first direction, wherein the fingers are spaced apart from adjacent fingers in a second direction at substantially the same interval, the patterns including gate patterns. | 2008-12-04 |
20080296701 | ONE-TIME PROGRAMMABLE READ-ONLY MEMORY - A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a gate dielectric layer, a first gate and a second gate. The substrate is of a first conductive type. The first doped region and the second doped region are of a second conductive type and are separately disposed in the substrate. The gate dielectric layer is disposed on the substrate between the first doped region and the second doped region. The first gate and the second gate are disposed on the gate dielectric layer, respectively. The first gate is adjacent to the first doped region, while the second gate is adjacent to the second doped region. Here, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. | 2008-12-04 |
20080296702 | Integrated circuit structures with multiple FinFETs - A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space. | 2008-12-04 |
20080296703 | Method for Producing a Field-Effect Transistor, Field-Effect Transistor and Integrated Circuit Arrangement - A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods. | 2008-12-04 |
20080296704 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Top and bottom surfaces of a gate insulating film are terminated with fluorine atoms and the top surface of the gate insulating film is then etched. New dangling bonds are formed on the top surface of the gate insulating film. Such new dangling bonds are terminated with nitrogen atoms. A semiconductor device is thus obtained that has a silicon substrate and a gate insulating film formed on the silicon substrate and that almost all dangling bonds on the top surface of the gate insulating film are terminated with nitrogen atoms and almost all dangling bonds on the bottom surface contacting the silicon substrate are terminated with fluorine atoms. | 2008-12-04 |
20080296705 | GATE AND MANUFACTURING METHOD OF GATE MATERIAL - A gate including a conductive buffer layer and a conductive layer is provided. The conductive buffer layer is disposed on a gate dielectric layer, and the average grain size of the conductive buffer layer is less than 100 nm. The conductive layer is disposed on the conductive buffer layer, and the average grain size of the conductive layer is greater than or equal to 100 nm. The disposition of the conductive buffer layer reduces the undesired effect caused by noise and dark current to the performance of the device. | 2008-12-04 |
20080296706 | COBALT DISILICIDE STRUCTURE - A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon. | 2008-12-04 |
20080296707 | SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES - A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region. | 2008-12-04 |
20080296708 | Integrated sensor arrays and method for making and using such arrays - The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer. | 2008-12-04 |
20080296709 | Chip assembly - The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip. | 2008-12-04 |
20080296710 | Photoconductive Metamaterials with Tunable Index of Refraction - Materials and structures whose index of refraction can be tuned over a broad range of negative and positive values by applying above band-gap photons to a structure with a strip line element, a split ring resonator element, and a substrate, at least one of which is a photoconductive semiconductor material. Methods for switching between positive and negative values of n include applying above band-gap photons to different numbers of elements. In another embodiment, a structure includes a photoconductive semiconductor wafer, the wafer operable to receive above band-gap photons at an excitation frequency in an excitation pattern on a surface of the wafer, the excitation patterns generating an effective negative index of refraction. Methods for switching between positive and negative values of n include projecting different numbers of elements on the wafer. The resonant frequency of the structure is tuned by changing the size of the split ring resonator excitation patterns. | 2008-12-04 |
20080296711 | MAGNETOELECTRONIC DEVICE HAVING ENHANCED PERMEABILITY DIELECTRIC AND METHOD OF MANUFACTURE - A magnetoelectronic device structure | 2008-12-04 |