49th week of 2009 patent applcation highlights part 17 |
Patent application number | Title | Published |
20090294767 | Isolated Sensor Structures Such As For Flexible Substrates - A photosensor structure includes a pixel metal layer disposed in physical and electrical contact with a pixel thin film transistor and a lower sensor layer of a p-i-n photosensor. The pixel metal layer extends laterally to an extent less that the lower sensor layer such that an overhang region is defined below the lower sensor layer and the adjacent the lateral edge of the pixel metal layer. When the relatively thick intrinsic sensor layer is formed over the lower sensor layer, it attaches to the upper surface and, due to the presence of the overhang region, the lateral edge of the lower sensor layer, forming a discrete intrinsic sensor layer structure over the pixel which is physically isolated from adjacent corresponding structures. This isolation allows for thermal expansion and contraction during formation of the intrinsic sensor layer without cracking the intrinsic sensor layer structure. | 2009-12-03 |
20090294768 | SELF-ALIGNED THIN-FILM TRANSISTOR AND METHOD OF FORMING SAME - A method of manufacturing a thin-film transistor or like structure provides conductive “tails” below an overhang region formed by a top gate structure. The tails increase in thickness as they extend outward from a point under the overhang to the source and drain contacts. The tails provide a low resistance conduction path between the source and drain regions and the channel, with low parasitic capacitance. The thickness profile of the tails is controlled by the deposition of material over and on the lateral side surfaces of the gate structure. | 2009-12-03 |
20090294769 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - According to a method of manufacturing a semiconductor device of the present invention, a gate electrode is formed above a substrate, and a insulating film is formed above the gate electrode. Then, an amorphous semiconductor film is formed above the insulating film, laser annealing is performed on the amorphous semiconductor film, and the amorphous semiconductor film is changed to a crystalline semiconductor film. After that, hydrofluoric acid processing is performed on the crystalline semiconductor film, and an amorphous semiconductor film is formed above the crystalline semiconductor film where the hydrofluoric acid processing is performed so that pattern ends of the amorphous semiconductor film are arranged outside pattern ends of the crystalline semiconductor film and the amorphous semiconductor film contacts with the insulating film near the pattern ends. | 2009-12-03 |
20090294770 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, first, second, and third gate lines disposed over the substrate, the first and second gate lines defining a first trench with a first aspect ratio, the second and third gate lines defining a second trench with a second aspect ratio, a first insulating layer formed to decrease the first and second aspect ratios, and a second insulating layer disposed over the first insulating layer to fill the first and second trenches. | 2009-12-03 |
20090294771 | THIN FILM TRANSISTOR ARRAY PANEL HAVING A MEANS FOR ARRAY TEST - A substrate for a display panel includes a base substrate, a plurality of signal lines, a plurality of signal pads corresponding to first end portions of the signal lines, a shorting bar corresponding to second end portions of the signal lines, a plurality of bridge lines on the base substrate disposed between the signal line and the shorting bar which electrically connects the signal line and the shorting bar. A color filter array panel opposite a TFT LCD panel substrate includes a medium dam layer which fully overlaps the bridge lines of the TFT LCD panel substrate. A data TFT for inspection having a source electrode coupled to the signal line, a drain electrode coupled to any one of the shorting bars, and a gate electrode coupled to a data TFT driving signal line ensures the normal operation of the display panel after the array test. | 2009-12-03 |
20090294772 | Thin film transistor, method of manufacturing the same and flat panel display device having the same - A thin film transistor is provided having an oxide semiconductor as an active layer, a method of manufacturing the thin film transistor and a flat panel display device having the thin film transistor. The thin film transistor includes: a gate electrode formed on a substrate; an oxide semiconductor layer isolated from the gate electrode by a gate insulating layer and including channel, source and drain regions; source and drain electrodes coupled to the source and drain regions, respectively; and an ohmic contact layer interposed between the source and drain regions and the source and drain electrodes. In the TFT, the ohmic contact layer is formed with the oxide semiconductor layer having a carrier concentration higher than those of the source and drain regions. | 2009-12-03 |
20090294773 | BOROALUMINO SILICATE GLASSES - Disclosed are alkali-free glasses having a liquidus viscosity of greater than or equal to about 90,000 poises, said glass comprising SiO | 2009-12-03 |
20090294774 | MANUFACTURING METHOD OF GaN THIN FILM TEMPLATE SUBSTRATE, GaN THIN FILM TEMPLATE SUBSTRATE AND GaN THICK FILM SINGLE CRYSTAL - Provided are a manufacturing method of a GaN single crystal in which the film thickness of the GaN single crystal can be controlled accurately, even when a hydride vapor phase epitaxy is applied; a GaN thin film template substrate which is suitable for growing a GaN thick film with a fine property; and a GaN single crystal growing apparatus. Provided is a manufacturing method of a GaN single crystal by a hydride vapor phase epitaxy, wherein the hydride vapor phase epitaxy comprises: spraying HCl (hydrogen chloride) onto Ga (gallium) which is heated and fused in a predetermined temperature to generate GaCl (gallium chloride); and forming a GaN thin film by a reaction of the generated GaCl (gallium chloride) with NH | 2009-12-03 |
20090294775 | HEXAGONAL WURTZITE TYPE EPITAXIAL LAYER POSSESSING A LOW ALKALI-METAL CONCENTRATION AND METHOD OF CREATING THE SAME - A method of obtaining a hexagonal würtzite type epitaxial layer with a low impurity concentration of alkali-metal by using a hexagonal würtzite substrate possessing a higher impurity concentration of alkali-metal, wherein a surface of the substrate upon which the epitaxial layer is grown has a crystal plane which is different from the c-plane. | 2009-12-03 |
20090294776 | Highly Oxygen-Sensitive Silicon Layer and Method for Obtaining Same - Silicon layer highly sensitive to oxygen and method for obtaining said layer. | 2009-12-03 |
20090294777 | METHOD FOR FORMING A GROUP III NITRIDE MATERIAL ON A SILICON SUBSTRATE - Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 μmol/cm | 2009-12-03 |
20090294778 | LIGHT-EMITTING DEVICE, DISPLAY APPARATUS, AND ELECTRONIC SYSTEM - A light-emitting device includes a cathode, an anode, a first light-emitting layer that is disposed between the cathode and the anode and that emits light of a first color, a second light-emitting layer that is disposed between the first light-emitting layer and the cathode and that emits light of a second color different from the first color, and an intermediate layer that is disposed between and in contact with the first light-emitting layer and the second light-emitting layer and that contains a first material and a second material different from the first material. The light-emitting device satisfies inequality (1): | 2009-12-03 |
20090294779 | Electronic element wafer module, method for manufacturing an electronic element wafer module, electronic element module,and electronic information device - An electronic element wafer module according to the present invention is provided, in which a translucent support substrate for covering and protecting a plurality of electronic elements is attached on an electronic element wafer having the plurality of electronic elements formed thereon, and an optical filter is formed corresponding to the electronic elements on at least one surface of the translucent support substrate, where the optical filter is removed to lessen warping along a part or all of dicing lines for individually dividing the electronic element wafer module into a plurality of electronic element modules. | 2009-12-03 |
20090294780 | LIGHT EMITTING DEVICE - A light emitting device comprises: a plurality of light emitting diodes and an insulating (low temperature co-fired ceramic) substrate with an array of recesses each for housing a respective one of the light emitting diodes. The substrate incorporates a pattern of electrical conductors that is configured for connecting the light emitting diodes in a selected electrical configuration and to provide at least two electrical connections on the floor of each recess. Light emitting diodes can be electrically connected to the electrical connections by at least one bond wire or by flip chip bonding. Each recess is filled with a transparent material to encapsulate each light emitting diode. The transparent material can incorporate at least one phosphor material such that the device emits light of a selected color and/or color temperature. | 2009-12-03 |
20090294781 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating an array substrate for a liquid crystal display device includes: forming an initial photoresist (PR) pattern on a metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process; forming a source electrode and a drain electrode on the substrate. | 2009-12-03 |
20090294782 | Light emitting diode lamp package structure and assembly thereof - The present invention provides a light emitting diode (LED) lamp package structure characterized in which a plurality of light emitting diodes, a control integrated circuit, a circuit board and four electric conductivity supports are encapsulated inside a package body where the electric conductivity supports are respectively a Vdd pad, a data input pad, a data output pad, and a Vss pad. The present invention further provides a LED lamp assembly, comprising a LED lamp, a lampshade, a socket, and a mount formed with a socket. After the LED lamp is mounted on the socket with the four electric conductivity supports exposed and the socket is plugged into the socket of the mount, the electric conductivity supports would contact the four electrode contacts in the socket where the four electrode contacts are respectively a positive DC voltage electrode, a data input electrode, a data output electrode and a negative DC voltage electrode. | 2009-12-03 |
20090294783 | Process to fabricate integrated mwir emitter - A device for medium wavelength infrared emission and a method for the manufacture thereof is provided. The device has a semiconductor substrate; a passive hermetic barrier disposed upon the substrate, and an emitter element disposed within said hermetic barrier; and a mirror. | 2009-12-03 |
20090294784 | Nitride Semiconductor Light Emitting Element and Method for Producing Nitride Semiconductor Light Emitting Element - Provided are a nitride semiconductor light emitting element which does not suffer a damage on a light emitting region and has a high luminance without deterioration, even though the nitride semiconductor light emitting element is one in which electrodes are disposed opposite to each other and an isolation trench for chip separation and laser lift-off is formed by etching; and a manufacturing method thereof. An n-type nitride semiconductor layer | 2009-12-03 |
20090294785 | LED DEVICE STRUCTURE TO IMPROVE LIGHT OUTPUT - A light-emitting device, including a substrate; a LED element formed over the substrate including a transparent or semi-transparent electrode, a reflective electrode, and one or more layers, at least one of which is light-emitting, formed between the transparent or semi-transparent electrode and reflective electrode, the transparent or semi-transparent electrode and reflective electrode defining a single, controllable light-emitting area, wherein the LED element emits light into a waveguide defined by the transparent or semi-transparent electrode, reflective electrode, and the one or more layers; and one or more first topographical features and one or more second topographical features different from the first topographical features formed over the substrate within the single, controllable light-emitting area, wherein the first and second topographical features disrupt the waveguiding of light within the single, controllable light-emitting area to increase the emission of light in at least one direction. | 2009-12-03 |
20090294786 | LIGHT EMITTING DIODE DEVICE - A light emitting diode device includes a substrate, a plurality of light emitting diode chips mounted on the substrate and arranged in a plurality of lines and a frame located on the substrate. The frame includes a plurality of first plates each extending along a first direction of the substrate, a plurality of second plates each extending along a second direction of the substrate and a plurality of reflecting plates. The first plates and the second plates cooperatively form a plurality of receiving rooms for receiving the light emitting diode chips therein. Each reflecting plate is located above a corresponding line of light emitting diode chips and inclined with respect to the substrate. | 2009-12-03 |
20090294787 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a distributed Bragg reflection layer of a first conductivity type, a distortion elaxation layer of the first conductivity type, a light absorbing layer, and a semiconductor layer of a second conductivity type, sequentially arranged on a semiconductor substrate. The distortion relaxation layer the same material as the semiconductor substrate. The total optical length of layers between the distributed Bragg reflection layer and the light absorbing layer is an integer multiple of one-half the wavelength of incident light that is detected. | 2009-12-03 |
20090294788 | LIGHT EMITTING DEVICE WITH A NON-ACTIVATED LUMINESCENT MATERIAL - The invention relates to a light emitting device having a radiation emitting element, for example a light emitting diode, and a luminescent material which is able to absorb a part of the radiation sent out by the radiation emitting element and to send out light with a wavelength which is different from the wavelength of the absorbed radiation. The device further has diffusing particles which are able to scatter a part of the radiation sent out by the radiation emitting element, and/or to scatter a part of the light sent out by the luminescent material. The diffusing particles are of non-activated luminescent material, through which production is simplified. | 2009-12-03 |
20090294789 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element emitting light, a first substrate on which the light emitting element is mounted, a second substrate forming a sealing space for the light emitting element between the first substrate and the second substrate and a light exiting window for allowing light emitted from the light emitting element to exit, in which at least one of the first substrate and the second substrate has cleavage characteristics and a cleavage plane thereof serves as a window attaching surface to which the light exiting window is attached. | 2009-12-03 |
20090294790 | ELECTROLUMINESCENT DEVICE AND FABRICATION METHOD THEREOF - An electroluminescent device includes a conduction substrate, a reflection layer, a patterned transparent conduction layer, at least one light emitting diode (LED) element, a first contact electrode and a second contact electrode. The reflection layer is disposed on the conduction substrate, and the patterned transparent conduction layer is formed on the reflection layer. The LED element is formed on the patterned transparent conduction layer, and the LED element includes a first semiconductor layer, a light emitting layer and a second semiconductor layer in sequence. The second semiconductor layer is disposed on the patterned transparent conduction layer and the reflection layer. The first contact electrode is disposed at one side of the first semiconductor layer, and the second contact electrode is disposed at one side of the conduction substrate. | 2009-12-03 |
20090294791 | ELECTRODE FOR SEMICONDUCTOR LIGHT EMITTING DEVICE - An object of the present invention is to provide an electrode that can produce powerful light emission with low driving voltage, without reducing crystallinity. | 2009-12-03 |
20090294792 | CARD TYPE MEMORY PACKAGE - A card-type memory package is revealed, primarily comprising a substrate, a plurality of gold fingers, at least a memory chip, an LED chip, and an encapsulant. The memory chip and the LED chip are disposed on an encapsulated surface of the substrate with the LED chip adjacent to a rear side of the substrate. The gold fingers are attached to the substrate adjacent to a front side of the substrate. The encapsulant is formed on the encapsulated surface to encapsulate the memory chip and the LED chip with the gold fingers exposed. Therefore, the card-type memory package has the LED indication of reading and writing information with simplified assembling processes. | 2009-12-03 |
20090294793 | LED PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is an LED package including a heat radiating portion that is composed of two or more metal layers and has a cavity formed therein; a first lead that extends from one side of the heat radiating portion; a second lead that is formed in the other side of the heat radiating portion so as to be separated from the heat radiating portion; a mold portion that fixes the heat radiating portion and the first and second leads; an LED chip that is mounted in the cavity; and a first filler that is filled in the cavity so as to protect the LED chip. | 2009-12-03 |
20090294794 | Method of manufacturing organic light emitting display and organic light emitting display - A method of manufacturing an organic light emitting display includes: forming a transistor on a substrate; forming a cathode electrode on the transistor to be connected to a source or a drain of the transistor; forming a bank layer having an opening on the cathode electrode; allowing a natural oxide layer to form on the cathode electrode; removing the natural oxide layer from the cathode electrode; forming an insulating buffer layer on the cathode electrode; forming an organic light emitting layer on the insulating buffer layer; and forming an anode electrode on the organic light emitting layer. | 2009-12-03 |
20090294795 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A light emitting device includes a light emitting layer made of semiconductor; an upper electrode including a bonding electrode capable of connecting a wire thereto and a thin-wire electrode surrounding the bonding electrode with a spacing and including a junction with the bonding electrode, and a current diffusion layer provided between the light emitting layer and the upper electrode and made of semiconductor, the current diffusion layer including a recess that is formed in a non-forming region of the upper electrode and capable of emitting light emitted from the light emitting layer. | 2009-12-03 |
20090294796 | Adhesive-Promoting Agent, Curable Organopolysiloxane Composition, and Semiconductor Device - An adhesion-promoting agent represented by the following average formula: R | 2009-12-03 |
20090294797 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light-emitting device according to the present invention includes: a GaN substrate | 2009-12-03 |
20090294798 | Bipolar Device Compatible with CMOS Process Technology - A bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device. | 2009-12-03 |
20090294799 | SEMICONDUCTOR DEVICE - A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor. | 2009-12-03 |
20090294800 | HYBRID FET INCORPORATING A FINFET AND A PLANAR FET - A stack of a vertical fin and a planar semiconductor portion are formed on a buried insulator layer of a semiconductor-on-insulator substrate. A hybrid field effect transistor (FET) is formed which incorporates a finFET located on the vertical fin and a planar FET located on the planar semiconductor portion. The planar FET enables a continuous spectrum of on-current. The surfaces of the vertical fin and the planar semiconductor portion may be set to coincide with crystallographic orientations. Further, different crystallographic orientations may be selected for the surfaces of the vertical fin and the surfaces of the planar semiconductor portion to tailor the characteristics of the hybrid FET. | 2009-12-03 |
20090294801 | METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE - Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned. | 2009-12-03 |
20090294802 | FIELD EFFECT TRANSISTOR WITH FREQUENCY DEPENDENT GATE-CHANNEL CAPACITANCE - A field effect transistor having a channel, a gate, and a means for decreasing a gate-to-channel capacitance of the transistor as an operating frequency of the transistor increases. The means can comprise, for example, a barrier layer disposed between the gate and the channel, which has a dielectric permittivity and/or a conductivity that varies with an operating frequency of the transistor. In an embodiment, the barrier layer comprises a conducting material, such as conducting polymer, conducting semiconductor, conducting semi-metal, amorphous silicon, polycrystalline silicon, and/or the like. | 2009-12-03 |
20090294803 | METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 2009-12-03 |
20090294804 | HIGH-EFFICIENCY THINNED IMAGER WITH REDUCED BORON UPDIFFUSION - A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator wafer (UTSOI) is disclosed. The UTSOI wafer includes a mechanical substrate, an insulator layer, and a seed layer. At least one dopant is applied to the semiconductor substrate. A first portion of an epitaxial layer is grown on the seed layer. A predefined concentration of carbon impurities is introduced into the first portion of the epitaxial layer. A remaining portion of the epitaxial layer is grown. During the epitaxial growth process, the at least one dopant diffuses into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile which has an initial maximum value at an interface between the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within at least a portion of at least one of the semiconductor substrate and the epitaxial layer. | 2009-12-03 |
20090294805 | Virtual semiconductor nanowire, and methods of using same - A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone. | 2009-12-03 |
20090294806 | Method of Improving Minority Lifetime in Silicon Channel and Products Thereof - Performance of field effect transistors and other channel dependent devices formed on a monocrystalline substrate is improved by carrying out a high temperature anneal in a nitrogen releasing atmosphere while the substrate is coated by a sacrificial oxide coating containing easily diffusible atoms that can form negatively charged ions and can diffuse deep into the substrate. In one embodiment, the easily diffusible atoms comprise at least 5% by atomic concentration of chlorine atoms in the sacrificial oxide coating and the nitrogen releasing atmosphere includes NO. The high temperature anneal is carried out for less than 10 hours at a temperature less than 1100° C. | 2009-12-03 |
20090294807 | Methods of Fabricating Transistors and Structures Thereof - Methods of fabricating transistors, semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, and forming a gate over the gate dielectric. Sidewall spacers are formed over the gate dielectric and the gate, the sidewall spacers comprising germanium oxide (GeO or GeO | 2009-12-03 |
20090294808 | Thin Film Transistor, Method for Manufacturing the Same and Film Formation Apparatus - One embodiment of the present invention is a method for manufacturing a bottom gate type thin film transistor having a gate electrode, a gate insulating film, an oxide semiconductor active layer, a source electrode and a drain electrode on a flexible plastic substrate of a supporting substrate, the method including continuously forming the gate insulating film and the oxide semiconductor active layer on the flexible plastic substrate with the gate electrode inside a vacuum film formation chamber of a film formation apparatus, the apparatus being a type of winding up continuously the roll-shaped substrate, and the gate insulating film and the oxide semiconductor active layer formed without being exposed to air. | 2009-12-03 |
20090294809 | REDUCTION OF METAL SILICIDE DIFFUSION IN A SEMICONDUCTOR DEVICE BY PROTECTING SIDEWALLS OF AN ACTIVE REGION - By protecting sidewall portions of active semiconductor regions during a silicidation process, the probability of creating nickel silicide pipes may be reduced. Consequently, yield losses caused by the shorting of PN junctions in sophisticated semiconductor devices may be reduced. | 2009-12-03 |
20090294810 | MICROSTRUCTURE DEVICE INCLUDING A COMPRESSIVELY STRESSED LOW-K MATERIAL LAYER - A nitrogen-containing silicon carbide material may be deposited on the basis of a single frequency or mixed frequency deposition recipe with a high internal compressive stress level up to 1.6 GPa or higher. Thus, this dielectric material may be advantageously used in the contact level of sophisticated integrated circuits, thereby providing high strain levels while not unduly contributing to signal propagation delay. | 2009-12-03 |
20090294811 | IMAGE SENSOR WITH BACKSIDE PASSIVATION AND METAL LAYER - An image sensor includes a semiconductor layer that low-pass filters light of different wavelengths. For example, the semiconductor layer proportionately absorbs photons of shorter wavelengths and proportionately passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed on a front surface of the semiconductor layer, where the photodiode is an N | 2009-12-03 |
20090294812 | Optical Sensor Including Stacked Photosensitive Diodes - A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes. | 2009-12-03 |
20090294813 | Optical Sensor Including Stacked Photodiodes - A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes. | 2009-12-03 |
20090294814 | Three-Dimensional Integrated Circuits and Techniques for Fabrication Thereof - Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer. | 2009-12-03 |
20090294815 | SOLID STATE IMAGING DEVICE INCLUDING A SEMICONDUCTOR SUBSTRATE ON WHICH A PLURALITY OF PIXEL CELLS HAVE BEEN FORMED - A solid state imaging device including a pixel region where a plurality of pixel cells | 2009-12-03 |
20090294816 | CMOS image sensor and driving method of the same - Provided are a CMOS image sensor and a driving method thereof. The CMOS image sensor may include a photodetector disposed in a semiconductor substrate to accumulate photocharges, a charge transfer element configured to control transfer of the photocharges accumulated in the photodetector, a detecting element configured to detect the photocharges transferred by the charge transfer element, and a well driving contact configured to increase a potential difference between the photodetector and the detecting element while the photocharges are transferred. | 2009-12-03 |
20090294817 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device comprising a dielectric layer comprising a mixture and/or a compound that comprises a ferroelectric organic polymer and an oxidiser and/or deioniser, and a pair of electrodes configured to apply an electric field to the dielectric layer. Also a method of fabricating a memory device. | 2009-12-03 |
20090294818 | FERROELECTRIC POLYMER - A ferroelectric film comprising polyaminodifluoroborane (PADFB). Also a memory device utilizing the ferroelectric film, a method of fabricating a ferroelectric polymer and a ferroelectric solution. | 2009-12-03 |
20090294819 | METHODS FOR ENHANCING CAPACITORS HAVING ROUGHENED FEATURES TO INCREASE CHARGE-STORAGE CAPACITY - Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material. | 2009-12-03 |
20090294820 | Capacitors and Methods of Manufacture Thereof - Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece. | 2009-12-03 |
20090294821 | SEMICONDUCTOR DEVICE HAVING DRIVING TRANSISTORS - One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion. | 2009-12-03 |
20090294822 | CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT - A microelectronic device comprising:
| 2009-12-03 |
20090294823 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT USING A SELECTIVE DISPOSAL SPACER TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED THEREBY - Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns. | 2009-12-03 |
20090294824 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A first select transistor is connected to one end of a plurality of memory cell transistors that are serially connected. A second select transistor is connected to the other end of the serially connected memory cell transistors. A first impurity diffusion region is formed in a semiconductor substrate and constitutes a first main electrode of the first select transistor. A second impurity diffusion region is formed in the semiconductor substrate and constitutes a second main electrode of the second select transistor. A depth of the first impurity diffusion region is greater than a depth of the second impurity diffusion region. | 2009-12-03 |
20090294825 | STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an integrated circuit including at least one storage cell is provided. The method includes providing a substrate having a first and second side, and a plurality of parallel trenches so that a dividing wall is formed between adjacent trenches, filling the trenches with an insulating compound, providing a first insulating layer having a first and second side on the top surface of the dividing wall, wherein the first side is arranged on the substrate's first side, providing a first conductive layer having a first and second side, wherein the first side is arranged on the insulating layer's second side, wherein the conductive layer protrudes from the substrate surface, providing a second conductive layer having a first and second side, wherein the first side is located on the first conductive layer's second side, and removing parts of the second conductive layer by an anisotropic etching means. | 2009-12-03 |
20090294826 | Semiconductor Device and Method of Fabricating the Same - Provided are semiconductor devices and methods of fabricating the same. The semiconductor device comprises: a floating gate pattern formed in a cell area of a semiconductor substrate; a dummy floating gate pattern extending from the floating gate pattern into an interface area around the cell area; and a control gate pattern intersecting the floating gate pattern at the cell area of the semiconductor substrate. | 2009-12-03 |
20090294827 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved. | 2009-12-03 |
20090294828 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode. | 2009-12-03 |
20090294829 | NAND FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory in which each memory cell in a NAND flash memory includes a columnar floating gate formed on an element region with a gate insulating film interposed between the floating gate and the element region, diffusion layers formed at portions of the element region located below both sides of the floating gate, and a control gate formed so as to surround the floating gate with an IPD film interposed between the control gate and the floating gate, the IPD film formed on a side surface of the floating gate. | 2009-12-03 |
20090294830 | MEMORY DEVICE WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRICS AND METAL FLOATING GATES - A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator. | 2009-12-03 |
20090294831 | Semiconductor Constructions, Methods Of Forming Transistor Gates, And Methods Of Forming NAND Cell Units - Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures. | 2009-12-03 |
20090294832 | Semiconductor Device - One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope. | 2009-12-03 |
20090294833 | Semiconductor memory device and method of fabricating the same - A semiconductor memory device includes a memory substrate including memory transistors and vertical active pillars, the vertical active pillars defining active regions of the memory transistors, a peripheral circuit substrate including peripheral circuit transistors, a bonding layer interposed between the memory substrate and the peripheral circuit substrate, and a connection structure electrically connecting the memory transistors to the peripheral circuit transistors. | 2009-12-03 |
20090294834 | NONVOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE, AND METHOD OF MANUFACTURING FLAT PANEL DISPLAY DEVICE PROVIDED WITH THE NONVOLATILE MEMORY DEVICE - Provided are a nonvolatile memory device, a method of manufacturing the nonvolatile memory device, and a method of manufacturing a flat panel display device provided therein with the nonvolatile memory device. According to an embodiment, an amorphous silicon layer is formed on a substrate, and then annealed by using an Excimer laser to form a crystallized silicon layer. A nitrogen plasma treatment is performed for the crystallized silicon layer to planarize an upper surface of the crystallized silicon layer. An ONO layer is formed on the nitrogen plasma-treated crystallized silicon layer. A metal layer is formed on the ONO layer. The metal layer, the ONO layer and the nitrogen plasma-treated crystallized silicon layer are patterned. | 2009-12-03 |
20090294835 | SEMICONDUCTOR MEMORY DEVICE INCLUDING LAMINATED GATE HAVING ELECTRIC CHARGE ACCUMULATING LAYER AND CONTROL GATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first active region, a second active region, an element isolation region, memory cell transistors. Each of memory cell transistors includes a laminated gate and a first impurity diffusion layer functioning as a source and a drain. The laminated gate includes a first insulating film, a second insulating film, and a control gate electrode. The second insulating film is commonly connected between the plurality of memory cell transistors to step over the element isolation region and is in contact with an upper surface of the element isolation region. An upper surface of the element isolation region is higher than a bottom surface of the first insulating film and is located under the upper surface of the first insulating film. | 2009-12-03 |
20090294836 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion. | 2009-12-03 |
20090294837 | Nonvolatile Memory Devices Having a Fin Shaped Active Region - A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region. | 2009-12-03 |
20090294838 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer. | 2009-12-03 |
20090294839 | RECESSED CHANNEL ARRAY TRANSISTOR (RCAT) STRUCTURES AND METHOD OF FORMATION - Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure. | 2009-12-03 |
20090294840 | METHODS OF PROVIDING ELECTRICAL ISOLATION AND SEMICONDUCTOR STRUCTURES INCLUDING SAME - Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase the effective gate length (“L | 2009-12-03 |
20090294841 | Formation of a MOSFET Using an Angled Implant - A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n | 2009-12-03 |
20090294842 | METHODS OF FORMING DATA CELLS AND CONNECTIONS TO DATA CELLS - Disclosed are methods and devices, among which is a method that includes forming a lower conductive material on a substrate, forming a stop material on the substrate, forming a sacrificial material on the substrate, etching the sacrificial material with an etch that is selective to the sacrificial material and selective against the stop material, and etching the lower conductive material. | 2009-12-03 |
20090294843 | ENCLOSED VOID CAVITY FOR LOW DIELECTRIC CONSTANT INSULATOR - Field effect devices and ICs ( | 2009-12-03 |
20090294844 | SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section. | 2009-12-03 |
20090294846 | TRENCH-TYPE POWER MOS TRANSISTOR AND INTEGRATED CIRCUIT UTILIZING THE SAME - A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region. | 2009-12-03 |
20090294847 | Plasma Display Apparatus - A plasma display apparatus which in its driving circuit mounts at least one of IGBTs having diodes built-in which are reverse conducting in a driving device which supplies a light emitting current and IGBTs having diodes built-in which have a reverse blocking function in a driving device which collects and charges the power. | 2009-12-03 |
20090294849 | RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices ( | 2009-12-03 |
20090294850 | METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE - The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer. | 2009-12-03 |
20090294851 | Semiconductor Device and Method for Fabricating the Same - A method for fabricating a semiconductor device comprises: performing a thermal process to expanding a local doped region formed between gate patterns on a semiconductor substrate; and etching a central region of an expanded local doped region so that the expanded local doped region remains at the total area of sidewalls of floating bodies isolated from each other. | 2009-12-03 |
20090294852 | Electronic device - A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator. | 2009-12-03 |
20090294853 | THIN FILM TRANSISTOR HAVING A COMMON CHANNEL AND SELECTABLE DOPING CONFIGURATION - Methods and apparatus for producing a thin film transistor (TFT) result in: a semiconductor layer; a channel region formed on or in the semiconductor layer and having first and second opposing ends, and having third and fourth opposing ends transverse to the first and second ends; an n-type source structure disposed on or in the semiconductor layer adjacent to the first end of the channel; an n-type drain structure disposed on or in the semiconductor layer adjacent to the second end of the channel; a p-type source structure disposed on or in the semiconductor layer adjacent to the third end of the channel; a p-type drain structure disposed on or in the semiconductor layer adjacent to the fourth end of the channel; and a gate structure disposed over the channel region. | 2009-12-03 |
20090294854 | HALO-FIRST ULTRA-THIN SOI FET FOR SUPERIOR SHORT CHANNEL CONTROL - Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes. | 2009-12-03 |
20090294855 | Electrostatic Discharge Protection Device - An electrostatic discharge protection device includes a first well comprising a MOS transistor; a second well comprising a first impurity region to which a first voltage is applied, and a second impurity region connected to an input/output pad, the second well being disposed adjacent to the first well; and a third well comprising a third impurity region to which the first voltage is applied, the third well being disposed adjacent to the second well. | 2009-12-03 |
20090294856 | I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS - A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps. | 2009-12-03 |
20090294857 | Method for Manufacturing Semiconductor Apparatus Having Saddle-Fin Transistor and Semiconductor Apparatus Fabricated Thereby - A method for manufacturing a semiconductor memory apparatus may include forming a channel region and a gate region through a self-alignment etching process on a cell region; and forming a three-dimensional multi-channel region through an etching process using a first multi-channel mask on a core region and a peripheral region and forming a gate region through an etching process using a second multi-channel mask, thereby preventing mis-arrangement of gates. | 2009-12-03 |
20090294858 | TRANSISTOR WITH CONTACT OVER GATE ACTIVE AREA - A transistor contact over a gate active area includes a transistor gate formed on a substrate of an integrated circuit. A gate insulator is formed beneath the transistor gate and helps define an active area for the transistor gate. An insulating layer is formed over the transistor gate. A metal contact plug is formed within a portion of the insulating layer that lies over the active area such that the metal contact plug forms an electrical contact with the transistor gate. | 2009-12-03 |
20090294859 | Trench MOSFET with embedded junction barrier Schottky diode - A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates. | 2009-12-03 |
20090294860 | IN SITU FORMED DRAIN AND SOURCE REGIONS IN A SILICON/GERMANIUM CONTAINING TRANSISTOR DEVICE - By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes. | 2009-12-03 |
20090294861 | SRAM MEMORY CELL HAVING TRANSISTORS INTEGRATED AT SEVERAL LEVELS AND THE THRESHOLD VOLTAGE VT OF WHICH IS DYNAMICALLY ADJUSTABLE - A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises: | 2009-12-03 |
20090294862 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND FABRICATING METHOD THEREOF - Disclosed are a non-volatile semiconductor memory device capable of simplifying the complicated structure of a transistor, and a fabrication method for the same. The non-volatile semiconductor memory device includes a semiconductor substrate including a plurality of active regions, gate electrodes formed over the respective active regions of the semiconductor substrate, gate spacers formed over both sides of each of the gate electrodes, common source/drain regions formed on the surface of the semiconductor substrate at both sides of the gate electrode including the gate spacers, an interlayer dielectric formed over the whole surface of a resultant structure including the substrate, gate electrodes, gate spacers and common source/drain regions, and contact plugs penetrating the interlayer dielectric, and connecting the common source/drain regions to a data line, wherein the contact plugs are made from a material which becomes electrically conductive when in contact with light and becomes non-conductive when out of contact with light. | 2009-12-03 |
20090294863 | Semiconductor Memory Device Having Three Dimensional Structure - A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers. | 2009-12-03 |
20090294864 | MOS FIELD EFFECT TRANSISTOR HAVING PLURALITY OF CHANNELS - A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed. | 2009-12-03 |
20090294865 | Schottky Diodes Having Low-Voltage and High-Concentration Rings - An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions. | 2009-12-03 |
20090294866 | Transistor Fabrication Methods and Structures Thereof - Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric. | 2009-12-03 |
20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 2009-12-03 |
20090294868 | DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY INDUCING DIFFERENT LATERAL STRAIN LEVELS IN THE ACTIVE REGION - The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of a strain-inducing mechanism, such as a stressed dielectric material and a stress memorization technique, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices in which a pronounced variation of the transistor width may be used to adjust the ratio of the drive current capabilities for the pull-down transistor and the pass transistor. | 2009-12-03 |