48th week of 2010 patent applcation highlights part 22 |
Patent application number | Title | Published |
20100301898 | FPGA HAVING LOW POWER, FAST CARRY CHAIN - FPGA carry chain that does not exhibit significant leakage current. In particular, the carry chain can be switched on/off when desired. In this manner, carry chains can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, a carry chain whose logic is separate from the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data from the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the input data without need to wait on results from the logic blocks. | 2010-12-02 |
20100301899 | CIRCUITS FOR SOFT LOGICAL FUNCTIONS - A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, the soft logic gates including one or more soft logic gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. | 2010-12-02 |
20100301900 | Pre-Charged High-Speed Level Shifters - An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor. | 2010-12-02 |
20100301901 | UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT - A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit. | 2010-12-02 |
20100301902 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 2010-12-02 |
20100301903 | BUILDING BLOCK FOR A SECURE CMOS LOGIC CELL LIBRARY - A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt. | 2010-12-02 |
20100301904 | NON-LINEAR INTERPOLATION CIRCUIT, INTERPOLATION CURRENT GENERATING CIRCUIT THEREOF AND METHOD FOR CONVERTING DIGITAL DATA INTO ANALOG DATA - A non-linear interpolation circuit includes current interpolation units and an I-V converter. The current interpolation units receive an operating voltage corresponding to digital image data and corresponding reference voltages to generate corresponding operating currents. When the operating voltage changes, at least one of the corresponding current interpolation units generate the corresponding operating current, and the operating currents with respect to the operating voltage are superimposed to form an interpolation current. The I-V converter converts the interpolation current into an interpolation voltage. An interpolation current generating circuit and a method for converting digital data into analog data are also disclosed herein. | 2010-12-02 |
20100301905 | Output circuit having pre-emphasis function - An output circuit includes a first differential pair of transistors driven by a first current source and differentially receiving input signals and a second differential pair of transistors driven by a second current source and differentially receiving first control signals (EMT, EMB). Output pairs of the first and second differential pairs are connected to the differential output terminals. A load resistor element pair is connected between a power supply and the differential output terminals. The output circuit further includes a third differential pair of transistors driven by a third current source and differentially receiving second control signals and a fourth differential pair of transistors driven by a fourth current source and differentially receiving third control signals. An output pair of the third differential pair of transistors is connected between one of the differential output terminals and the power supply. An output pair of the fourth differential pair of transistors is connected between the power supply and the other of the differential output terminals. | 2010-12-02 |
20100301906 | MULTIPHASE SIGNAL DIVIDER - A divider of an input multiphase signal by a given division factor so as to obtain an output multiphase signal, the divider having a circuit adapted to divide a first signal component of an input multiphase signal by an given division factor to obtain a first component of a output multiphase signal, and a plurality of N−1 devices including a first device adapted to sample the first component with a component of the input multiphase signal to obtain the component of the output multiphase signal corresponding to the one component of the input multiphase signal. Every other device of the plurality of N−1 devices is adapted to sample the component of the output multiphase signal of the preceding device with another component of the input multiphase signal, phase shifted by a further constant factor to obtain the corresponding component of the output multiphase signal. | 2010-12-02 |
20100301907 | SYSTEM AND METHOD FOR SECURE REAL TIME CLOCKS - A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC. A clock line transmits the signal having the first frequency and the signal having the second frequency from the frequency adjuster to the secure RTC, and has a first power consumption when transmitting the signal having the first frequency and a second power consumption when transmitting the signal having the second frequency, the first power consumption being greater than the second power consumption. | 2010-12-02 |
20100301908 | CIRCUIT FOR CONTROLLING PSON SIGNAL - A circuit includes an ATX power connector with a PSON pin, a time delay circuit, and a stabilizer circuit. The time delay circuit receives an input PSON# signal and then sends an output PSON# signal to the PSON pin of the power connector after a time delay has elapsed. The stabilizer circuit is coupled to the PSON pin of the power connector for stabilizing the output PSON# signal. | 2010-12-02 |
20100301909 | STARTUP CIRCUITRY AND CORRESPONDING METHOD FOR PROVIDING A STARTUP CORRECTION TO A MAIN CIRCUIT CONNECTED TO A STARTUP CIRCUITRY - A startup circuitry connected to a main circuit which has at least an output terminal connected to its feedback terminal by a feedback loop. The startup circuitry is connected to the main circuit in such a manner to break the feedback loop, by having a first circuit node connected to said output terminal of said main circuit and a second circuit node connected to its feedback terminal, said startup circuitry providing a correct output voltage value during the startup phase of said main circuit. | 2010-12-02 |
20100301910 | Frequency synthesizer - A frequency synthesizer comprises a VCO group; a phase comparator; and a loop filter. Each VCO includes a varactor and a capacitor bank including a plurality of weighted capacitance elements, and a plurality of switches turned ON and OFF based on a control signal. Also provided a temperature compensation including a varactor correction potential generation circuit, a correction potential generation circuit for parasitic capacitance of the capacitor bank, a variable gain amplifier in which weighting processing, based on a control signal of the capacitor bank, is performed on an output potential of the correction potential generation circuit, and an adder circuit that adds the output voltage of the correction potential generation circuit of the varactor and output voltage of the variable gain amplifier, and the varactor of the VCO is controlled by output (correction potential) of the adder circuit. | 2010-12-02 |
20100301911 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals. | 2010-12-02 |
20100301912 | DELAY LOCKED LOOP AND DELAY LOCKING METHOD HAVING BURST TRACKING SCHEME - A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock. | 2010-12-02 |
20100301913 | CMOS Clock Receiver with Feedback Loop Error Corrections - A system for correcting duty cycle errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signals. A duty cycle error detector has inputs for a pair of amplified clock signals and an output for a duty cycle error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the duty cycle error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the duty cycle error correction signal. Also, a system for correcting cross point errors in a clock receiver that includes a differential amplifier having inputs for a pair of differential clock signal. A cross point error detector has inputs for a pair of amplified clock signals and an output for a cross point error correction signal. A signal conditioner is also provided with the differential amplifier having an input for the cross point error correction signal. Furthermore, the signal conditioner adjusts the differential clock signals in response to the cross point error correction signal. | 2010-12-02 |
20100301914 | LATCH WITH CLOCKED DEVICES - A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device, and a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device, and a keeper circuit. The first output is operatively connected to the second input. The keeper circuit is operatively connected to the first output, and the keeper circuit is driven from the second output. The feed-back circuit includes a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output, and a fourth-inverting-stage with a fourth input and a fourth output. The fourth input is operatively connected to the third output. The fourth output is connected to the third input to form a storage node. | 2010-12-02 |
20100301915 | LATCH WITH SINGLE CLOCKED DEVICE - A D-latch circuit includes a feed forward circuit, a full keeper circuit, and an output buffer circuit. The feed forward circuit inputs a clock signal and a data signal. The feed forward circuit is connected to an input of the full keeper circuit. The feed forward circuit is connected to an output of the full keeper circuit and an input of the output buffer circuit. The output buffer circuit outputs an output signal. The D-latch consists of a single clocked device that switches with the clock signal. | 2010-12-02 |
20100301916 | CLOCK DISTRIBUTION CIRCUIT AND LAYOUT DESIGN METHOD USING SAME - A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit. | 2010-12-02 |
20100301917 | LEVEL SHIFT CIRCUIT - The invention provides a level shift circuit that prevents an offset when the supply voltage changes. A level shift circuit has a differential amplification circuit, a current generation circuit, a capacitor and a holding circuit. An input signal from the optical pickup is inputted to the non-inversion input terminal of the differential amplification circuit. First, by turning on a first switch, a feedback loop is formed by the differential amplification circuit, the current generation circuit and the capacitor to perform a level shift, and the voltage charged in the capacitor is held by the holding circuit. Then by turning off the first switch and turning on a second switch, the voltage held by the holding circuit is applied to the non-inversion input terminal of the differential amplification circuit to perform a level shift. | 2010-12-02 |
20100301918 | Level Shifter and Level Shifting Method Thereof - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage. | 2010-12-02 |
20100301919 | MIXER AND FREQUENCY CONVERTING APPARATUS - A mixer includes a magnetoresistive effect element, a magnetic field applying unit, and an impedance circuit. The magnetoresistive effect element includes a fixed magnetic layer, a free magnetic layer, and a nonmagnetic spacer layer disposed between the fixed magnetic layer and the free magnetic layer, is operable when a first high-frequency signal and a second high-frequency signal as a local signal are inputted, to multiply the first high-frequency signal and the second high-frequency signal according to a magnetoresistive effect to generate a multiplication signal. The magnetic field applying unit applies a magnetic field to the free magnetic layer. The impedance circuit has a higher impedance for the multiplication signal than an impedance for the first high-frequency signal and the second high-frequency signal and is disposed between an input transfer line, which transfers the first high-frequency signal and the second high-frequency signal, and the magnetoresistive effect element. | 2010-12-02 |
20100301920 | MIXER WITH HIGH LINEARITY - A mixer is provided. The transconductance stage receives an input signal through an input node and outputs an output signal through an output node. The transconductance stage includes a first transistor coupled between the output node and a first power node, having a first gate coupled to the input node, and operating in a saturation region, a second transistor coupled to the first power node, having a second gate coupled to the input node, and operating in a sub-threshold region, a first biasing circuit providing a first bias voltage, and a third transistor coupled between the output node and the second transistor, and having a third gate coupled to the first bias voltage. The switching quad is coupled to the output node and generates a translation current according to the output signal. The transimpedance amplifier transforms the translation current to a corresponding voltage. | 2010-12-02 |
20100301921 | SWITCHING CONTROL CIRCUIT - According to one embodiment, a switching control circuit includes an output circuit, a first circuit, and a second circuit. The output circuit includes an input terminal, an output terminal, and a switching element. The first circuit is connected to a control terminal of the switching element. The first circuit controls an input signal during a period when an output signal of the output circuit changes. The second circuit is connected to a control terminal of the first circuit. The second circuit generates a control signal for controlling a current flowing in the first circuit during the period when the output signal of the output circuit changes. | 2010-12-02 |
20100301922 | FIELD EFFECT TRANSISTOR WITH INTEGRATED GATE CONTROL AND RADIO FREQUENCY SWITCH - A field effect transistor (FET) including a monolithically integrated gate control circuit element can be included in, for example, a radio frequency switch circuit. For example, the FET can be included as a series and/or shunt FET of a radio frequency coplanar waveguide circuit. The widths of the series and shunt FETs of a switch circuit can be selected to provide a target isolation and/or a target insertion loss for a target operating frequency. | 2010-12-02 |
20100301923 | MONOLITHIC VOLTAGE REFERENCE DEVICE WITH INTERNAL, MULTI-TEMPERATURE DRIFT DATA AND RELATED TESTING PROCEDURES - A testing procedure may determine whether a monolithic voltage reference device meets a temperature drift specification. A first non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a first non-room temperature which is substantially different than room temperature. First non-room temperature information may be stored in a memory within the monolithic voltage reference device which is a function of the first non-room temperature output voltage. A second non-room temperature output voltage of the monolithic voltage reference device may be measured while the monolithic voltage reference device is at a second non-room temperature which is substantially different than the room temperature and the first non-room temperature. Second non-room temperature information may be stored in the memory without destroying the first non-room temperature information which is a function of the second non-room temperature output voltage. A determination may be made whether the monolithic voltage reference device meets the temperature drift specification based on a computation that is a function of both the first non-room temperature information and the second non-room temperature information. | 2010-12-02 |
20100301924 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD FOR THE SAME - The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit. | 2010-12-02 |
20100301925 | PRESSURE SENSITIVE SWITCH AND INPUT DEVICE USING PRESSURE SENSITIVE SWITCH - There is provided a pressure sensitive switch including: a cover; a slide portion that is stored in the cover and is slidable by being pressed in a horizontal direction; a pressing unit including a pressure portion that has an inner side face brought into contact with the slide portion and can be moved by being pressed by the slide potion; a sheet resistive body that has an upper face brought into contact with the pressing unit; and a conductive plate that is disposed on the lower side of the sheet resistive body with a predetermined gap arranged therebetween. The slide portion is slidable within a horizontal plane, and the pressing portion presses the sheet resistive body by sliding the slide portion, and a resistance value between the sheet resistive body and the conductive plate changes in accordance with a change in a slide operation force for sliding the slide portion. | 2010-12-02 |
20100301926 | Optimization of Circuits Having Repeatable Circuit Instances - Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions. | 2010-12-02 |
20100301927 | BOOSTER CIRCUIT - Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage. | 2010-12-02 |
20100301928 | LOW NOISE, LOW POWER SUBSAMPLING RECEIVER - Techniques for a receiver includes a low noise amplifier, a Q-enhanced bandpass filter on a chip, and an analog to digital converter (ADC) at a sub-sampling speed suitable for an intermediate frequency (IF) signal. In some embodiments, a temperature compensation circuit is included. The receiver has an effective noise level less than 7 dB. In some embodiments a 1-bit ADC is used. In some of these embodiments, one or more switches in the ADC are inverted to cancel charge injection. | 2010-12-02 |
20100301929 | Power Switching Devices Having Controllable Surge Current Capabilities - Semiconductor switching devices include a wide band-gap power transistor, a wide band-gap surge current transistor that coupled in parallel to the power transistor, and a wide hand-gap driver transistor that is configured to drive the surge current transistor. Substantially all of the on-state output current of the semiconductor switching device flows through the channel of the power transistor when a drain-source voltage of the power transistor is within a first voltage range, which range may correspond, for example, to the drain-source voltages expected during normal operation. In contrast, the semiconductor switching device is further configured so that in the on-state the output current flows through both the surge current transistor and the channel of the power transistor when the drain-source voltage of the power transistor is within a second, higher voltage range. | 2010-12-02 |
20100301930 | REDUCING DEVICE PARASITICS IN SWITCHED CIRCUITS - A system and method are provided to reduce the influence of parasitic capacitance at the drain and source of MOS transistors of a sampling circuit. In one embodiment, the bulk is left floating during a first phase and refreshed during a second phase. During the first phase, the effective parasitic contribution of the drain or source of a MOS transistor is lower due to the series combination of Cj and Cw capacitances. In another embodiment, a large resistance provides a path from a reference voltage to the bulk of a MOS transistor, thereby resulting in an effective parasitic capacitance of the series combination of Cj and Cw. Advantageously, the parasitic capacitance is reduced as well as its non-linear effect, the operating speed is improved, as well as the signal distortion and noise. | 2010-12-02 |
20100301931 | RECURSIVE DEMODULATION APPARATUS AND METHOD - A recursive demodulation apparatus is provided. Therecursive demodulation apparatus, including: a segment generation unit dividing data symbols with a residual frequency or phase error into a predetermined number of data symbols, and generating a plurality of segments, each of the plurality of segments including the predetermined number of data symbols; and a phase error correction unit sequentially correcting a phase error of each of the data symbols, included in the each of the plurality of segments, for each segment. | 2010-12-02 |
20100301932 | NON-INVERTING AMPLIFIER AND VOLTAGE SUPPLY CIRCUIT INCLUDING THE SAME - A non-inverting amplifier includes an operational amplifier, an input resistor, and a feedback resistor. The operational amplifier amplifies and outputs a difference between an input voltage and a voltage of a control node. The input resistor is connected between a reference voltage port and the control node. The feedback resistor is connected to an output port of the operational amplifier and the control node. The non-inverting amplifier supplies a control current to the control node for controlling an offset voltage of the output port. | 2010-12-02 |
20100301933 | OUTPUT NETWORKS IN COMBINATION WITH LINC TECHNIQUE - The present invention relates to balanced power amplifier network in combination with outphasing techniques such as Chireix. The object of the present invention is to provide a solution to the problem to combine balanced amplifiers like the current mode class D (CMCD) or class E/F with a LINC network. The main problem is that some power amplifiers have balanced output and the LINC network is single-ended so that a high power low loss transformer that works at several impedance levels is needed, which is hard to realize at cellular frequencies. | 2010-12-02 |
20100301934 | RF POWER AMPLIFIER CONTROLLER CIRCUIT WITH COMPENSATION FOR OUTPUT IMPEDANCE MISMATCH - A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude control loop may also compensate for impedance mismatch with the load by increasing the power delivered from the power amplifier to the load, or decrease the output power of the power amplifier upon detection of excessive power dissipation in the power amplifier. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal to reduce phase distortion generated by the power amplifier. | 2010-12-02 |
20100301935 | BIAS CIRCUIT, HIGH-POWER AMPLIFIER, AND PORTABLE INFORMATION TERMINAL - To provide a bias circuit for gain control that can reduce gain variation at low-power output, facilitate setting of output power, and is unlikely to be affected by variation in element values and variations among products. Use in an HPA having three bias circuits serially-connected is assumed. Current of the third bias circuit is varied with a square-law characteristic. The square-law characteristic is amplified by a buffer amplifier including a linear amplifier and a peripheral circuit thereof. Output current of the third bias circuit varies depending on a current drivability coefficient of the diode-connected FET branched from the connection point between a constant current source and the linear amplifier. The output current of the third bias circuit is controlled by providing a circuit that draws a certain amount of current from the current flowing in the FET. | 2010-12-02 |
20100301936 | DIFFERENTIAL LOW FREQUENCY NOISE SUPPRESSION TECHNIQUE FOR A COMMON MODE FEEDBACK CIRCUIT - Disclosed is a common mode feedback circuit for a differential amplifier that eliminates the effects of low frequency noise. A modulator is placed in a common mode feedback loop that modulates the feedback loop signal at a predetermined frequency to up-convert the low frequency noise. The predetermined frequency may be selected to be above the operating range of the downstream circuitry. In addition, a low pass filter can be used to eliminate the up-converted noise. | 2010-12-02 |
20100301937 | OUTPUT CIRCUIT - An output circuit that occupies a small area includes a control unit, X, Y, and Z axes amplification units, and first and second common circuits. The control unit outputs a temperature coefficient offset for correcting the temperature dependence of a sensor output. The first and second common circuits use the output from an acceleration sensor when performed amplification for each axis. In a reset phase, the charge accumulated in the first and second common circuits is released. In an amplification phase, the first and second common circuits and an operational amplifier uses the temperature coefficient offset voltage of each voltage to correct and amplify a signal from the acceleration sensor. In a hold phase, the accumulated charge is maintained in the same state to hold the output value of each axis. | 2010-12-02 |
20100301938 | OPERATIONAL AMPLIFICATION CIRCUIT - An operational amplification circuit includes a differential amplification circuit portion that amplifies a differential input, and an output circuit portion that outputs the amplified output using a signal amplified in the differential amplification circuit portion. The differential amplification circuit portion is provided with a pair of first transistors to which signals are differentially input, and second and third transistors which are connected to current paths of the pair of first transistors and which constitute current mirror circuits with respect to each other. The output circuit portion is provided with a fourth transistor, a gate of which is connected to a drain of the second transistor, and an amplified output is output from a drain of the fourth transistor. | 2010-12-02 |
20100301939 | High frequency receiver preamplifier - A folded cascode receiver amplifier with constant gain has inputs coupled to PMOS and NMOS differential transistors pairs with scaled geometries. The transconductance of both PMOS and NMOS transistors is the same whether the common mode input voltage is low or high. In a first version the transconductance of both PMOS and NMOS differential transistor pairs is reduced when the common mode input voltage is at mid-rail. Resistive means between current sources and the sources of the PMOS and NMOS transistor pairs force the current source transistors into the triode region of operation. A second version insures a constant voltage gain through control means which maintain a constant ratio of the transconductance of the output stage transistors versus the PMOS and NMOS differential transistor pairs when active. | 2010-12-02 |
20100301940 | NEGATIVE CAPACITANCE SYNTHESIS FOR USE WITH DIFFERENTIAL CIRCUITS - Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit. | 2010-12-02 |
20100301941 | Receiver - Disclosed herein is a receiver, including: an amplifier for amplifying a received signal; a strain compensator for having a function of compensating for a strain generated in an output signal from the amplifier in accordance with a stain compensation amount which is controlled based on a bias signal from the output signal from the amplifier; and a stain compensation amount controlling portion for generating the bias signal and outputting the bias signal to the strain compensator so that the strain compensation is carried out with a compensation amount corresponding to a strength of the received signal. | 2010-12-02 |
20100301942 | AMPLIFIER WITH BYPASS SWITCH - An amplifying circuit of a receiver for receiving a signal in a wireless network includes an amplifier and a switch. The amplifier includes an amplifying transistor having a gate connected to an input for receiving the signal and a source/drain connected to a voltage source through an inductance. The amplifier also includes a bypass transistor having a gate connected to a control signal for activating the bypass transistor in a bypass mode and a source/drain connected in parallel with the inductance. The switch is connected in parallel with the amplifier between the input and an output, and activates in the bypass mode, enabling the received signal to bypass the amplifier. In the bypass mode, a voltage at the source/drain of the amplifying transistor is lower when the bypass transistor is activated than when not activated, the lower source/drain RF voltage reducing unwanted harmonics from the amplifier. | 2010-12-02 |
20100301943 | High Voltage Amplification Using Low Breakdown Voltage Devices - Methods and apparatus for amplifying signals over a wide frequency range to generate high voltage outputs feature a pair of switching modules which are connected in series. Switching modules, e.g., field-effect transistors (FETs), operate based on the voltage difference between an amplified signal and a fixed DC signal at two of their terminals, thereby generating an output waveform that has peak-to-peak voltage higher than, e.g. twice, the breakdown voltage of the transistors within the amplifier. The DC signals applied at the switching modules may be varied using an AC signal to improve the risetime of the output waveform and achieve a faster operational speed of the amplifier. | 2010-12-02 |
20100301944 | POWER AMPLIFIER - A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device. | 2010-12-02 |
20100301945 | POWER AMPLIFIER INTEGRATED CIRCUIT WITH COMPENSATION MECHANISM FOR TEMPERATURE AND OUTPUT POWER - A power amplifier integrated circuit, which generates an RF output signal by amplifying an RF input signal, includes a thermal-sensing circuit, a feedback circuit, a logic judging circuit, an adjusting circuit, and an amplifying circuit. The thermal-sensing circuit generates a thermal sensing signal according to the operational temperature, and the feedback circuit generates a power compensation circuit according to power variations in the RF output signal. The logic judging circuit outputs a compensation signal according to the thermal sensing signal and the power compensation signal. The adjusting circuit adjusts the level of the RF input signal according to the compensation signal, thereby generating a corresponding 1st stage RF signal. The amplifying circuit can amplify the 1st stage RF signal, thereby generating the corresponding RF output signal. | 2010-12-02 |
20100301946 | Switchable Multiband LNA Design - A low noise amplifying (LNA) circuit comprising an amplifying section ( | 2010-12-02 |
20100301947 | RF POWER AMPLIFIER - The RF power amplifier includes first and second amplifiers Q | 2010-12-02 |
20100301948 | Low Noise Amplifier and Mixer - A low noise amplifier (LNA) system with controllable linearity and noise figure versus power consumption is provided. The system comprises two control inputs for tuning. One input controls an effective transistor width, and the other input controls bias current. Changes to the effective transistor width alter a gain that is applied to a signal, and changes to the bias current alter a power consumption of the system. For more stringent signal specifications, an impedance matched inductive degeneration variation of the LNA is provided. | 2010-12-02 |
20100301949 | INTERNAL POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units. | 2010-12-02 |
20100301950 | Clock regeneration apparatus and electric equipment - Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively. | 2010-12-02 |
20100301951 | CURRENT CONTROLLED RING OSCILLATOR AND METHOD FOR CONTROLLING THE SAME - A current controlled ring oscillator and a method for controlling the same are provided. The current controlled ring oscillator includes a charge pump (CP), a loop filter (LF), a voltage-current (V-I) converter, and an oscillation unit. The CP is used to provide a charging/discharging current. The LF is coupled to the CP, and is used to provide a control voltage. The V-I converter is coupled to the CP, and is used to convert the control voltage to a control current. The oscillation unit includes a plurality of current controlled delay cells serially connected to one another as a ring, and the oscillation unit is coupled to the V-I converter, and controlled by the control current to generate an oscillation signal. | 2010-12-02 |
20100301952 | Method For The Production Of High Amplitude RF Voltages With Control Of The Phase Angle Between Outputs - A method of producing high frequency high amplitude AC voltages with control of the phase angle between outputs from a plurality of generators having individual DC current controlled variable inductors which method comprises controlling the timing of the circuit to allow inputs at the same frequency to have their phase angle preserved. All the outputs are phase locked and synchronised to a common external timed signal and programmed to the same output frequency. | 2010-12-02 |
20100301953 | PHASE LOCK LOOP WITH A MULTIPHASE OSCILLATOR - A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal from the oscillator to a lower desired frequency, thereby increasing phase resolution. | 2010-12-02 |
20100301954 | PIEZOELECTRIC TRANSDUCER, PIEZOELECTRIC TRANSDUCER MANUFACTURING METHOD, OSCILLATOR, ELECTRONIC DEVICE, AND RADIO CLOCK - Provided are: a piezoelectric oscillation piece which has a pair of oscillation arms disposed in parallel with each other with base ends of the oscillation arms fixed to a base of the piezoelectric oscillation piece and with weight metal films formed at the tips of the oscillation arms; a base substrate on the upper surface of which the piezoelectric oscillation piece is mounted; a lid substrate joined with the base substrate such that the mounted piezoelectric oscillation piece can be accommodated in a cavity; and a control film disposed in the vicinity of the pair of the oscillation arms as viewed in the plan view and formed at least on either of the substrates in such a manner as to extend from the base end side to the tip side in the longitudinal direction of the oscillation arms for increasing the degree of vacuum inside the cavity by heating. The control film is locally deposited on the side surfaces of the oscillation arms in the vicinity of the control film by heating. | 2010-12-02 |
20100301955 | Frequency divider using an injection-locking-range enhancement technique - A locking range enhancement technique is described that steers away part of the DC current and reuses it to generate more injected AC current to the injection-locked resonator-based frequency dividers (ILFDs). The injection-enhanced ILFDs maintain the key features of ILFDs, which are high speed and low power consumption, without requiring any extra inductive component and thus extra chip area. | 2010-12-02 |
20100301956 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator includes a resonator section in which a plurality of types of variable capacitance elements having different structures and capacitance variation characteristics are connected in parallel and capacitance values of the plurality of types of variable capacitance elements are controlled simultaneously by a control voltage; and an amplifier section for maintaining oscillation produced by the resonator section. Varactor diodes and MOS varactors can be used as the variable capacitance elements. | 2010-12-02 |
20100301957 | RELAXATION OSCILLATOR USING SPINTRONIC DEVICE - Disclosed herein is a relaxation oscillator using a spintronic device. The relaxation oscillator includes a power source unit, a spintronic device, and a capacitor. The power source unit applies power. The spintronic device is driven by the power applied by the power source unit, and has a variable voltage value depending on the intensity of a magnetic field. The capacitor is connected in parallel with the spintronic device, and is discharged when it assumes a minimum-voltage value in the threshold voltage range of the spintronic device and charged when it assumes a maximum voltage value in the threshold voltage range. | 2010-12-02 |
20100301958 | Unit, oscillator having unit and electronic apparatus having oscillator - A unit comprising a quartz crystal resonator vibratable in a flexural mode and having a base portion including a length less than 0.5 mm, and first and second vibrational arms connected to the base portion, at least one groove being formed in each of two of opposite main surfaces of each of the first and second vibrational arms, and an electrode being disposed on a surface of the at least one groove formed in each of the two of the opposite main surfaces of each of the first and second vibrational arms so that the electrode disposed on the surface of the at least one groove formed in each of the two of the opposite main surfaces of the first vibrational arm has an electrical polarity opposite to an electrical polarity of the electrode disposed on the surface of the at least one groove formed in each of the two of the opposite main surfaces of the second vibrational arm. | 2010-12-02 |
20100301959 | PULSE WIDTH MODULATOR WITH TWO-WAY INTEGRATOR - A pulse width modulator (PWM) includes a driver and a two-way integrator. The driver is coupled to output a first and a subsequent period of a PWM signal. Both the first and the subsequent periods include the PWM signal changing between first and second states. The two-way integrator is coupled to integrate an input current and coupled to generate a duty ratio signal in response to integrating the input current. The driver determines a duty factor of both the first and the subsequent periods by setting the PWM signal to the second state in response to the duty ratio signal. The two-way integrator includes a capacitor that integrates the input current during the first period by charging the capacitor and integrates the input current during the subsequent period by discharging the capacitor. | 2010-12-02 |
20100301960 | Method and Arrangement for Generating a Frequency-Modulated Signal - In order to generate a broadband, frequency-modulated output signal, of which the carrier frequency is adjustable within a wide frequency range, a frequency-modulated signal is generated on an arbitrary, fixed carrier frequency, which is then converted into IQ signals, and the IQ signals generated in this manner are combined with the desired carrier frequency by IQ modulation to form the frequency-modulated output signal. By preference, the generated IQ signals are low-pass filtered before the IQ modulation. | 2010-12-02 |
20100301961 | PHASE LOCKED LOOP - A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronised with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator. | 2010-12-02 |
20100301962 | COMPOSITE BALUN - A composite balun includes a plurality of baluns, at least one capacitor, a ground terminal, and a DC voltage supply terminal. The plurality of baluns and the capacitor are built into a single chip. Each of the baluns includes first to fourth connection lines, a first balanced terminal, a second balanced terminal, and an unbalanced terminal. The first connection line is connected at one end to the unbalanced terminal. The second connection line is connected at one end to the other end of the first connection line. The third connection line is electromagnetically coupled to the first connection line and connected at one end to the first balanced terminal and at the other end to the DC voltage supply terminal. The fourth connection line is electromagnetically coupled to the second connection line and connected at one end to the second balanced terminal and at the other end to the DC voltage supply terminal. The capacitor is connected at one end to the DC voltage supply terminal and led at the other end to said ground terminal. | 2010-12-02 |
20100301963 | BALUN WITH INTERMEDIATE CONDUCTOR - A balun comprising first and second transmission lines having a shared intermediate conductor. The first transmission line may include first and second conductors. The first conductor may have a first end for conducting an unbalanced signal relative to a circuit ground and a second end for conducting a balanced signal. The second conductor may have first and second ends proximate the respective first and second ends of the first conductor. The first end of the second conductor is open circuited. The second transmission line may include the second conductor and a third conductor having a first end connected to circuit ground and a second end for conducting the balanced signal. A resistor may connect the second end of the second conductor to circuit ground. | 2010-12-02 |
20100301964 | HIGH-FREQUENCY MODULE - A high-frequency module includes at least first and second signal circuits that are each connected between a common antenna port and at least first and second signal ports. The first signal circuit includes a first inductor connected in series between the antenna port and the first signal port, a first capacitor connected in series between the first inductor and the first signal port, and a second inductor connected in shunt between the first capacitor and the first signal port. Series resonance is produced between the first inductor, the first capacitor, and the second inductor at a frequency within the frequency band of a target signal of the second signal circuit. | 2010-12-02 |
20100301965 | Waveguide System with Differential Waveguide - A waveguide system comprises a differential waveguide with at least one first and one second signal conductor, which are coupled to one another within the waveguide, and a divider network with front network elements disposed at a front end of the waveguide in the signal-flow direction and with rear network elements disposed at a rear end of the waveguide in the signal-flow direction. The front network elements comprise a first parallel element, which extends in the direction from the first signal conductor to the earth conductor, and a second parallel element, which extends in the direction from the second signal conductor to the earth conductor. Alternatively, the parallel element can also be disposed between the signal conductors. | 2010-12-02 |
20100301966 | MULTILAYER COMMON MODE FILTER - A multilayer common mode filter is provided, which can inhibit cracks from occurring, while securing the magnetic coupling between coil conductors. | 2010-12-02 |
20100301967 | MEMS Device - System and method for a microelectromechanical system (MEMS) is disclosed. A preferred embodiment comprises a first anchor region, a vibrating MEMS structure fixed to the first anchor region, a first electrode adjacent the vibrating MEMS structure, a second electrode adjacent the vibrating MEMS structure wherein the vibrating MEMS structure is arranged between the first and the second electrode. | 2010-12-02 |
20100301968 | POWER AMPLIFIER FILTER FOR RADIO-FREQUENCY SIGNALS - A power amplifier filter for radio-frequency signals having an outphasing type architecture comprising a first stage ( | 2010-12-02 |
20100301969 | ACOUSTIC WAVE DEVICE - A longitudinally-coupled resonator-type acoustic wave device includes first to third IDT electrodes disposed on a piezoelectric material and first and second reflectors disposed in acoustic wave propagation directions. Each of any two IDT electrodes adjacent to each other in the acoustic wave propagation directions, of the first to third IDT electrodes, has a narrower-pitch electrode finger portion at an edge thereof adjacent to the other IDT electrode. Most portions of the first to third IDT electrodes are apodized, and the narrower-pitch electrode finger portions and the electrode finger portions adjacent thereto are normally shaped. | 2010-12-02 |
20100301970 | SELF-MATCHING BAND-PASS FILTER AND RELATED FREQUENCY DOWN CONVERTER - A band-pass filter includes an input port, an output port, and a plurality of resonators. The input port is utilized for receiving a radio frequency signal. The output port is utilized for outputting a filtered signal. The plurality of resonators are placed between the input port and the output port, and are utilized for band-pass filtering the radio frequency signal for generating the filtered signal, wherein the plurality of resonators comprise at least two different trace widths for matching the output impedance of the band-pass filter with the input impedance of a rear-stage circuit coupled to the output port. | 2010-12-02 |
20100301971 | TUNABLE METAMATERIALS - A metamaterial comprises a support medium, such as a planar dielectric substrate and a plurality of resonant circuits supported thereby. At least one resonant circuit is a tunable resonant circuit including a conducting pattern and a tunable material, so that an electromagnetic parameter (such as resonance frequency) may be adjusted using an electrical control signal applied to the tunable material. | 2010-12-02 |
20100301972 | SELF-TERMINATING COAXIAL CABLE PORT - A circuit for automatically terminating a user port in a coaxial cable system includes a signal path extending from a user-side port toward a supplier-side port, the signal path including a conductor and a ground. The user-side port is adapted to connect to a user device. The circuit further includes a passive signal sampler coupled to the signal path, and a comparator element in communication with the passive signal sampler. The comparator is adapted to compare a line signal on the signal path to a reference signal and generate an output. A switch disposed in the signal path has a first state for terminating the line signal and a second state for passing the line signal. The first state and the second state are responsive to the output generated from the comparator. | 2010-12-02 |
20100301973 | Systems, Devices, and/or Methods Regarding Waveguides - Certain exemplary embodiments can provide a rectangular waveguide and backshort adapted for using/studying millimeter and/or submillimeter waves. Exemplary sliding shorts can exhibit relatively low loss, relatively smooth phase variation with frequency and movement, and/or relatively good repeatability. Certain exemplary embodiments can resist transmission of power by reflecting substantially all power from an incident signal. | 2010-12-02 |
20100301974 | ELECTROMAGNETIC RELAY - An electromagnetic relay comprises a coil generating magnetic force when power is distributed, a contact point part opened and closed by the magnetic force, and a fuse functional part having a conductor wired electrically in series with the contact point part and disconnected when predetermined heat quantity is received, and the fuse functional part is disposed at a position which receives arc heat generated in the contact point part when switching the contact point part from conduction state to cut-off state. Thereby, a small electromagnetic relay which enables interruption of current in all current value range can be provided. | 2010-12-02 |
20100301975 | DEVICE AND SYSTEM FOR BYPASSING A POWER CELL OF A POWER SUPPLY - A bypass device for bypassing a power cell of a multi-cell device. The bypass device includes a stationary portion of a first set of contacts connected to at least first and second output terminals of a power cell, a magnetically latching solenoid that, when energized, moves a moving portion of the first set of contacts from a first position to a second position or from the second position to the first position, and at least one added insulating material positioned between the solenoid and the first set of contacts, and configured to allow a voltage between the magnetically latching solenoid and the first and second output terminals of the power cell to exceed a voltage between said output terminals. | 2010-12-02 |
20100301976 | CIRCUIT INTERRUPTER INCLUDING A MOLDED CASE MADE OF LIQUID CRYSTAL POLYMER - A circuit interrupter includes a housing having a molded case made of liquid crystal polymer. Separable contacts are disposed within the housing. An operating mechanism is disposed within the housing and is structured to open and close the separable contacts. A trip mechanism is disposed within the housing and is structured to cooperate with the operating mechanism to trip open the separable contacts. The trip mechanism includes an electronic trip circuit and a rigid, conductive base providing a ground to the electronic trip circuit. The rigid, conductive base is insert molded to a portion of the molded case. | 2010-12-02 |
20100301977 | Superconducting Magnet Device - A superconducting magnet device includes a main coil that generates a static magnetic field in an imaging space and a disturbance magnetic field compensation coil that suppresses influences of a variable magnetic field flowing inside from outside in the imaging space. The main coil is divided to at least two diode circuits. The disturbance magnetic field compensation coil has at least one coil formed of minus turns so that mutual inductances with the respective diode circuits in the main coil are made minimum. | 2010-12-02 |
20100301978 | LINEAR ACTUATOR - A linear actuator includes a coil that generates a magnetic force upon energization thereof, a yoke covering an outer peripheral surface of the coil, a magnetic attraction core that generates an attractive magnetic force in an axial direction with the magnetic force generated by the coil, a plunger that is magnetically attracted to the magnetic attraction core, and a magnetic conduct core that conducts magnetic flux received from the yoke to the plunger in a radial direction. An outer peripheral surface of the plunger is configured to slide along an inner peripheral surface of the magnetic conduct core. The plunger has a distribution-adjusting recess, which is recessed in an outer peripheral surface of a portion of the plunger made of a magnetic material to adjust magnetic flux distribution of the magnetic flux along the plunger in the axial direction with respect to the magnetic conduct core. | 2010-12-02 |
20100301979 | METHOD AND SYSTEM FOR TRANSPORTATION USING A MAGNETIC BEARING STRUCTURE - A method and system for transportation using a magnetic bearing structure is disclosed. In one aspect, an apparatus for carrying a load comprises a source of magnetic flux and a controller configured to control the position of the source of magnetic flux relative to a magnetizable structure. The source of magnetic flux comprises a first upper portion and a first lower portion of opposite polarities. The first portions are spaced apart horizontally from a first side of the magnetizable structure. The source of magnetic flux further comprises a second upper portion and a second lower portion of opposite polarities. The second portions are spaced apart horizontally from a second side of the magnetizable structure. The second side is opposite the first side. The first and second upper portions are magnetically attracted to an upper portion of the magnetizable structure and the first and second lower portions are magnetically attracted to a lower portion of the magnetizable structure. | 2010-12-02 |
20100301980 | Current Transformer, Protection Device Including Such transformer and Related Circuit Breaker - A current transformer adapted for use in an electrical circuit. The current transformer includes a toroidal core and at least one electrical conductor having a portion passing within the toroidal core. The current transformer includes a cooling device having a body made of thermal conducting material and configured so that it has a first portion connected to the electrical conductor at a position upstream from the toroidal core and suitable for absorbing heat from the electrical conductor, and a second portion, spaced apart from the first portion, which is connected to the electrical conductor at a position downstream from the toroidal core and is suitable for transmitting heat to the electrical conductor. The thermal conducting body comprises at least one portion made of an electrically insulating material capable of preventing the current flow through the cooling device itself. | 2010-12-02 |
20100301981 | COIL ASSEMBLY AND MAGNETIC ELEMENT WITH SHIELDING FUNCTION - A coil assembly includes at least one insulated wire and an electromagnetic interference shielding layer. The insulated wire is wound into a winding coil part. The winding coil part includes a first wire-outlet segment, a second wire-outlet segment and a central through-hole. The electromagnetic interference shielding layer is formed on the winding coil part for shielding the insulated wire. The electromagnetic interference shielding layer has lateral projection profile on the winding coil part. The electromagnetic interference shielding layer has a radial gap such that the electromagnetic interference shielding layer is a non-conducting loop. | 2010-12-02 |
20100301982 | HIGH FREQUENCY TRANSFORMER AND MULTI-OUTPUT CONSTANT CURRENT SOURCE WITH HIGH FREQUENCY TRANSFORMER - In various embodiments, a high frequency transformer is provided. The high frequency transformer may include a magnetic core; a primary winding; and a plurality of secondary windings; wherein the plurality of secondary windings and the primary winding are arranged separately, and each secondary winding constitutes a parasite current transformer with the primary winding. | 2010-12-02 |
20100301983 | SURFACE-MOUNT AIR-CORE COIL - A surface-mount air-core coil is provided in which a conductive wire covered with an insulation coating is wound into a spiral shape to form a cylindrically wound coil portion, conductive wires which are not covered with the insulation coating extend from both ends of the wound coil portion to form a pair of terminal portions, and the terminal portions are soldered onto electrode lands of a circuit board. A lower side of the wound coil portion which faces the circuit board is curved, an upper side thereof is formed in a flat shape, and the curved part is mounted on the circuit board. | 2010-12-02 |
20100301984 | ELECTROMAGNETIC COIL MEANS - The present invention discloses an electromagnetic coil means, comprising a terminal part and pins passing through the terminal part, wherein the pins are divided into a first group of pins connected with an upper coil stator and a second group of pins connected with a lower coil stator which are spaced apart from each other; the first group of pins comprises first outer sections with first head portions and first inner sections with first root portions; the second group of pins comprising second outer sections with second head portion and second inner sections with second root portions; the first and second head portions extend out from a pin leading-out surface of the terminal part, characterized in that, at least one group of the first and second groups of pins are bent, and a distance between adjacent said first and second head portions is larger than that between adjacent said first and second root portions. By this electromagnetic coil means, the distance of solder joints between adjacent head portions of pins is increased, thus the insulation performance between the solder joints is improved. | 2010-12-02 |
20100301985 | HIGH-VOLTAGE POWER GENERATION SYSTEM AND PACKAGE - A power generation system comprises a power source, a transformer module for converting a low voltage from the power source into a higher voltage, and a voltage-multiplier module for amplifying higher voltage from the transformer module. The transformer module comprises a number N of transformer units. Each transformer unit comprises at least one transformer, and each transformer comprises a magnetic core, a primary winding, and a secondary winding. Primary windings of the transformers in the transformer module are electrically coupled in parallel to the power source, secondary windings of the transformers of each transformer unit comprise a pair of output terminal, and N is equal to or greater than two. The voltage-multiplier module comprises the number N of multipliers. Each multiplier module comprises a positive and a negative input terminal, and a positive and a negative output terminal. Positive and negative terminals of each multiplier are electrically coupled to the positive and negative output terminals of a corresponding transformer unit, and positive and negative output terminals of the multipliers are connected in series. | 2010-12-02 |
20100301986 | REACTOR APPARATUS FOR A RAILWAY VEHICLE - A reactor apparatus for a railway vehicle includes a coil assembly, a side cover, through bolts inserted into the coil assembly, cover supporting members, a pair of frames, and ribs that reinforce the pair of frames. A support/fixation section of each frame is fixed to an under surface of a vehicle pedestal. The pair of the frames are disposed on both sides of the coil assembly, and support the through bolts and the cover supporting member. For each rib, leg members that extend from corresponding reinforcing body are penetrated into and welded to the corresponding frame. For each cover supporting member, a leg member that extends from corresponding cover supporting body is penetrated into and welded to the corresponding frame. | 2010-12-02 |
20100301987 | MILLIMETER WAVE TRANSFORMER WITH A HIGH TRANSFORMATION FACTOR AND A LOW INSERTION LOSS - A millimeter wave transformer including, at its primary, a turn formed of a conductive track made in at least one first metallization level, and, at its secondary, a winding in front of the primary turn, including at least one turn formed of a conductive track made in at least one second metallization level isolated from the at least one first level, the track width of the primary turn being at least equal to the total width of the secondary winding. | 2010-12-02 |
20100301988 | Breakdown Layer via Lateral Diffusion - An electronic device including a breakdown layer having variable thickness. The device includes a variable resistance material positioned between two electrodes. A breakdown layer is interposed between the variable resistance material and one of the electrodes. The breakdown layer has a non-uniform thickness, which serves to bias the breakdown event toward the thinner portions of the breakdown layer. As a result, the placement, size, and number of ruptures in the breakdown layer are more consistent over a series or array of devices. The variable resistance material may be a phase-change material. The variable-thickness breakdown layer may be formed through a diffusion process by introducing a gas containing a resistivity-enhancing species to the environment of segmented variable resistance devices during fabrication. The resistivity-enhancing element penetrates the outer perimeter of the variable resistance material and diffuses toward the interior of the device. The resistivity-enhancing species increases the resistance of the interface between the variable resistance material and the electrode by interacting with the variable resistance material and/or electrode to form a resistive interfacial material. Based on the diffusional nature of the process, the concentration of the resistivity-enhancing species decreases toward the center of the device and as a result, the breakdown layer is thinner toward the center of the device. | 2010-12-02 |
20100301989 | Sputter deposition of cermet resistor films with low temperature coefficient of resistance - A solution for producing nanoscale thickness resistor films with sheet resistances above 1000Ω/□ (ohm per square) and low temperature coefficients of resistance (TCR) from −50 ppm/° C. to near zero is disclosed. In a preferred embodiment, a silicon-chromium based compound material (cermet) is sputter deposited onto a substrate at elevated temperature with applied rf substrate bias. The substrate is then exposed to a process including exposure to a first in-situ anneal under vacuum, followed by exposure to air, and followed then by exposure to a second anneal under vacuum. This approach results in films that have thermally stable resistance properties and desirable TCR characteristics. | 2010-12-02 |
20100301990 | APPARTUS AND METHOD FOR AFFECTING CHANGE IN A TARGET USING AN INTEGRATED LIGHTING SYSTEM - Methods and systems for affecting change in a target using an integrated lighting system are provided. A light source having one or more parameters and being configured to provide lighting is operably connectable to a control system. A sensor configured to detect a lighting condition from a target and/or target environment is also operably connectable to the control system. The control system may adjust the one or more parameters of the light source assembly when the detected lighting condition from the target environment is different from a desired lighting condition. The light source, sensor, and control system may be provided in connection with an enclosed environment. | 2010-12-02 |
20100301991 | THEFT DETECTION AND PREVENTION IN A POWER GENERATION SYSTEM - A system for generation of electrical power including an inverter connected to a photovoltaic source including a theft prevention and detection feature. A first memory is permanently attached to the photovoltaic source. The first memory is configured to store a first code. A second memory is attached to the inverter. The second memory configured to store a second code. During manufacture or installation of the system, the first code is stored in the first memory attached to the photovoltaic source. The second code based on the first code is stored in the second memory. Prior to operation of the inverter, the first code is compared to the second code and based on the comparison; the generation of the electrical power is enabled or disabled. | 2010-12-02 |
20100301992 | Channel Discovery and Disconnection in Networks Over White Spaces and Other Portions of the Spectrum - Functionality is described for discovering a channel within an environment in which non-privileged entities have subordinate access rights to spectrum compared to privileged entities. The functionality operates by investigating spectrum units within the spectrum for the presence of the channel. In one case, the functionality operates by investigating the spectrum units in linear succession; in another case, the functionality advances in a staggered fashion over the available spectrum. Functionality is also described for handling disconnection by a node from a channel. The functionality allows the node to convey its disconnection status to other communication participants. In one case, various aspects of the functionality are implemented by performing analysis in the time domain. | 2010-12-02 |
20100301993 | PATTERN BASED SECURITY AUTHORIZATION - A method, system and computer-usable medium for authorizing access to a secure location are disclosed. Data indicative of security-related activities (e.g., badging in and/or out of a secure building) can be compiled and then mined to deduce a particular pattern of security-related activities. Access to the secure location can be then authorized, based on the particular pattern of security-related activities. | 2010-12-02 |
20100301994 | ANTI-TAMPER DEVICE, METHOD OF CONTROLLING AN ANTI-TAMPER DEVICE, AND A FISCAL PRINTER USING THE SAME - Anti-tamper devices, control methods for electronic appliances having an anti-tamper device, and fiscal printers having an anti-tamper device are disclosed. A control method for an electronic appliance having an anti-tamper device includes detecting a removal sequence of a plurality of fasteners from the electronic appliance, comparing the specified removal sequence with the detected removal sequence, and, when the compared sequences differ, limiting one or more specific operations of the electronic appliance or causing the electronic appliance to execute one or more specific operations. A corresponding plurality of sensors can be used to monitor the installation states of the fasteners. The specified removal sequence can be changed based on time kept by a timer. The detected removal sequence and the specified removal sequence can be stored in memory and compared by a control unit. | 2010-12-02 |
20100301995 | FLUID HUMAN-MACHINE INTERFACE - A method of operating a communication device to interface with a machine system comprises projecting a human-machine interface (HMI) system for the machine system on a surface, wherein the HMI system comprises a plurality of commands associated with the machine system, detecting an input from a user, wherein the input comprises a fluid motion in air performed by the user corresponding to a selection of a command of the plurality of commands associated with the machine system, and transferring the selected command for delivery to the machine system. | 2010-12-02 |
20100301996 | Nightstand With a Security Safety Drawer - A nightstand with a security safety drawer, that provides for the safe storage of a handgun or firearm while providing convenient and quick access to the handgun or firearm. The nightstand has a structure with an exterior side, a plurality of drawers, a top security drawer for the nightstand to safely and conveniently store the handgun or firearm and a biometric finger scanner to verify and allow the user access to the security top drawer. The nightstand also has a locking device for locking the security top drawer and preventing access to an unauthorized user and a means for providing a primary electrical power source with a battery back-up, to provide a secondary electrical power source to the biometric finger scanner. There is also a portable version of the security safety drawer that can be used in other venues with other nightstands. | 2010-12-02 |
20100301997 | METHODS FOR AUTHENTICATING THE IDENTITY OF INDIVIDUALS RESPONSIBLE FOR MAINTAINING ELECTRICALLY OPERATED FOLDING PARTITIONS - A method for maintaining the folding operable wall comprising: (a) recording a template of a biological trait of an authorized individual into a biometric verification system; (b) saving the template in a database; (c) capturing a new record; (d) comparing the new record against the template; (e) confirming the identity of the authorized individual if the new record is substantially similar to the saved template; (f) preventing the electrical operation circuit from functioning if the biometric verification system fails to authenticate the identity of the authorized individual; and (g) restarting the electrical operation circuit after the identity of the authorized individual is verified. | 2010-12-02 |