48th week of 2011 patent applcation highlights part 47 |
Patent application number | Title | Published |
20110294242 | FLIP-CHIP GAN LED FABRICATION METHOD - A flip-chip LED fabrication method includes the steps of (a) providing a GaN epitaxial wafer, (b) forming a first groove in the GaN epitaxial layer, (c) forming a second groove in the GaN epitaxial layer to expose a part of the N-type GaN ohmic contact layer of the GaN epitaxial layer, (d) forming a translucent conducting layer on the epitaxial layer, (e) forming a P-type electrode pad and an N-type electrode pad on the translucent conducting layer, (f) forming a first isolation protection layer on the P-type electrode pad, the N-type electrode pad, the first groove and the second groove, (g) forming a metallic reflection layer on the first isolation protection layer, (h) forming a second isolation protection layer on the first isolation protection layer and the metallic reflection layer, (i) forming a third groove to expose one lateral side of the N-type electrode pad, (j) separating the processed GaN epitaxial wafer into individual GaN LED chips, and (k) bonding at least one individual GaN LED chip thus obtained to a thermal substrate with a conducting material. | 2011-12-01 |
20110294243 | PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN USING THE SAME - A photoresist composition suitable for forming a high-resolution pattern, and a method of forming a photoresist pattern using the same. The photoresist composition includes about 10 to about 45 parts by weight of an alkali soluble binder resin including a hydroxyl group, about 0.1 to about 5 parts by weight of a photo-acid generator, about 1 to about 5 parts by weight of a cross-linker that cross-links the alkali-soluble binder resin including the hydroxyl group, about 0.3 to about 3 parts by weight of a quinone diazide compound, and a remainder of a solvent. | 2011-12-01 |
20110294244 | METHOD FOR MANUFACTURING DISPLAY DEVICE - Provided is a method of manufacturing a display device, including: forming a polymer layer which includes an organic material on a principal surface side of a support substrate; forming one of a semiconductor circuit and a display circuit on the polymer layer; irradiating the polymer layer from the support substrate side with light having a wavelength that is absorbed in the polymer layer, to thereby separate the polymer layer from the support substrate; one of thinning and removing the polymer layer; and adhering a first substrate to one of a surface of the polymer layer and a face where the polymer layer has been provided. | 2011-12-01 |
20110294245 | ADAPTATION OF THE LATTICE PARAMETER OF A LAYER OF STRAINED MATERIAL - The invention relates to a method of adapting the lattice parameter of a seed layer of a strained material, comprising the following successive steps: a) a structure is provided that has a seed layer of strained material, of lattice parameter A | 2011-12-01 |
20110294246 | SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES - An apparatus includes a semiconductor layer ( | 2011-12-01 |
20110294247 | SOLID-STATE IMAGING ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor element comprises: a semiconductor substrate; and an amorphous metal oxide film as a first film deposited on the semiconductor substrate. By providing the amorphous metal oxide film as the first film, a recess with a large aspect ratio can be filled. As a result, a void/crack-free film of excellent quality can be formed. | 2011-12-01 |
20110294248 | METHOD FOR HEATING A SUBSTRATE OF SOLAR CELL - Disclosed is a method for heating a substrate of a solar cell. The method includes: providing a single or poly crystalline substrate; heating the substrate at atmosphere by a non-contact heater; and forming a thin film, which includes amorphous silicon or silicon alloy, on the substrate. | 2011-12-01 |
20110294249 | METHOD FOR CLEANING A SUBSTRATE OF SOLAR CELL - Disclosed is a method for cleaning the substrate of a solar cell. The method includes: providing a single or poly crystalline substrate; performing a wet etching process such that the surface of the substrate is textured; performing an atmospheric pressure plasma cleaning process on the textured substrate; and forming p-n junction. | 2011-12-01 |
20110294250 | IMAGE SENSOR ELEMENT FOR BACKSIDE-ILLUMINATED SENSOR - Provided is a method of forming and/or using a backside-illuminated sensor including a semiconductor substrate having a front surface and a back surface. A transfer transistor and a photodetector are formed on the front surface. The gate of the transfer transistor includes an optically reflective layer. The gate of the transfer transistor, including the optically reflective layer, overlies the photodetector. Radiation incident the back surface and tratversing the photodetector may be reflected by the optically reflective layer. The reflected radiation may be sensed by the photodetector. | 2011-12-01 |
20110294251 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing an image sensor having a plurality of pixels, each pixel having a photoelectric converter including an accumulation region, and a transfer gate, the accumulation region extending under a corresponding transfer gate, the plurality of pixels including a plurality of pixel groups, each pixel group including N adjacent pixels, and the channels of the N adjacent pixels, in each pixel group, being configured to transfer the charges of the N adjacent pixels away from each other, the method comprising a step of forming a resist pattern having one opening corresponding to each pixel group, and a step of forming a charge accumulation region for each of the N adjacent pixels by implanting ions into a substrate through the one opening of the resist pattern along N ion implantation directions so as to implant the ions under the transfer gate of each of the N adjacent pixels. | 2011-12-01 |
20110294252 | LATERAL COLLECTION ARCHITECTURE FOR SLS DETECTORS - Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections. | 2011-12-01 |
20110294253 | POLYDIODE STRUCTURE FOR PHOTO DIODE - An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal. | 2011-12-01 |
20110294254 | LOW COST SOLAR CELLS FORMED USING A CHALCOGENIZATION RATE MODIFIER - Methods and devices are provided for forming an absorber layer. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. | 2011-12-01 |
20110294255 | METHOD FOR FORMING SILICON TRENCH - A method for forming a silicon trench, comprises the steps of: defining an etching area at a silicon substrate; forming metal catalysts at the surface of the etching area; immersing the silicon substrate in a first etching solution thereby forming anisotropic silicon nanostructures in the etching area; immersing the silicon substrate in a second etching solution thereby resulting in the silicon nanostructures being side-etched and detached from the silicon substrate, thus forming the silicon trench. | 2011-12-01 |
20110294256 | FILM-FORMING METHOD FOR FORMING PASSIVATION FILM AND MANUFACTURING METHOD FOR SOLAR CELL ELEMENT - The challenge for the present invention is to provide a film-forming method and for forming a passivation film which can sufficiently inhibit the loss of carriers due to their recombination; and a method for manufacturing a solar cell element with the use of the method or the device. The film-forming device comprises a mounting portion | 2011-12-01 |
20110294257 | METHODS OF PROVIDING SEMICONDUCTOR LAYERS FROM AMIC ACID SALTS - A semiconductor layer and device can be provided using a method including thermally converting an aromatic, non-polymeric amic acid salt to a corresponding arylene diimide. The semiconducting thin films can be used in various articles including thin-film transistor devices that can be incorporated into a variety of electronic devices. In this manner, the arylene diimide need not be coated but is generated in situ from a solvent-soluble, easily coated aromatic, non-polymeric amic acid salt at relatively lower temperature because the cation portion of the salt acts as an internal catalyst. | 2011-12-01 |
20110294258 | METHOD AND APPARATUS FOR TRENCH AND VIA PROFILE MODIFICATION - Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. Particularly, embodiments of the present invention relates to methods and apparatus for profile modification prior to filling a structure, such as a trench or a via. One embodiment of the present invention comprises forming a sacrifice layer to pinch off a top opening of a structure by exposing the structure to an etchant. In one embodiment, the etchant is configured to remove the first material by reacting with the first material and generating a by-product, which forms the sacrifice layer. | 2011-12-01 |
20110294259 | NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND NONVOLATILE SEMICONDUCTOR APPARATUS USING THE NONVOLATILE MEMORY ELEMENT - A nonvolatile memory element comprises a first electrode layer ( | 2011-12-01 |
20110294260 | Semiconductor package and method of forming the same - Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip. | 2011-12-01 |
20110294261 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode. | 2011-12-01 |
20110294262 | SEMICONDUCTOR PACKAGE PROCESS WITH IMPROVED DIE ATTACH METHOD FOR ULTRATHIN CHIPS - A semiconductor packaging process with improved die attach method for ultrathin chips package comprises the steps of providing a semiconductor wafer having a wafer frontside and a wafer backside with a plurality of integrated circuit chips (IC chips) formed on the wafer frontside; adhering a supporting substrate onto the wafer frontside through a bonding layer to form a wafer combo; grinding the wafer backside with the supporting substrate and the wafer bonded together; dicing the wafer combo into a plurality of die combos each comprising a substrate piece stacked on top of an IC chip bonded by a bonding layer piece; attaching a die combo onto a die pad of a lead frame with a bottom of the IC chip connected to the lead frame thereof; and removing the substrate piece with the bonding layer piece from the top surface of the IC chip. | 2011-12-01 |
20110294263 | Pattern verification method, program thereof, and manufacturing method of semiconductor device - A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern. | 2011-12-01 |
20110294264 | HEAT SPREADER AS MECHANICAL REINFORCEMENT FOR ULTRA-THIN DIE - A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die. | 2011-12-01 |
20110294265 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material. | 2011-12-01 |
20110294266 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing, the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps. | 2011-12-01 |
20110294267 | METHOD OF FABRICATING THIN FILM TRANSISTOR - A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer on the entire surface of the substrate having the gate electrode, a first contact hole and a second contact hole, and source and drain electrodes on the interlayer insulating layer, insulated from the gate electrode, and having a portion connected with the semiconductor layer through the first contact hole. An organic light emitting diode display may include the thin film transistor along with a passivation layer on the entire surface of the substrate, and a first electrode, an organic layer, and a second electrode, which are on the passivation layer and electrically connected with the source and drain electrodes. | 2011-12-01 |
20110294268 | Thin Film Transistors and Methods of Manufacturing Thin Film Transistors - A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency. | 2011-12-01 |
20110294269 | Transistor With Embedded Strain-Inducing Material Formed in Diamond-Shaped Cavities Based on a Pre-Amorphization - When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved. | 2011-12-01 |
20110294270 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Extension regions | 2011-12-01 |
20110294271 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first pMISFET region having an Si channel, a second pMISFET region having an Si channel and an nMISFET region having an Si channel. First SiGe layers which apply first compression strain to the Si channel are embedded and formed in the first pMISFET region to sandwich the Si channel thereof and second SiGe layers which apply second compression strain different from the first compression strain to the Si channel are embedded and formed in the second pMISFET region to sandwich the Si channel thereof. | 2011-12-01 |
20110294272 | SEMICONDUCTOR DEVICE PRODUCTION METHOD - This semiconductor device includes a first device and a second device provided on a semiconductor substrate and having different breakdown voltages. More specifically, the semiconductor device includes a semiconductor substrate, a first region defined on the semiconductor substrate and having a first device formation region isolated by a device isolation portion formed by filling an insulator in a trench formed in the semiconductor substrate, a first device provided in the first device formation region, a second region defined on the semiconductor substrate separately from the first region and having a second device formation region, and a second device provided in the second device formation region and having a higher breakdown voltage than the first device, the second device having a drift drain structure in which a LOCOS oxide film thicker than a gate insulation film thereof is disposed at an edge of a gate electrode thereof. | 2011-12-01 |
20110294273 | Method and Layout of Semiconductor Device with Reduced Parasitics - An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection. | 2011-12-01 |
20110294274 | METHOD OF FORMING METAL GATE STRUCTURE AND METHOD OF FORMING METAL GATE TRANSISTOR - A method of forming metal gate transistor includes providing a substrate; forming a gate dielectric layer, a work function metal layer and a polysilicon layer stacked on the substrate; forming a hard mask and a patterned photoresist on the polysilicon layer; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the work function metal layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent. | 2011-12-01 |
20110294275 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an isolation layer over a substrate, forming a plurality of open regions exposing the substrate by selectively etching the isolation layer, performing a surface treatment over the isolation layer, expanding the open regions by removing the surface-treated portion of the isolation layer, and forming a conductive layer in the expanded open regions. | 2011-12-01 |
20110294276 | Method of manufacturing semiconductor device - SiOC film ( | 2011-12-01 |
20110294277 | METHODS FOR MANUFACTURING MULTILAYER WAFERS WITH TRENCH STRUCTURES - The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like. | 2011-12-01 |
20110294278 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which prevents damage to alignment marks used for alignment between a superjunction structure and process layers at subsequent steps. In the related art, recesses are made in a semiconductor substrate before the formation of the superjunction structure and used as alignment marks and in order to prevent damage to the alignment marks, the alignment marks are covered by an insulating film such as a silicon oxide film during the subsequent process of forming the superjunction structure, but the inventors have found that damage may penetrate the cover film, reach the semiconductor substrate and destroy the marks. In the method according to the invention, alignment marks for alignment between the superjunction structure and process layers at subsequent steps are formed after the formation of the superjunction structure. | 2011-12-01 |
20110294279 | WORKING METHOD FOR SAPPHIRE SUBSTRATE - A working method for a sapphire substrate for dividing a sapphire substrate along a set planned dividing line includes a cutting groove forming step of positioning a cutting blade, which includes a cutting edge to which diamond grain is secured by nickel plating, to a planned dividing line of the sapphire substrate and feeding the cutting blade and the sapphire substrate relative to each other for working while rotating the cutting blade to form a cutting groove, which serves as a start point of break, along the planned division line on the sapphire substrate, and a breaking step of applying external force to the sapphire substrate, for which the cutting groove forming step is carried out, to break the sapphire substrate along the planned dividing line along which the cutting groove is formed. The cutting groove forming step is set such that a rotational speed of the cutting blade is 20000 to 35000 rpm, a cutting-in depth of the cutting blade is 5 to 15 μm and a working feeding speed is 50 to 150 mm/second. | 2011-12-01 |
20110294280 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided are a method of manufacturing a semiconductor device and a substrate processing apparatus capable of improving defects of conventional CVD and ALD methods, satisfying requirements of film-thinning, and realizing high film-forming rate. The method includes forming a first layer including a first element being able to become solid state by itself on a substrate by supplying a gas containing the first element into a process vessel in which the substrate is accommodated under a condition that a CVD reaction occurs, and forming a second layer including the first element and a second element being unable to become solid state by itself by supplying a gas containing the second element into the process vessel to modify the first layer, wherein a cycle including the forming of the first layer and the forming of the second layer is performed at least once to form a thin film including the first and second elements and having a predetermined thickness. | 2011-12-01 |
20110294281 | METHOD OF AT LEAST PARTIALLY RELEASING AN EPITAXIAL LAYER - A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate. | 2011-12-01 |
20110294282 | Semiconductor device and method for manufacturing the same - A method for manufacturing a semiconductor device including a vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type. | 2011-12-01 |
20110294283 | MOCVD REACTOR HAVING CYLINDRICAL GAS INLET ELEMENT - The invention relates to a device for depositing semiconductor layers, comprising a process chamber ( | 2011-12-01 |
20110294284 | METHOD FOR DEPOSITING ULTRA FINE GRAIN POLYSILICON THIN FILM - According to the present invention, a method for depositing an ultra-fine crystal particle polysilicon thin film supplies a source gas in a chamber loaded with a substrate to deposit a polysilicon thin film on the substrate, wherein the source gas contains a silicon-based gas, a nitrogen-based gas and a phosphorous-based gas. The mixture ratio of the nitrogen-based gas to the silicon-based gas among the source gas may be 0.03 or lower (but, excluding zero). Nitrogen in the thin film may be 11.3 atomic percent or lower (but, excluding zero). | 2011-12-01 |
20110294285 | PHOTO KEY AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE PHOTO KEY - A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns. | 2011-12-01 |
20110294286 | REVERSE PLANARIZATION METHOD - A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a semiconductor feature over the substrate; forming a first photoresist layer over the substrate; performing a lithography process on the first photoresist layer, such the first photoresist layer includes an opening therein that exposes the semiconductor feature; performing a stabilization process on the first photoresist layer; forming a second photoresist layer over the first photoresist layer, wherein the second photoresist layer fills the opening; and etching back the first and second photoresist layers until the semiconductor feature is exposed. | 2011-12-01 |
20110294287 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE - A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate. | 2011-12-01 |
20110294288 | METHOD OF FABRICATING METAL INTERCONNECTION AND METHOD OF FABRICATING IMAGE SENSOR USING THE SAME - A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region. | 2011-12-01 |
20110294289 | Method for Producing a Connection Electrode for Two Semiconductor Zones Arranged One Above Another - A method for producing a connection electrode for a first and second adjacent and complementarily doped semiconductor zones includes a step of producing a trench extending through the first semiconductor zone into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes producing a first connection zone in the first semiconductor zone by implanting dopant atoms into the sidewalls at least at a first angle. The method further includes producing a second connection zone in the second semiconductor zone by implanting dopant atoms at least at a second, different angle. The method also includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode. | 2011-12-01 |
20110294290 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A three-dimensional semiconductor memory device includes a stacked structure including a plurality of conductive patterns, an active pillar penetrating the stacked structure, and a data storage pattern between the active pillar and the conductive patterns, wherein the active pillar includes a vertical semiconductor pattern penetrating the stacked structure and protruding semiconductor patterns between the vertical semiconductor pattern and the data storage pattern, the protruding semiconductor patterns having a different crystalline structure from that of the vertical semiconductor pattern. | 2011-12-01 |
20110294291 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less. | 2011-12-01 |
20110294292 | METHOD OF FORMING A SHARED CONTACT IN A SEMICONDUCTOR DEVICE - A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material. | 2011-12-01 |
20110294293 | CHEMICAL PLANARIZATION OF COPPER WAFER POLISHING - Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarzing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer. | 2011-12-01 |
20110294294 | PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 2011-12-01 |
20110294295 | METHOD FOR MAKING THREE-DIMENSIONAL NANO-STRUCTURE ARRAY - A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed. | 2011-12-01 |
20110294296 | Using edges of self-assembled monolayers to form narrow features - The present invention provides a method for manufacturing a structure over a semiconductor substrate. To form a trench, a patterned layer is formed on a portion of a substrate such that the patterned layer forms a target area located adjacent an edge of the patterned layer. A self-assembled monolayer (SAM) is coupled to the substrate up to the patterned layer, but excluded from the patterned layer. The substrate is then removed within the target area. A wire is formed in a similar fashion except that the first SAM is exchanged with a second SAM in the target area. Then either the substrate outside of the target area is removed, or conductive metal crystals are grown within the target area. Such structures may be advantageously used in the manufacture of a number of active or passive electronic devices, such as a field effect transistor. | 2011-12-01 |
20110294297 | Method of manufacturing semiconductor device - In a method of forming a dense contact-hole pattern in a semiconductor device, the method uses a self-align double patterning technique including forming a square or triangular lattice dot pattern on double layers of mask materials, forming first holes in the upper mask material and second holes wider than the first holes in the lower mask material by double patterning, additionally forming an insulating layer to a thickness such that the first holes are closed such that voids are left in the second holes, and transferring the shape of the voids to a base layer. The hole pattern formed thereby has a high precision, with a density thereof being double or triple that of a pattern formed by a lithography technique. | 2011-12-01 |
20110294298 | TEXTURED SINGLE CRYSTAL - A method for fabricating a textured single crystal including depositing pads made of metal on a surface of a single crystal. A protective layer is deposited on the pads and on the single crystal between the pads; and etching the surface with a first compound that etches the metal more rapidly than the protective layer is carried out. Processing continues with etching the surface with a second compound that etches the single crystal more rapidly than the protective layer; and etching the surface with a third compound that etches the protective layer more rapidly than the single crystal. The textured substrate may be used for the epitaxial growth of GaN, AlN or III-N compounds (i.e. a nitride of a metal the positive ion of which carries a +3 positive charge) in the context of the fabrication of LEDs, electronic components or solar cells. | 2011-12-01 |
20110294299 | METHOD AND APPARATUS FOR SILICON OXIDE RESIDUE REMOVAL - A method for removing silicon oxide based residue from a stack with a doped silicon oxide layer with features with diameters less than 100 nm is provided. A wet clean solution of between 25% to 60% by weight of NH | 2011-12-01 |
20110294300 | SELECTIVE ETCH FOR SILICON FILMS - A method of etching patterned heterogeneous silicon-containing structures is described and includes a remote plasma etch with inverted selectivity compared to existing remote plasma etches. The methods may be used to conformally trim polysilicon while removing little or no silicon oxide. More generally, silicon-containing films containing less oxygen are removed more rapidly than silicon-containing films which contain more oxygen. Other exemplary applications include trimming silicon carbon nitride films while essentially retaining silicon oxycarbide. Applications such as these are enabled by the methods presented herein and enable new process flows. These process flows are expected to become desirable for a variety of finer linewidth structures. Methods contained herein may also be used to etch silicon-containing films faster than nitrogen-and-silicon containing films having a greater concentration of nitrogen. | 2011-12-01 |
20110294301 | Method of Preventing Premature Drying - A method for processing a substrate includes receiving a substrate and processing the substrate using a first fluid meniscus and a second fluid meniscus. The first fluid meniscus and the second fluid meniscus are applied to a surface of the substrate such that the first fluid meniscus is spaced apart from the second fluid meniscus by a transition region. A saturated gas chemistry is applied to the surface of the substrate at the transition region. The saturated gas chemistry is configured to maintain moisture in the transition region so as to prevent drying of the surface of the substrate in the transition region, before the second fluid meniscus is applied to the surface of the substrate. | 2011-12-01 |
20110294302 | Method for Fast Macropore Etching in n-Type Silicon - Method for the electrochemical etching of macropores in n-type silicon wafers, using illumination of the wafer reverse sides and using an aqueous electrolyte, characterized in that the electrolyte is an aqueous acetic acid solution with the composition of H | 2011-12-01 |
20110294303 | CONFINED PROCESS VOLUME PECVD CHAMBER - An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, a shield member disposed in the processing chamber below the substrate support, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source, and an electrode separated from the conductive gas distributor and the chamber body by electrical insulators. The electrode is also coupled to a source of electric power. The substrate support is formed with a stiffness that permits very little departure from parallelism. The shield member thermally shields a substrate transfer opening in the lower portion of the chamber body. A pumping plenum is located below the substrate support processing position, and is spaced apart therefrom. | 2011-12-01 |
20110294304 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine. | 2011-12-01 |
20110294305 | Antireflective Coating - Device and method for an antireflective coating to improve image quality in an image display system. A preferred embodiment comprises a first high refractive index layer overlying a reflective surface of an integrated circuit, a first low refractive index layer overlying the first high refractive index layer, a second high refractive index layer overlying the first low refractive index layer, and a second low refractive index layer overlying the second high refractive index layer. The alternating layers of high refractive index material and low refractive index material form an optical trap, allowing light to readily pass through in one direction, but not so easily in a reverse direction. The dual alternating layer topology improves the antireflective properties of the antireflective layer and permits a wide range of adjustments for manipulating reflectivity and color point. | 2011-12-01 |
20110294306 | CONTROLLED PROCESS AND RESULTING DEVICE - A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN or SiC. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film. | 2011-12-01 |
20110294307 | PCB HAVING CONNECTOR SOCKET MATING WITH TERMINAL PLUG OF FPCB - A PCB includes a mounting surface, a face-down connector socket, a face-up connector socket, and a number of electronic components. The mounting surface defines two connector outlines arranged in a back-to-back fashion. The face-down connector socket and the face-down connector socket are selectively mounted to the mounting surface within the corresponding connector outlines to facilitate a connection with a terminal plug of an FPCB. The electronic components are mounted to the mounting surface, outside the connector outlines. | 2011-12-01 |
20110294308 | SUBSTRATE AND IC SOCKET - There is provided a substrate that includes a base substrate, a socket that has a step where the step has a first surface and a second surface, the socket being electrically coupled with the base substrate at the first surface; and a connection substrate that is disposed between the second surface and the base substrate, where the connection substrate is electrically coupled with the socket at the second surface. | 2011-12-01 |
20110294309 | EXPANSION CARD AND EXPANSION APPARATUS THEREOF - An expansion card includes a card body and an expansion apparatus. The expansion apparatus includes a connection board and a connector mounted to the connection board to connect to the card body. A connection portion is mounted to the connection board and connected to the connector. When the connection portion is connected to the expansion slot, the connection portion receives signals from the expansion slot and output the signals to the card body. | 2011-12-01 |
20110294310 | MEMORY CARD AND MEMORY CARD HOLDING STRUCTURE - A memory card includes a first memory unit and the second memory unit. The first memory unit and the second memory unit are detachably connected together and are capable of storing and transmitting data, and are capable of working independently. A memory card holding structure using the memory card is also described. The first memory unit and the second memory unit are detachably incorporated together and electrically connected to the connector. Thus, each memory unit can be respectively detached and replaced, which does not affect normal operation of other memory unit. Moreover, the memory cards have two or more memory chip card functions. | 2011-12-01 |
20110294311 | ELECTRICAL DISTRIBUTION CENTER ASSEMBLY - An electrical distribution center assembly includes a housing having a connector shroud. The shroud defines a shroud cavity adapted for receiving a mating electrical connector body. A blade stabilizer is formed integral with the shroud in a first position within the shroud cavity. The blade stabilizer has blade apertures formed therein. Bladed terminals extend from the housing into the blade apertures. In this position, the blade stabilizer protects the terminal blades from being bent away from a terminal axis. The blade stabilizer is movable to a second position to enable female terminals of the mating electrical connector to electrically connect to the blade terminals. | 2011-12-01 |
20110294312 | ELECTRICAL CONNECTOR FOR MOUNTING A RIBBON CABLE ON A PRINTED CIRCUIT BOARD - A connector and cable assembly is provided for mounting on a printed circuit board. The assembly includes a ribbon cable having an end that includes an electrical conductor. The assembly also includes an electrical connector that includes a dielectric body comprising a circuit side, a cable side that is opposite the circuit side, and a contact opening that extends through the body. The electrical connector also includes an electrical contact having a cable segment and a tail extending from the cable segment. The electrical contact is held within the contact opening such that at least a portion of the cable segment extends along the cable side of the body and at least a portion of the tail projects from the circuit side of the body. The cable segment is electrically connected to the electrical conductor of the ribbon cable. The tail is configured to be separably mated with the printed circuit board. | 2011-12-01 |
20110294313 | RECEPTACLE CONNECTOR - A receptacle connector is provided for mounting on a printed circuit having a contact mounting area and an incoming trace that extends into the contact mounting area. The receptacle connector includes a housing having a slot configured to receive a mating connector therein. The receptacle connector also includes an upper contact and a lower contact held by the housing. The upper and lower contacts include mating segments, mounting feet, and intermediate segments that extend between the mating segments and the mounting feet. The mounting foot of the lower contact is configured to be mounted on the incoming trace of the printed circuit such that the mounting foot creates a conductive path between the incoming trace and the intermediate segment of the lower contact. The conductive path forms part of a propagation path of electrical current through the electrical trace and the lower contact. | 2011-12-01 |
20110294314 | ELECTRICAL CONNECTOR HAVING BOARD ESCHEWING CAVITY - An electrical connector assembly includes a first electrical connector and a second circuit board mounted with a second electrical connector which is intended to mate the first connector, the first electrical connector further includes a recessed cavity to receive a board edge of the second circuit board when the first electrical connector is mated with the second electrical connector. | 2011-12-01 |
20110294315 | CIRCUIT BOARD MODULE AND ELECTRONIC DEVICE PROVIDED WITH THE SAME - Provided are a circuit board module and an electronic device provided with the same capable of increasing the strength of a card connector, with the configuration that the card connector is mounted to have a specific space from the board. The circuit board module is provided with a card connector portion | 2011-12-01 |
20110294316 | LOW PROFILE ELECTRICAL CONNECTOR TERMINAL AND METHOD OF MOUNTING TERMINAL ON PRINTED CIRCUIT BOARDD - An electrical connector assembly comprises a printed circuit board (PCB) having opposite upper and lower surfaces, an insulating housing having opposite top and bottom surfaces and a plurality of terminals disposed on a bottom surface thereof. Each terminal defines a fusible member disposed thereon. The insulating housing can place the terminal on the upper surface of the PCB and is removed from the terminals after the terminals are soldered on the PCB through the fusible members. | 2011-12-01 |
20110294317 | GROUND CONNECTING DEVICE AND WIRE HARNESS HAVING THE SAME - Provided are a ground connecting device occupying only a little space and a wire harness having the ground connecting device. The ground connecting device comprises first and second ground joint connectors to connect a plurality of first and second grounding wires included in a wire harness to a ground site. The first ground joint connector includes a plurality of first wire terminals to be attached to respective terminal ends of the first grounding wires and a first ground conductor having a first ground-side terminal portion and a first connector housing which holds the first ground conductor. The second ground joint connector includes a plurality of wire terminals to be attached to respective terminal ends of the second remaining grounding wires, and a second ground conductor having a second ground-side terminal portion, and a second connector housing which holds the second ground conductor. The first and second connector housings are stacked above a wall surface while the ground-side terminal portions of the first and second ground conductors are stacked. | 2011-12-01 |
20110294318 | VARIABLE GROUNDING PLUG DESIGN FOR CONTINENTAL EUROPE - An electrical plug for charging a vehicle is provided. The electrical plug has variable grounding and includes a plug body and a collar configured to selectively adjust between a first and second position along the plug body to selectively expose a face portion of the electrical plug. The electrical plug further includes a first electrical prong and a second electrical prong extending from the face portion, the first and second electrical prong enable current transmission. The electrical plug further includes a plurality of grounding mechanisms compatible with a plurality of receptacles respectively, each of the plurality of grounding mechanisms provide a connection to ground. | 2011-12-01 |
20110294319 | Line System - The invention relates to a line system, in particular in an aircraft cabin. The line system has a line channel ( | 2011-12-01 |
20110294320 | WALL PHONE JACK COVER APPARATUS - An apparatus for covering an unused wall telephone jack assembly is disclosed, the apparatus additionally hosting one or more items such as a notepad, writing instrument, whiteboard, keys or picture frame. The apparatus has a frame that fits over the wall telephone jack assembly and conceals it. The apparatus is attached to the wall jack using either wall telephone jack screws or wall phone mounting screws located on the wall telephone jack assembly. Several embodiments and variations are presented; the one embodiment has a front plate and a back plate comprising the frame; another embodiment having the frame as a single unit. In the embodiments, an elastic ribbon mounted on the front of the frame that releasably supports a notepad, and a shelf mounted on the frame supports a writing instrument are included. The inventive concept applies to other unused wall-mounted electrical devices. | 2011-12-01 |
20110294321 | ELECTRICAL PLUG CONNECTOR - An electrical plug connector includes a first plug having a first clip and a second clip, and a second plug including a catch element, first and second releasing tabs and an unlatching element. At least one of the first clip and second clip is configured to engage the catch element. The first and second releasing tabs respectively contact the first and second clips in a plugged state of the electrical plug connector and are configured to release the respective clip from the catch element. The unlatching element surrounds the first and second releasing tabs in the plugged state of the electrical plug connector so as to contact the first releasing tab on a first side and to contact the second releasing tab on an opposing side. The unlatching element is displaceable in a direction transverse to a longitudinal axis of the electrical plug connector. In the plugged state, the connector is configured to receive a tool between the unlatching element and at least one of the first releasing tab and the second releasing tab. | 2011-12-01 |
20110294322 | Card Connector - A card connector with an ejection mechanism is described. The card connector may include a base member, a cover member, a card accommodating space, and contact lines, which are electrically connected to a card placed into the card accommodating space. The card connector may also include an ejection lever, a spring, which pushes the ejection lever to the card accommodating space, and a pair of guide walls, which lead the ejection lever in a card insertion/withdrawal direction. The card connector may further include an ejection mechanism for pulling the IC card out of the card accommodating space. The ejection lever may include an arm portion, which comes in contact with a front end portion of the card, a spring mounting portion, a slide portion, which is led to a pair of the guide walls, and a pull portion, which extends outside the base member. | 2011-12-01 |
20110294323 | Card connector with ejector - A card connector includes an insulative housing defining a card receiving space, a number of contacts retained in the insulative housing, an ejector received in the insulative housing and a metal shell covering the insulative housing. The ejector includes a movable slider, a spring, and a pin member, the slider defines a heart-shaped slot, and the pin member has a positioning end being rotatablely retained to the insulative housing and a free end being slidable along the heart-shaped slot to lock the slider. A latching piece is retained to the insulative housing and has a catching portion catching the pin member and an elastic portion connecting with the catching portion. When the pin member slides, the catching portion will bring the elastic portion to deflect and provide an outward or inward force to the pin member so as to control a movement trace of the pin member. | 2011-12-01 |
20110294324 | Plug Connector - In order to improve a plug connector comprising a plug connector housing which is designed to be electrically insulating and consists of a plurality of housing parts, at least one contact element which is arranged in a receiving area of the plug connector housing and is accessible for a contact element of a complementary plug connector via a plug opening, and an electric cable which leads into the plug connector housing via a cable opening and the electrical conductor of which is connected to the contact element, in such a manner that the plug connector housing can be configured in as space-saving a manner as possible with creeping current paths which are as large as possible it is suggested that joins between the housing parts and adjoining the receiving area be closed in a materially joined manner and that, as a result, creeping current paths which lead away from the contact element in the receiving area run exclusively to the plug opening and/or to the cable opening. | 2011-12-01 |
20110294325 | SOCKET CONTACT FOR A HEADER CONNECTOR - A header connector includes a housing extending along a longitudinal axis between mating and mounting ends. The housing has contact channels open between the mating and mounting ends, and the housing has air pockets provided between selected ones of the contact channels to control an impedance of socket contacts received in the contact channels. Socket contacts are loaded into the contact channels, with each socket contact including a contact body extending along a longitudinal axis between mating and mounting ends. The contact body has a box-shaped socket at the mating end that clergies a reception area configured to receive a mating contact. The box-shaped socket is configured to engage four different sides of the mating contact. | 2011-12-01 |
20110294326 | FLOATING CONNECTOR - A floating connector including a receptacle having a receptacle contact and a receptacle housing for supporting the receptacle contact, a plug having plug contact and a plug housing for supporting the plug contact, and a positional deviation absorbing mechanism provided in at least one of the receptacle and the plug for capable of absorbing a positional deviation between the receptacle housing and the plug housing at a time of fitting between the receptacle housing and the plug housing. Each of the receptacle contact and the plug contact has a terminal portion abutted to each other at the time of fitting between the receptacle housing and the plug housing, and at least one of the receptacle contact and the plug contact has a support part for supporting the terminal portion in a manner movable relative to the supporting housing. | 2011-12-01 |
20110294327 | WATERPROOF ELECTRICAL CONNECTOR AND SYSTEM - In one possible embodiment, a waterproof connector is provided having pins secured to a bendable board. The bendable board and a portion of each of the pins are encased in a compressible material capable of providing a biasing force on the plurality of pins upon mating with a mating surface. The compressible material also provides a deformable sealing surface for mating with the mating surface. | 2011-12-01 |
20110294328 | PLUG LOCKING DEVICE - A locking device that locks a power feeding plug to an inlet of an plug-in vehicle to restrict removal of the power feeding plug from the inlet. The locking device includes a housing coupled to the inlet. The housing covers a peripheral portion of the inlet and includes a hook port that receives the hook when the power feeding plug is inserted into the inlet. A lock bar, which is arranged in the housing, moves between a lock position, in which the lock bar locks the hook to the inlet, and an unlock position, in which the lock bar permits the hook to move relative to the inlet. The lock bar, when located at the lock position, blocks the hook, which is hooked to the inlet, to restrict removal of the housing from the inlet. | 2011-12-01 |
20110294329 | CONNECTOR - A male connector comprises: a holder, attached rotatably to the outer peripheral surface of a plug main unit portion, having male threads formed on the outer peripheral surface thereof and having sliding grooves formed at specific intervals at the rearward side on the outer peripheral surface; and a knob portion, formed integrally with engaging protruding portions that have engaging hooks on the tip end sides thereof and that sliding in the sliding grooves, where the knob portion is attached so as to be able to rotate together with the holder. | 2011-12-01 |
20110294330 | FASTENER AND ELECTRIC CONNECTOR DEVICE HAVING THE SAME - A fastener for securing a chip module onto a circuit board includes a fixing bracket mounted on the circuit board; a pressing frame covering the chip module; a lever having a driving portion and a shaft portion, wherein the shaft portion is formed by extending and bending from the driving portion, with the shaft portion running through the fixing bracket and the pressing frame for controlling the forward and backward rotation of the pressing frame; a protective cover mounted on the pressing frame, wherein a projection portion is formed on a bottom surface of the protective cover and located at the rear end of the chip module, and the projection portion has a slant surface adjacent to the chip module; and thereby, when the pressing frame moves forward, the slant surface presses against the chip module. | 2011-12-01 |
20110294331 | CONNECTOR - A connector is provided which is rugged and will not be broken when stepped on, prevents a socket from being removed and disconnected from a plug when subjected to accidental forces or inadvertently pressed, is simple in structure, and can be manufactured at a low cost. | 2011-12-01 |
20110294332 | AUTOMOBILE CABLE SOCKET - An automobile cable socket. The automobile cable socket including a first socket member that is disposed to surround the first cable and includes a plurality of sawtooth portions formed on an external surface thereof in a direction in which the first cable extends, a second socket member coupled to the first socket member and including an engaging portion, a spring installed outside of the second socket member, and a position fix member that is disposed between the second socket member and the spring, releases engagement between the engaging portion of the second socket member and the plurality of sawtooth portions of the first socket member by pressing the spring, and engages the plurality of sawtooth portions with the engaging portion when the spring is restored to an original position. | 2011-12-01 |
20110294333 | CABLE CONNECTOR ASSEMBLY WITH LATCH MECHANISM - A cable connector assembly includes a housing and a plurality of conductive contacts located in the housing. The housing defines a receiving room therein and a mating port through which a complementary connector is inserted into the receiving room. A plurality of cables electrically connects with the conductive contacts. A latch mechanism is assembled to an outside face of the housing and includes a latch member and a pulling member connecting with the latch member. The latch member defines a pair of hook portions inserted into the receiving room from the outside face and latching with the complementary connector. The latch member further defines a pair of shaft pins and the pulling member defines a pair of shaft holes. The shaft pins are pivotedly received in the shaft holes. | 2011-12-01 |
20110294334 | LATCH FOR A CABLE ASSEMBLY - A latch assembly for a connector is provided. The latch assembly includes a latch coupled to the connector. The latch includes a crossbar and a latch arm extending from the crossbar. The latch arm is configured to engage a mating connector. An anchor point engages the latch. The latch rotates about the anchor point between an open position, where the latch arm is configured to disengage from the mating connector, and a closed position. where the latch arm is configured to engage the mating connector. A biasing mechanism engages the crossbar of the latch to bias the latch into the closed position, wherein in the closed position the latch assembly generates a latch force on the mating connector in a direction opposite to a load force imposed on at least one of the connector and the mating connector. | 2011-12-01 |
20110294335 | Electrical connector - The present invention relates to an electrical connector with a first and a second sub-assembly. The first sub-assembly comprises a contact area for receiving a conductor end and for establishing an electrical contact with the received conductor end. The first sub-assembly further comprises a clamping device for clamping the conductor in the contact area. The second sub-assembly comprises a hollow body with a hollow space for receiving the contact area. The first and the second sub-assemblies are made as one piece and are configured to release the clamping device in the open state for manually clamping the conductor end, and to electrically insulate the contact area including the clamping device in the closed state. | 2011-12-01 |
20110294336 | MOUNTING FOR A DC-AC CONVERTER AND METHOD FOR FITTING A DC-AC CONVERTER - The invention relates to a mounting ( | 2011-12-01 |
20110294337 | SYMMETRIC HEADER CONNECTOR - A header connector includes socket contacts having a socket portion extending along a longitudinal axis that defines a reception area configured to receive a mating contact. A housing extends along a central axis between mating and mounting ends and has contact channels open between the mating and mounting ends that receive the socket contacts. The housing has a primary plane and a secondary plane with the contact channels being arranged symmetrically about the primary plane and the secondary plane such that the housing is configured to be mated with a receptacle connector in a first orientation and a second orientation different than the first orientation. | 2011-12-01 |
20110294338 | CONNECTOR AND MOUNTING ASSEMBLIES INCLUDING STRESS-DISTRIBUTION MEMBERS - A mounting assembly configured to mount a communication connector to a panel of an electrical system. The mounting assembly including a stress-distribution member that has an abutment surface abutting a flange of the connector. The stress-distribution member has a fastener opening. The mounting assembly also includes a fastener element that extends along a central axis. The fastener element has a cross-section taken perpendicular to the central axis that is sized and shaped to permit the fastener element to be freely inserted through through-holes of the connector and the panel. The fastener element is inserted into the fastener opening and secured to the fastener element. The stress-distribution member distributes mechanical energy provided by the fastener element when the connector is in a shock or vibration environment. | 2011-12-01 |
20110294339 | LOW PROFILE CABLE CONNECTOR ASSEMBLY - A cable connector assembly ( | 2011-12-01 |
20110294340 | CONNECTOR AND CABLE ASSEMBLY - An object is to provide a connector with which a cable assembly with suppressed generation of a noise during high-speed signal transmission can be formed, and a cable assembly using the connector. The connector | 2011-12-01 |
20110294341 | Connector for Connecting Cable and Terminal of Same - A low profile flat printed circuit connector has a plurality of terminals supported along a support bar. The terminals are spaced apart from each other and extend lengthwise in a connector housing. The terminals have body portions that engage the support bar and body portions that extend forwardly thereof. Contact portions are joined to the body portions and extend rearwardly and terminate in free ends so that they form a series of cantilevered contacts. | 2011-12-01 |