48th week of 2012 patent applcation highlights part 17 |
Patent application number | Title | Published |
20120299113 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In a first transistor of a semiconductor device, a first gate insulating film is located on a first active region, and the first gate insulating film includes a first high-κ material of a first metal oxide and a first metal which changes a flat-band voltage of the first transistor. In a second transistor of a semiconductor device, a second gate insulating film is located on a second active region, and the second gate insulating film includes a second high-κ material of a second metal oxide and a second metal which changes a flat-band voltage of the second transistor. The first metal oxide has an amorphous structure. The second metal oxide has a tetragonal or cubic crystal structure. | 2012-11-29 |
20120299114 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention is directed to a semiconductor device which is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer is formed being in contact with a bottom portion of a P type base region under an N+ type emitter region. The N type base width control layer shallows a portion of the P type base region under the N+ type emitter region partially. The P type base region is formed by using a process of forming a P type well region, and the N type base width control layer is formed by using a process of forming an N type well region, thereby achieving the process rationalization. | 2012-11-29 |
20120299115 | SEMICONDUCTOR STRUCTURE WITH SUPPRESSED STI DISHING EFFECT AT RESISTOR REGION - A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate. | 2012-11-29 |
20120299116 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A display panel, in which a plurality of drive units in a transistor array substrate include a faulty drive unit, and a plurality of pixel electrodes include a first pixel electrode corresponding to the faulty drive unit and a second drive unit corresponding to a non-faulty drive unit. A portion of the second pixel electrode is embedded in the corresponding contact hole, and is in contact with a power supply pad of the non-faulty drive unit, so that the second pixel electrode is electrically connected to the non-faulty drive unit. An insulator is inserted between the first pixel electrode and a power supply pad of the faulty drive unit, so that the first pixel electrode is electrically insulated from the faulty drive unit. | 2012-11-29 |
20120299117 | 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed. | 2012-11-29 |
20120299118 | Multiple Threshold Voltages in Field Effect Transistor Devices - A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel. | 2012-11-29 |
20120299119 | STACKED POWER SEMICONDUCTOR DEVICE USING DUAL LEAD FRAME AND MANUFACTURING METHOD - A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip. | 2012-11-29 |
20120299120 | RF Circuits Including Transistors Having Strained Material Layers - Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance. | 2012-11-29 |
20120299121 | Source/Drain Formation and Structure - A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region. | 2012-11-29 |
20120299122 | HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER - A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack. | 2012-11-29 |
20120299123 | Gate-Last Fabrication of Quarter-Gap MGHK FET - A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack. | 2012-11-29 |
20120299124 | GATE STRUCTURE AND A METHOD FOR FORMING THE SAME - A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure. | 2012-11-29 |
20120299125 | SELF-ALIGNED CONTACTS - A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer. | 2012-11-29 |
20120299126 | INTEGRATED CIRCUIT WITH SENSOR AND METHOD OF MANUFACTURING SUCH AN INTEGRATED CIRCUIT - Disclosed is an integrated circuit (IC) comprising a substrate ( | 2012-11-29 |
20120299127 | DYNAMIC QUANTITY SENSOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A dynamic quantity sensor device includes: first and second dynamic quantity sensors having first and second dynamic quantity detecting units; and first and second substrates, which are bonded to each other to provide first and second spaces. The first and second units are air-tightly accommodated in the first and second spaces, respectively. A SOI layer of the first substrate is divided into multiple semiconductor regions by trenches. First and second parts of the semiconductor regions provide the first and second units, respectively. The second part includes: a second movable semiconductor region having a second movable electrode, which is provided by a sacrifice etching of the embedded oxide film; and a second fixed semiconductor region having a second fixed electrode. The second sensor detects the second dynamic quantity by measuring a capacitance between the second movable and fixed electrodes, which is changeable in accordance with the second dynamic quantity. | 2012-11-29 |
20120299128 | METHOD OF BONDING SEMICONDUCTOR SUBSTRATE AND MEMS DEVICE - A method of bonding a semiconductor substrate in which a first semiconductor substrate is bonded with a second semiconductor substrate by eutectic bonding with pressurization and heating, an aluminum containing layer primarily made of aluminum and a germanium layer in a polymer state being interposed between a bonding surface of the first semiconductor substrate and a bonding surface of the second semiconductor substrate, the method including a step of: setting a weight ratio of the germanium layer to an aluminum containing layer to be eutectic alloyed is between 27 wt % to 52 wt %. | 2012-11-29 |
20120299129 | Process and Structure for High Temperature Selective Fusion Bonding - A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding. | 2012-11-29 |
20120299130 | ACCELEROMETER AND PRODUCTION METHOD - A MEMS accelerometer uses capacitive sensing between two electrode layers. One of the electrode layers has at least four independent electrodes arranged as two pairs of electrodes, with one pair aligned orthogonally to the other such that tilting of the membrane can be detected as well as normal-direction movement of the membrane. In this way, a three axis accelerometer can be formed from a single suspended mass, and by sensing using a set of capacitor electrodes which are all in the same plane. This means the fabrication is simple and is compatible with other MEMS manufacturing processes, such as MEMS microphones. | 2012-11-29 |
20120299131 | ARRANGEMENT WITH A MEMS DEVICE AND METHOD OF MANUFACTURING - An arrangement and a production method for the arrangement with at least one MEMS device, which comprises a package that closely encloses the MEMS device and seals it from ambient influences. The package comprises as sealing a PFPE layer of a perfluoropolyether polymerized with the aid of functional groups. | 2012-11-29 |
20120299132 | TUNNELING MAGNETORESISTANCE (TMR) READ SENSOR WITH LOW-CONTACT-RESISTANCE INTERFACES - The invention provides a TMR read sensor with low-contact-resistance metal/metal, metal/oxide and oxide/metal interfaces. The low-contact-resistance metal/metal interfaces in a reference or sense layer structure are in-situ formed in a high-vacuum deposition module of a sputtering system, without exposures to low vacuum in a transfer module and damages caused by a plasma treatment conducted in an etching module. The low-contact-resistance metal/oxide interface is formed by utilizing a thin Co—Fe—B reference layer and a thick Co—Fe reference layer to reduce boron diffusion and segregation caused by annealing. The low-contact-resistance oxide/metal interface is formed by replacing a Co—Fe—B sense layer with a Co-rich Co—Fe sense layer to eliminate boron diffusion and segregation caused by annealing. With the low-contact-resistance metal/metal, metal/oxide and oxide/metal interfaces, the TMR read sensor exhibits a junction resistance-area product of below 0.6 Ω-μm | 2012-11-29 |
20120299133 | MAGNETIC DEVICES AND METHODS OF FABRICATING THE SAME - Magnetic devices and methods of fabricating the same are provided. According to the magnetic device, a tunnel barrier pattern is interposed between a first magnetic pattern and a second magnetic pattern. An edge portion of the tunnel barrier pattern is thicker than a central portion of the tunnel barrier pattern. The central portion of the tunnel barrier pattern has a substantially uniform thickness. | 2012-11-29 |
20120299134 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X) | 2012-11-29 |
20120299135 | NON VOLATILE MEMORY INCLUDING STABILIZING STRUCTURES - An apparatus that includes a magnetic structure including a reference layer; and a free layer; an exchange coupling spacer layer; and a stabilizing layer, wherein the exchange coupling spacer layer is between the magnetic structure and the stabilizing layer and exchange couples the free layer of the magnetic structure to the stabilizing layer. | 2012-11-29 |
20120299136 | PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY - A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact. | 2012-11-29 |
20120299137 | SEED LAYER AND FREE MAGNETIC LAYER FOR PERPINDICULAR ANISOTROPY IN A SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY - A magnetic layer that includes a seed layer comprising at least tantalum and a free magnetic layer comprising at least iron. The free magnetic layer is grown on top of the seed layer and the free magnetic layer is perpendicularly magnetized. The magnetic layer may be included in a magnetic tunnel junction (MTJ) stack. | 2012-11-29 |
20120299138 | Wafer Level Optical Packaging System, And Associated Method Of Aligning Optical Wafers - An optical system has a first relief-type diffraction grating fiducial, or alignment mark, on a transparent surface of a first optical wafer or plate, the grating arranged to deflect light away from an optical path and appear black. The first wafer may have lenses. The first fiducial is aligned to another fiducial on a second wafer having further optical devices as part of system assembly; or the fiducials are aligned to alignment marks or fiducials on an underlying photosensor. Once the optical devices are aligned and the wafers bonded, they are diced to provide aligned optical structures for a completed camera system. Alternatively, an optical wafer is made by aligning a second relief-type diffraction grating fiducial on a first master to a first relief-type diffraction grating fiducial on an optical wafer preform, pressing the first master into a blob to form optical shapes and adhere the blob to the optical wafer preform. | 2012-11-29 |
20120299139 | METHOD OF FABRICATION OF AN ARRAY OF GRADED REFRACTIVE INDEX MICROLENSES INTEGRATED IN A IMAGE SENSOR - Methods and devices that incorporate microlens arrays are disclosed. An image sensor includes a pixel layer and a dielectric layer. The pixel layer has a photodetector portion configured to convert light absorbed by the pixel layer into an electrical signal. The dielectric layer is formed on a surface of the pixel layer. The dielectric layer has a refractive index that varies along a length of the dielectric layer. A method for fabricating an image sensor includes forming an array of microlenses on a surface of the dielectric layer, emitting ions through the array of microlenses to implant the ions in the dielectric layer, and removing the array of microlenses from the surface of the dielectric layer. | 2012-11-29 |
20120299140 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND CAMERA MODULE - Certain embodiments provide a solid-state imaging device including a curved guide having a curved portion of a concave shape, a sensor substrate, an adhesive, a transparent substrate, and an external electrode. The sensor substrate includes a sensor section, for receiving light collected by a lens and generating charges in accordance with a light receiving quantity, on a surface, has the curved guide fixed on a back surface, and has a region including the sensor section curved downward to a convex shape along the curved portion of the curved guide. The adhesive is formed at a periphery of the sensor section. The transparent substrate is a plate-like substrate fixed on the sensor substrate by the adhesive. The external electrode is formed on the back surface of the sensor substrate, and is electrically connected to the sensor section through a through-electrode provided on the sensor substrate. | 2012-11-29 |
20120299141 | AVALANCHE PHOTODIODE AND AVALANCHE PHOTODIODE ARRAY - An avalanche photodiode including a semiconductor substrate of a first conductivity type, an avalanche multiplication layer, an electric field control layer, a light absorption layer, and a window layer wherein the layers are laid one on another in this order on a major surface of the semiconductor substrate, an impurity region of a second conductivity type in a portion of the window layer, and a straight electrode on the impurity region and connected to the impurity region, the straight electrode being straight as viewed in a plan view facing the major surface of the semiconductor substrate. | 2012-11-29 |
20120299142 | PHOTOELECTRIC CONVERSION DEVICE - Disclosed is a photoelectric conversion device provided with transparent electrodes having high electric conductivity, low optical absorptance, and capable of obtaining a high light scattering effect. A first transparent electrode layer ( | 2012-11-29 |
20120299143 | Thin, very high transmittance, back-illuminated, silicon-on-saphire semiconductor substrates bonded to fused silica - A very high transmittance, back-illuminated, silicon-on-thin sapphire-on-fused silica wafer substrate design is presented for enabling high quantum efficiency and high resolution, silicon or silicon-germanium avalanche photodiode detector arrays with improved indirect optical crosstalk suppression. The wafer substrate incorporates a stacked antireflective bilayer between the sapphire and silicon, comprised of single crystal aluminum nitride (AlN) and non-stoichiometric, silicon rich, amorphous silicon nitride (a-SiN | 2012-11-29 |
20120299144 | SEMICONDUCTOR LIGHT RECEIVING DEVICE - A semiconductor light-detecting device includes: a semi-insulating substrate; and n light-detecting elements (n is a natural number equal to or larger than 4) electrically isolated from each other and on the semi-insulating substrate. Each light-detecting element includes a conductive layer of a first conductivity type, a light absorption layer, a window layer, and an impurity diffusion region of a second conductivity type, which are laminated, one on another, on the semi-insulating substrate. The light absorption layer is a photoelectrical converter. The impurity diffusion region is located in part of the window layer and serves as a light-detecting section. A part of the conductive layer and the light absorption layer use the same material. The n light-detecting elements are not all located on a common straight line. | 2012-11-29 |
20120299145 | APPARATUS FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE - Apparatus configured for the fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO | 2012-11-29 |
20120299146 | VERTICAL ESD PROTECTION DEVICE - A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer. | 2012-11-29 |
20120299147 | TRANSFER METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - After depressed portions ( | 2012-11-29 |
20120299148 | Integrated Circuit and Method of Forming Sealed Trench Junction Termination - An integrated circuit having a substrate with a first conductivity type of semiconductor material. A buried layer is formed in the substrate. The buried layer has a second conductivity type of semiconductor material. A first semiconductor layer is formed over the buried layer. The first semiconductor layer has the second conductivity type of semiconductor material. A trench is formed through the first semiconductor layer and buried layer and extends into the substrate. The trench is lined with an insulating layer and filled with an insulating material. A second semiconductor layer is formed in the first semiconductor layer. The second semiconductor layer has the first conductivity type of semiconductor material. A third semiconductor layer is formed in the second semiconductor layer. The third semiconductor layer has the second conductivity type of semiconductor material. The first, second, and third semiconductor layers form the collector, base, and emitter of a bipolar transistor. | 2012-11-29 |
20120299149 | Semicinductor Device with Cross-Talk Isolation Using M-CAP and Method Thereof - A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements. | 2012-11-29 |
20120299150 | Power Semiconductor Module with Embedded Chip Package - A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias. | 2012-11-29 |
20120299151 | Semiconductor Device and Method of Forming RF Balun having Reduced Capacitive Coupling and High CMRR - A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace. | 2012-11-29 |
20120299152 | DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material. | 2012-11-29 |
20120299153 | STACK CAPACITOR STRUCTURE AND FORMING METHOD - The present invention discloses a stack capacitor structure and method of making the same. The top plate of the stack capacitor structure is connected to each other through a connecting node. The method of forming the stack capacitor structure includes providing an insulating substrate with a doped insulating material layer disposed therein. Then, the insulating substrate is patterned to form a trench, wherein an inner sidewall of the trench has a first region and a second region and the doped insulating material layer within the second region is entirely removed to form a hole. Later, a top plate is formed to surround the inner sidewall of the trench, and the top plate fills in the hole. Next, a capacitor dielectric layer is formed to surround the top plate. Finally, a storage node is formed to fill up the trench. | 2012-11-29 |
20120299154 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEBICE - A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal. | 2012-11-29 |
20120299155 | METHOD FOR FORMING FULLY RELAXED SILICON GERMANIUM ON SILICON - Semiconductor devices are formed with a thin layer of fully strain relaxed epitaxial silicon germanium on a substrate. Embodiments include forming a silicon germanium (SiGe) epitaxial layer on a semiconductor substrate, implanting a dopant into the SiGe epitaxial layer, and annealing the implanted SiGe epitaxial layer. | 2012-11-29 |
20120299156 | WAFER PROCESSING METHOD - A wafer processing method includes the steps of: (a) annealing a silicon wafer at a temperature higher than 650° C.; (b) after step (a), depositing a silicon-germanium layer on the silicon wafer; (c) after step (b), implanting oxygen ions into the silicon wafer; and (d) after step (c), annealing the silicon wafer at a temperature higher than 650° C. to form a silicon oxide layer underneath the silicon-germanium layer. | 2012-11-29 |
20120299157 | SEMICONDUCTOR PROCESS AND FABRICATED STRUCTURE THEREOF - A semiconductor process includes the following steps. A substrate is provided, which includes an isolation structure and an oxide layer. The isolation structure divides the substrate into a first region and a second region. The oxide layer is located on the surface of the first region and the second region. A dry cleaning process is performed to remove the oxide layer. A dielectric layer is formed on the first region and the second region. A wet etching process is performed to remove at least one of the dielectric layers located on the first region and the second region. A semiconductor structure is fabricated by the above semiconductor process. | 2012-11-29 |
20120299158 | CMP POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND ELECTRONIC COMPONENT - The CMP polishing liquid of the invention is used by mixing a first solution and a second solution, the first solution comprises cerium-based abrasive grains, a dispersant and water, the second solution comprises a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, the pH of the second solution is 6.5 or higher, and the first solution and second solution are mixed so that the phosphoric acid compound content is within a prescribed range. The CMP polishing liquid of the invention comprises cerium-based abrasive grains, a dispersant, a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, with the phosphoric acid compound content being within a prescribed range. | 2012-11-29 |
20120299159 | STRUCTURE DESIGNS AND METHODS FOR INTEGRATED CIRCUIT ALIGNMENT - Devices and methods for pattern alignment are disclosed. In one embodiment, a semiconductor device includes a die including an integrated circuit region, an assembly isolation region around the integrated circuit region, and a seal ring region around the assembly isolation region. The device further includes a die alignment mark disposed within the seal ring region or the assembly isolation region. | 2012-11-29 |
20120299160 | Method of Forming Contacts for Devices with Multiple Stress Liners - Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness. | 2012-11-29 |
20120299161 | CONDUCTIVE VIA STRUCTURE - The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate and having an opening with a first width over the contact pad; a conductive via within the opening; and a conductive pillar having a second width completely covering the conductive via, wherein a ratio of the first width to the second width is from about 0.15 to 0.55. | 2012-11-29 |
20120299162 | BARRIER FILM FOR ELECTRONIC DEVICE, METHOD OF MANUFACTURE THEREOF, AND ARTICLES INCLUDING THE SAME - A barrier film for an electronic device, the barrier film including: a resin film; a layer-by-layer stack portion including a tabular inorganic particle layer and a binder layer which are alternately disposed on the resin film and are oppositely charged; and a filling portion that fills a defect portion of the tabular inorganic particle layer wherein the defect portion is a portion of the tabular inorganic particle layer where a tabular inorganic particle of the tabular inorganic particle layer is not present. | 2012-11-29 |
20120299163 | PIN DIODE - Provided is a PIN diode that can suppress thermal destruction from occurring at the time of a reverse bias exceeding a breakdown voltage by current concentration on a curved part of an anode region. The PIN diode is configured to have: a semiconductor substrate | 2012-11-29 |
20120299164 | PIN DIODE - A PIN diode having improved avalanche resistance is provided. The PIN diode includes: a semiconductor substrate | 2012-11-29 |
20120299165 | Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer - A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure. | 2012-11-29 |
20120299166 | CONDUCTION PATH, SEMICONDUCTOR DEVICE USING THE SAME, AND METHOD OF MANUFACTURING CONDUCTION PATH, AND SEMICONDUCTOR DEVICE - A conduction path includes a first conduction path forming plate ( | 2012-11-29 |
20120299167 | UNIFORMITY CONTROL FOR IC PASSIVATION STRUCTURE - The present disclosure involves a semiconductor device. The semiconductor device includes a wafer containing an interconnect structure. The interconnect structure includes a plurality of vias and interconnect lines. The semiconductor device includes a first conductive pad disposed over the interconnect structure. The first conductive pad is electrically coupled to the interconnect structure. The semiconductor device includes a plurality of second conductive pads disposed over the interconnect structure. The semiconductor device includes a passivation layer disposed over and at least partially sealing the first and second conductive pads. The semiconductor device includes a conductive terminal that is electrically coupled to the first conductive pad but is not electrically coupled to the second conductive pads. | 2012-11-29 |
20120299168 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier having a base carrier hole from a base carrier interconnection side to a base carrier device side; mounting a base integrated circuit over the base carrier; forming an encapsulation over the base carrier covering the base integrated circuit, the encapsulation having an encapsulation top side and having an encapsulation hole directly over the base carrier hole; and forming an interconnection structure as a single integral structure through the base carrier hole and the encapsulation hole, the interconnection structure directly on the encapsulation top side and directly on the base carrier interconnection side. | 2012-11-29 |
20120299169 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 2012-11-29 |
20120299170 | Module and Method of Manufacturing a Module - A module and a method for manufacturing a module are disclosed. An embodiment of a module comprises a first semiconductor device, a frame arranged on the first semiconductor device, the frame comprising a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity. | 2012-11-29 |
20120299171 | LEADFRAME-BASED BALL GRID ARRAY PACKAGING - A metal sheet is patterned into a leadframe that includes metal wiring structures one side and metal pads arranged for ball grid array (BGA) style connection on the other side. A semiconductor chip is bonded to the leadframe, for example, by solder balls that are reflowed onto the side of the leadframe that includes the metal wiring structures. The metal wiring structures provide interconnection among solder balls as needed. Peripheral portions of the leadframe are removed. The bonded structure is embedded in a dielectric molding compound that embeds, and provides mechanical support for, lead structures and the solder balls. The composite structure including the bonded structure and the dielectric molding compound can be bonded to a substrate employing an array of BGA balls that is bonded to the metal pads of the lead structures embedded in the dielectric molding compound. | 2012-11-29 |
20120299172 | LEAD FRAME FOR SEMICONDUCTOR DEVICE - Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM), thereby preventing oxidation of a base layer while simplifying the manufacturing process, reducing the manufacturing costs and reducing a failure ratio. In one embodiment, in the lead frame for a semiconductor device including a die pad and a plurality of leads positioned adjacent to each other around the die pad, the lead frame includes a base layer made of copper; and a first strike plating layer formed on the one or more portions of the surface of the base layer. | 2012-11-29 |
20120299173 | Thermally Enhanced Stacked Package and Method - A package-on-package (PoP) device is provided. The device includes a first package with a first chip mounted on a first substrate, a heat spreader stacked on the first package, the heat spreader in thermal contact with the first chip, and a second package stacked on the heat spreader. In an embodiment, the heat spreader is formed using carbon fibers to provide good lateral thermal conductivity. In an embodiment, ends of the heat spreader project beyond a periphery of the first and second packages. | 2012-11-29 |
20120299174 | Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected By Bumps and Conductive Vias - A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via. | 2012-11-29 |
20120299175 | SYSTEMS AND METHODS TO COOL SEMICONDUCTOR - Systems and methods are disclosed for fabricating a semiconductor device by forming heat conducting nanowires on a first side of a wafer; and depositing semiconductor structures on a second side of the wafer. | 2012-11-29 |
20120299176 | Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area - A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer. | 2012-11-29 |
20120299177 | SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING THE SAME - A semiconductor component structure is provided, which includes a body formed with openings, an insulating layer formed on surfaces of the body and the openings, conductive bumps formed in the openings, and a re-distributed circuit formed by conductive traces electrically connecting the conductive bumps, wherein the conductive traces are formed on a portion of the insulating layer on the body. As the conductive traces and the conductive bumps are formed on and in the body prior to the formation of the re-distributed circuit. The process for fabricating the semiconductor component structure is simplified and the reliability of the semiconductor component structure is enhanced. A method for fabricating the semiconductor component is also provided. | 2012-11-29 |
20120299178 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad. | 2012-11-29 |
20120299179 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be farmed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 2012-11-29 |
20120299180 | BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT COMPRISING A PLURALITY OF BONDING PAD STRUCTURES - A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer. | 2012-11-29 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 2012-11-29 |
20120299182 | COPPER BONDING WIRE FOR SEMICONDUCTOR AND BONDING STRUCTURE THEREOF - It is an object of the present invention to provide a bonding structure and a copper bonding wire for semiconductor that are realizable at an inexpensive material cost, superior in a long-term reliability of a bonded portion bonded to an Al electrode, and suitable for use in a vehicle-mounted LSI. A ball-bonded portion is formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the aforementioned ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion. | 2012-11-29 |
20120299183 | SEMICONDUCTOR DEVICE AND STACKED-TYPE SEMICONDUCTOR DEVICE - In a semiconductor device according to the present invention, a solder resist has a plurality of openings that expose electrodes. Solder bumps are formed in the openings and each have a solder ball portion protruding from the corresponding opening. The height of the openings is set to increase with increasing gap distance between the electrodes of an interposer substrate and board electrodes of a printed wiring board on which the semiconductor device is mounted. Thus, the solder bumps that correspond to sections where the gap distance is large can be increased in height, whereas the solder bumps that correspond to sections where the gap distance is small can be decreased in height, thereby avoiding the occurrence of defective joints caused by a reduction in size and thickness of the interposer substrate, as well as extending the lifespan of solder joints. | 2012-11-29 |
20120299184 | SYSTEM AND METHOD FOR MONITORING COPPER BARRIER LAYER PRECLEAN PROCESS - A monitor wafer for use in monitoring a preclean process and method of making same are described. One embodiment is a monitor wafer comprising a silicon base layer; a capping layer disposed on the silicon base layer; and a barrier layer disposed on the USG layer. The monitor wafer further comprises a copper (“Cu”) seed layer disposed on the barrier layer; and a thick Cu layer disposed on the Cu seed layer. | 2012-11-29 |
20120299185 | Slit Recess Channel Gate and Method of Forming the Same - A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate. | 2012-11-29 |
20120299186 | SEMICONDUCTOR DEVICE - A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge. | 2012-11-29 |
20120299187 | Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products - Embodiments of an aluminum pad thinning in bond pad for fine pitch ultra-thick aluminum pad structures are provided herein. Embodiments include a conductive structure formed on a substrate. A first passivation layer is formed over the substrate and the conductive structure, the first passivation layer having an opening formed over the conductive structure. An ultra-thick conductive structure having a thinned trench region formed over the opening of the first passivation layer. The ultra-thick conductive structure is in contact with the conductive structure. A second passivation layer formed over the first passivation region and the ultra-thick conductive structure. The second passivation layer having an opening formed over the thinned trench region of the ultra-thick conductive structure. | 2012-11-29 |
20120299188 | WIRING STRUCTURE AND METHOD OF FORMING THE STRUCTURE - Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity. | 2012-11-29 |
20120299189 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND METHOD OF FORMING CONTACT STRUCTURE - When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole. | 2012-11-29 |
20120299190 | METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS - A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias. | 2012-11-29 |
20120299191 | Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected Through Conductive Vias Formed in Encapsulant Around Die - A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. | 2012-11-29 |
20120299192 | PAD STRUCTURE, CIRCUIT CARRIER AND INTEGRATED CIRCUIT CHIP - A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad. | 2012-11-29 |
20120299193 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, INTERPOSER, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND INTERPOSER MANUFACTURING METHOD - A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area. | 2012-11-29 |
20120299194 | SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES - A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of spikes that extends from the first portion into the substrate, each of the spikes being spaced apart form one another. | 2012-11-29 |
20120299195 | CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD - A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface. | 2012-11-29 |
20120299196 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead. | 2012-11-29 |
20120299197 | SEMICONDUCTOR PACKAGES - Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter. | 2012-11-29 |
20120299198 | INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS - High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed. | 2012-11-29 |
20120299199 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 2012-11-29 |
20120299200 | 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER - A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer. | 2012-11-29 |
20120299201 | Use of a Local Constraint to Enhance Attachment of an IC Device to a Mounting Platform - An embodiment is directed to an IC mounting assembly that comprises an IC device having a first planar surface, wherein multiple electrically conductive first terminals are located at the first surface. The assembly further comprises an IC device mounting platform having a second planar surface in closely spaced relationship with the first surface, wherein multiple electrically conductive second terminals are located at the second surface, each second terminal corresponding to one of the first terminals. A solder element extends between each first terminal and its corresponding second terminal, and a constraining element is fixably joined to the second surface, wherein the constraining element has a CTE which is selectively less than the CTE of the mounting platform at the second surface. The constraining element is provided with a number of holes or apertures, and each hole is traversed by a solder element that extends between a first terminal and its corresponding second terminal. | 2012-11-29 |
20120299202 | MOUNTING STRUCTURE OF SEMICONDUCTOR PACKAGE COMPONENT AND MANUFACTURING METHOD THEREFOR - A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity η | 2012-11-29 |
20120299203 | POLYMER HAVING SILPHENYLENE AND SILOXANE STRUCTURES, A METHOD OF PREPARING THE SAME, AN ADHESIVE COMPOSITION, AN ADHESIVE SHEET, A PROTECTIVE MATERIAL FOR A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE - One aspect of the present invention provides a polymer having repeating units represented by the formulas (1-1), (1-2) and (1-3) and weight-average molecular weight of from 3,000 to 500,000, as determined by GPC using tetrahydrofuran as a solvent, reduced to polystyrene. Another aspect of the present invention provides an adhesive composition comprising (A) the polymer, (B) a thermosetting resin, and (C) a compound having flux activity. Further, the present invention provides an adhesive sheet having an adhesive layer made of the adhesive composition, a protective material for a semiconductor device, which has the adhesive layer, and a semiconductor device having a cured product obtained from the adhesive composition. | 2012-11-29 |
20120299204 | OVERLAY MARK AND METHOD FOR FABRICATING THE SAME - A method for fabricating an overlay mark, including the steps of: forming a patterned layer on a substrate, wherein the patterned layer comprises at least one mark element forming region, wherein each mark element forming region comprises two column recesses and a plurality of row recesses, and the row recesses connect the two column recesses; growing a mark material from the sidewalls of the column recesses and the row recesses so that the mark material merges in the column recesses and the row recesses; and removing the patterned layer. Consequently, an overlay mark including mark elements with high image contrast is fabricated. | 2012-11-29 |
20120299205 | SYSTEM FOR DENITRIFYING EXHAUST GAS CAPABLE OF PREVENTING BLOCKAGES IN A UREA WATER INFLOW PATH AND AN INJECTION NOZZLE, AND DEVICE FOR SUPPLYING UREA WATER CAPABLE OF PREVENTING THE COAGULATION OF UREA WATER - A system for denitrifying exhaust gas, including a urea water injection unit for supplying urea water and air to a reaction chamber, wherein the urea water injection unit includes: an air supply unit for supplying external air to an injector through an air supply line; a urea water supply unit for supplying urea water to the injector through a urea water supply line; a water supply unit for supplying water to the injector through a water supply line connected to one side of the urea water supply line; a flow control valve for selectively supplying water or urea water to the injector through the urea water supply line; and the injector respectively connected to the air supply unit and the urea water supply unit to selectively discharge air, urea water or water to the reaction chamber through an injection nozzle. | 2012-11-29 |
20120299206 | GENERATOR OF OXYGEN-RICH WATER - Disclosed is a generator of oxygen-rich water. An exemplary embodiment of the present invention provides a generator of oxygen-rich water, including: a housing; a water tank provided in the housing; an oxygen generator provided in the housing; and a mixing unit mixing water supplied from the water tank and oxygen generated from the oxygen generator, wherein the mixing unit includes a hollow fiber membrane therein, and the hollow fiber membrane includes an inlet to which at least one end of a hollow fiber is fixed and a protrusion in which a body of the hollow fiber protrudes and is provided so that water and oxygen flows into an opening of at least one end fixed to the inlet and is discharged to the protrusion. | 2012-11-29 |
20120299207 | SYNTHETIC AMORPHOUS SILICA POWDER AND METHOD FOR PRODUCING SAME - The synthetic amorphous silica powder of the present invention is characterized in that it comprises a synthetic amorphous silica powder obtained by applying a spheroidizing treatment to a granulated silica powder, and by subsequently cleaning and drying it so that the synthetic amorphous silica powder has an average particle diameter D | 2012-11-29 |
20120299208 | METHOD AND DEVICE FOR ACTIVE WEDGE ERROR COMPENSATION BETWEEN TWO OBJECTS THAT CAN BE POSITIONED SUBSTANTIALLY TO PARALLEL TO EACH OTHER - The invention relates to a method and device for expanding the travel or control displacement of linear actuators that is available during an imprinting or embossing stroke. The wedge error compensating head ( | 2012-11-29 |
20120299209 | DEVICE AND METHOD FOR THE LONGITUDINAL STRETCHING OF A FILM WEB - The invention describes a device ( | 2012-11-29 |
20120299210 | PLANT FOR THE CONTINUOUS MANUFACTURE OF AN EXPANDABLE PLASTIC GRANULATE AS WELL AS METHOD FOR PRODUCING IT | 2012-11-29 |
20120299211 | MULTICOMPONENT FIBERS COMPRISING A DISSOLVABLE STARCH COMPONENT, PROCESSES THEREFOR, AND FIBERS THEREFROM - A melt spinnable fiber is provided that comprises a first component comprising a thermoplastic polymer, and a second component comprising thermoplastic starch where the second component is not encompassed by another component or components or if encompassed by another component or components then the second component encompasses a hollow core. A particular use of such a fiber is for removal of the second component in the presence of a solvent in order to produce fibers with desired properties. An agent may be present in the second component for controlling the rate of removal of the second component thereby allowing for physical manipulation of the fiber prior to complete removal of the component. The invention is also directed to nonwoven webs and disposable articles comprising the fibers. | 2012-11-29 |
20120299212 | MOLDING DEVICE AND MOLDING METHOD - A molding device for molding a resin composition into a sheet shape by pressurizing the resin composition has a pair of rollers arranged parallel to one another. Each of the rollers has a columnar or cylindrical core portion and an outer layer provided on an outer periphery of the core portion. The outer layer is constituted of the ceramic material. A thickness of the outer layer is in the range of 0.2 to 100 nm. Further, an arithmetic mean deviation of a profile Ra of an outer peripheral surface of each of the rollers defined by JIS B 0601 is in the range of 0 to 2 μm. | 2012-11-29 |