48th week of 2013 patent applcation highlights part 15 |
Patent application number | Title | Published |
20130313551 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 2013-11-28 |
20130313552 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. | 2013-11-28 |
20130313553 | SEMICONDUCTOR FUSE WITH ENHANCED POST-PROGRAMMING RESISTANCE - Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated. | 2013-11-28 |
20130313554 | ION SENSOR AND DISPLAY DEVICE - The present invention provides an ion sensor with which an ion concentration can be stably measured with high accuracy, and a display device. The present invention is an ion sensor that includes a field effect transistor. The ion sensor also includes an ion sensor antenna and a reset device. The ion sensor antenna and the reset device are connected to a gate electrode of the field effect transistor. The reset device is capable of controlling the potential of the gate electrode and the ion sensor antenna to a predetermined potential. | 2013-11-28 |
20130313555 | PHOTOELECTRIC CONVERISON ELEMENT, PHOTOELECTRIC CONVERSION CIRCUIT, AND DISPLAY DEVICE - A photoelectric conversion element including a first gate electrode, a first gate insulating layer, a crystalline semiconductor layer, an amorphous semiconductor layer, an impurity semiconductor layer, a source electrode and a drain electrode in contact with the impurity semiconductor layer, a second gate insulating layer covering a region between the source electrode and the drain electrode, and a second gate electrode over the second gate insulating layer. In the photoelectric conversion element, a light-receiving portion is provided in the region between the source electrode and the drain electrode, the first gate electrode includes a light-shielding material and overlaps with the entire surface of the crystalline semiconductor layer and the amorphous semiconductor layer, the second gate electrode includes a light-transmitting material and overlaps with the light-receiving portion, and the first gate electrode is electrically connected to the source electrode or the drain electrode is provided. | 2013-11-28 |
20130313556 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An array substrate for a liquid crystal display and a method for manufacturing the same are disclosed. The array substrate for a liquid crystal display includes a source electrode and a drain electrode and an organic insulating film positioned on the source electrode and the drain electrode. The organic insulating layer includes a first contact hole exposing the drain electrode, and having a stepped level difference formed on the sloping surface of the first contact hole. | 2013-11-28 |
20130313557 | DISPLAY APPARATUS - A display apparatus includes a scanning line to which a scanning signal is input, a signal line arranged perpendicular to the scanning line to which an image signal is input, a storage capacity line arranged in parallel with the signal line, an insulating film having a gate insulating portion that covers a gate electrode of a transistor, a pixel electrode connected to the transistor, a capacitor including a first electrode and a second electrode, the first electrode connected to the storage capacity line, the second electrode connected to the pixel electrode, and a protection film having a first insulating portion and a second insulating portion, the first insulating portion covering a source electrode and a drain electrode, the second insulating portion provided between the first electrode and the second electrode, the first electrode and the second electrode arranged to face each other with the second insulating portion disposed therebetween. | 2013-11-28 |
20130313558 | EL Display Device and Method for Manufacturing the Same - A plurality of pixels are arranged on the substrate. Each of the pixels is provided with an EL element which utilizes as a cathode a pixel electrode connected to a current control TFT. On a counter substrate, a light shielding film, a first color filter having a first color and a second color filter having a second color are provided. The second color is different from the first color. | 2013-11-28 |
20130313559 | THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor (TFT) array panel includes: first and second pixel electrodes neighboring each other; a data line extending between the first and the second pixel electrodes; first and second gate lines extending perpendicularly to the data line; a first TFT including a first gate electrode connected to the first gate line, a first source electrode connected to the data line, and a first drain electrode facing the first source electrode and connected to the first pixel electrode; and a second TFT including a second gate electrode connected to the second gate line, a second source electrode connected to the data line, and a second drain electrode facing the second source electrode and connected to the second pixel electrode. The first source electrode has the same relative position with respect to the first drain electrode as the second source electrode with respect to the second drain electrode. | 2013-11-28 |
20130313560 | NON-UNIFORM TWO DIMENSIONAL ELECTRON GAS PROFILE IN III-NITRIDE HEMT DEVICES - A HEMT device has a substrate; a buffer layer disposed above the substrate; a carrier supplying layer disposed above the buffer layer; a gate element penetrating the carrier supplying layer; and a drain element disposed on the carrier supplying layer. The carrier supplying layer has a non-uniform thickness between the gate element and the drain element, the carrier supplying layer having a relatively greater thickness adjacent the drain element and a relatively thinner thickness adjacent the gate element. A non-uniform two-dimensional electron gas conduction channel is formed in the carrier supplying layer, the two-dimensional electron gas conduction channel having a non-uniform profile between the gate and drain elements. | 2013-11-28 |
20130313561 | GROUP III-NITRIDE TRANSISTOR WITH CHARGE-INDUCING LAYER - Embodiments of the present disclosure describe apparatuses, methods, and systems of a device such as a transistor. The device includes a buffer layer disposed on a substrate, the buffer layer being configured to serve as a channel of a transistor and including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer being configured to supply mobile charge carriers to the channel and including aluminum (Al), gallium (Ga), and nitrogen (N), a charge-inducing layer disposed on the barrier layer, the charge-inducing layer being configured to induce charge in the channel and including aluminum (Al) and nitrogen (N), and a gate terminal disposed in the charge-inducing layer and coupled with the barrier layer to control the channel. Other embodiments may also be described and/or claimed. | 2013-11-28 |
20130313562 | PACKAGE-INTEGRATED THIN FILM LED - LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features. There is very little absorption of light by the thinned epitaxial layer, there is high thermal conductivity to the package because the LED layers are directly bonded to the package substrate without any support substrate therebetween, and there is little electrical resistance between the package and the LED layers so efficiency (light output vs. power input) is high. The light extraction features of the LED layer further improves efficiency. | 2013-11-28 |
20130313563 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes. | 2013-11-28 |
20130313564 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device. | 2013-11-28 |
20130313565 | COMPOUND SEMICONDUCTOR DEVICE - The compound semiconductor device comprises an i-GaN buffer layer | 2013-11-28 |
20130313566 | GaN Epitaxy With Migration Enhancement and Surface Energy Modification - Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example. | 2013-11-28 |
20130313567 | BASE SUBSTRATE, GALLIUM NITRIDE CRYSTAL MULTI-LAYER SUBSTRATE AND PRODUCTION PROCESS THEREFOR - A GaN crystal multi-layer substrate having surfaces with various crystal orientations formed on a sapphire base substrate, such as a substrate whose principal surface is a <11-20> plane which is the a-plane, a <1-100> plane which is the m-plane, or a <11-22> plane having a low threading dislocation density and high crystal quality of a GaN crystal, and a production process therefor. | 2013-11-28 |
20130313568 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A silicon carbide substrate has a first conductivity type. The silicon carbide substrate has a first surface provided with a first electrode and a second surface provided with first trenches arranged to be spaced from one another. A gate layer covers an inner surface of each of the first trenches. The gate layer has a second conductivity type different from the first conductivity type. A filling portion fills each of the first trenches covered with the gate layer. A second electrode is separated from the gate layer and provided on the second surface of the silicon carbide substrate. A gate electrode is electrically insulated from the silicon carbide substrate and electrically connected to the gate layer. Thereby, a silicon carbide semiconductor device capable of being easily manufactured can be provided. | 2013-11-28 |
20130313569 | Semiconductor Gas Sensor And Method For Producing The Same - A technique capable of realizing a semiconductor gas sensor having a high rising response speed is provided. A gate insulating film (e.g., a SiO | 2013-11-28 |
20130313570 | MONOLITHICALLY INTEGRATED SIC MOSFET AND SCHOTTKY BARRIER DIODE - A SIC VDMOS transistor is integrated with a SiC SBD, in a seamless way, without any increase of the device area. The SiC SBD is integrated in the active area of the VDMOS by splitting the P-Wells, such that the lightly doped drift region extents all the way to the surface of semiconductor, and by trenching through the source of the VDMOS and partially through the P-Wells to reach the peak of the P-type doping in the P-Well regions. The source of the VDMOS is contacted from the top surface and from the vertical sidewalls of the trenched source and the forward voltage of the Schottky Barrier diode is tailored by using two different metals for the ohmic contact on the source and for the SBD. | 2013-11-28 |
20130313571 | SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR COMPRISING SHIELDING REGIONS AND METHODS OF MANUFACTURING THE SAME - A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region having a first conductivity type, a base region having a second conductivity type opposite the first conductivity type, and an emitter region having the first conductivity type, the collector region, the base region and the emitter region being arranged as a stack. The emitter region defining an elevated structure defined at least in part by an outer sidewall on top of the stack. The base region having a portion capped by the emitter region and defining an intrinsic base region where the intrinsic base region includes a portion extending from the emitter region to the collector region. The SiC BJT can include a first shielding region and a second shield region each having the second conductivity type. | 2013-11-28 |
20130313572 | SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF - Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions. The finished cavities having different depths and nose regions at different heights extending toward each other under the gate, are epitaxially refilled with the strain inducing semiconductor material for the source-drain regions. | 2013-11-28 |
20130313573 | SEMICONDUCTOR RECTIFIER - A semiconductor rectifier includes a first conductivity type wide bandgap semiconductor substrate having a first conductivity type wide bandgap semiconductor layer on an upper surface of which is formed a plurality of first wide bandgap semiconductor regions of the first conductivity type sandwiching a plurality of second wide bandgap semiconductor regions of a second conductivity type, and a plurality of third wide bandgap semiconductor regions of the second conductivity type, at least a part of the third wide bandgap semiconductor regions being connected to the second wide bandgap semiconductor regions and each of the third wide bandgap semiconductor regions having a width smaller than that of the second wide bandgap semiconductor regions. A first electrode is formed on the first and second wide bandgap semiconductor regions and a second electrode is formed on a lower surface of the wide bandgap semiconductor substrate. | 2013-11-28 |
20130313574 | SEMICONDUCTOR POWER MODULE AND METHOD OF MANUFACTURING THE SAME - A semiconductor power module according to the present invention includes a base member, a semiconductor power device having a surface and a rear surface with the rear surface bonded to the base member, a metal block, having a surface and a rear surface with the rear surface bonded to the surface of the semiconductor power device, uprighted from the surface of the semiconductor power device in a direction separating from the base member and employed as a wiring member for the semiconductor power device, and an external terminal bonded to the surface of the metal block for supplying power to the semiconductor power device through the metal block. | 2013-11-28 |
20130313575 | SEMI-INSULATING SILICON CARBIDE MONOCRYSTAL AND METHOD OF GROWING THE SAME - A semi-insulating silicon carbide monocrystal and a method of growing the same are disclosed. The semi-insulating silicon carbide monocrystal comprises intrinsic impurities, deep energy level dopants and intrinsic point defects. The intrinsic impurities are introduced unintentionally during manufacture of the silicon carbide monocrystal, and the deep energy level dopants and the intrinsic point defects are doped or introduced intentionally to compensate for the intrinsic impurities. The intrinsic impurities include shallow energy level donor impurities and shallow energy level acceptor impurities. A sum of a concentration of the deep energy level dopants and a concentration of the intrinsic point defects is greater than a difference between a concentration of the shallow energy level donor impurities and a concentration of the shallow energy level acceptor impurities, and the concentration of the intrinsic point defects is less than the concentration of the deep energy level dopants. The semi-insulating SiC monocrystal has resistivity greater than 1×10 | 2013-11-28 |
20130313576 | SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor power device of the present invention includes a first electrode and a second electrode, a breakdown voltage holding layer that is made of a semiconductor having a predetermined thickness and a predetermined impurity concentration, to which the first electrode and the second electrode are joined, and that has an active region in which carriers to generate electric conduction between the first electrode and the second electrode move, and an insulation film that is formed on the breakdown voltage holding layer and that has a high dielectric-constant portion having a higher dielectric constant than SiO | 2013-11-28 |
20130313577 | LAMINATE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer. | 2013-11-28 |
20130313578 | METHOD OF DRIVING A LIGHT EMITTING DEVICE - The present invention is characterized in that a transistor with its L/W set to 10 or larger is employed, and that |V | 2013-11-28 |
20130313579 | DILUTE SN-DOPED GE ALLOYS - Detectors based on such Ge(Sn) alloys of the formula Ge | 2013-11-28 |
20130313580 | LIGHTING DEVICE - This invention discloses a lighting device for providing an illumination with enhanced color uniformity. The lighting device includes a light generating element adjacent a substrate and configured to produce light having wavelengths substantially within a first wavelength range; a transparent frame attached to the substrate, surrounding the transparent frame; a wavelength converting layer for converting a portion of the light produced by the light generating element into light having wavelengths within a second wavelength range, substantially covering the light emitting surface and at least part of the transparent frame; and a scattering frame configured to substantially scatter light that travels therein, covering a portion of the light emitting surface around periphery thereof to thereby receive a portion of the light leaving the wavelength converting layer around the periphery of the light emitting area. Light components in said portion of the light are substantially mixed in the scattering frame. | 2013-11-28 |
20130313581 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING MODULE - According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer including a first and second surfaces, and a light emitting layer; a p-side electrode provided on the second surface; an n-side electrode provided on the second surface; a first insulating film covering the p-side and the n-side electrodes; a p-side wiring section electrically connected to the p-side electrode through the first insulating film; an n-side wiring section electrically connected to the n-side electrode through the first insulating film; and a phosphor layer provided on the first surface. The phosphor layer has an upper surface and an oblique surface, the oblique surface forming an obtuse angle with the upper surface and inclined with respect to the first surface. Thickness of the phosphor layer immediately below the oblique surface is smaller than thickness of the phosphor layer immediately below the upper surface. | 2013-11-28 |
20130313582 | UNITARY DISPLAY PANNEL AND METHOD OF MANUFACTURING THE SAME - A monolithically integrated display panel is formed to include a substrate, a first electrode disposed on the substrate, a partitioning member disposed above the first electrode where the partitioning member defines a substantially containerizing volume for a to-be-introduced and then later selectively removed sacrificial member, a light attribute controlling material disposed in the containerizing volume and replacing the selectively removed sacrificial member, where an upper width of the light attribute controlling material is substantially different in dimension than a lower width of the light attribute controlling material, and a second electrode disposed above the light attribute controlling material and insulated from the first electrode. | 2013-11-28 |
20130313583 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The present application relates to a light-emitting device and method of manufacturing the same. The device includes a lower portion, and vertical light-emitting structures disposed on the lower portion. A conductive member partially surrounds the vertical light-emitting structures, and reflective members are disposed between the vertical light-emitting structures. The reflective members reflect light that is emitted in a lateral direction from the vertical light-emitting structures to minimize the number of times that light emitted in a lateral direction from the vertical light-emitting structure is transmitted through the light-absorbing member, thereby increasing a luminous efficiency. | 2013-11-28 |
20130313584 | LED illumination device having a first LED chip and a second LED chip, and a method for the production thereof - An LED illumination device ( | 2013-11-28 |
20130313585 | LIGHT EMITTING DEVICE HAVING WAVELENGTH CONVERTING LAYER - Disclosed is a light emitting device having a wavelength converting layer. The light emitting device comprises a plurality of semiconductor stacked structures; connectors for electrically connecting the plurality of semiconductor stacked structures to one another; a single wavelength converting layer for covering the plurality of semiconductor stacked structures; an electrode electrically connected to at least one of the semiconductor stacked structures; and at least one additional electrode positioned on the electrode, passing through the wavelength converting layer to be exposed to the outside, and forming a current input terminal to the light emitting device or a current output terminal from the light emitting device. Since the single wavelength converting layer covers the plurality of semiconductor stacked structures, the plurality of semiconductor stacked structures can be integrally mounted on a chip mounting member such as a package or a module. | 2013-11-28 |
20130313586 | POLARIZATION DOPING IN NITRIDE BASED DIODES - A light emitting device comprising a three-dimensional polarization-graded (3DPG) structure that improves lateral current spreading within the device without introducing additional dopant impurities in the epitaxial structures. The 3DPG structure can include a repeatable stack unit that may be repeated several times within the 3DPG. The stack unit includes a compositionally graded layer and a silicon (Si) delta-doped layer. The graded layer is compositionally graded over a distance from a first material to a second material, introducing a polarization-induced bulk charge into the structure. The Si delta-doped layer compensates for back-depletion of the electron gas at the interface of the graded layers and adjacent layers. The 3DPG facilitates lateral current spreading so that current is injected into the entire active region, increasing the number of radiative recombination events in the active region and improving the external quantum efficiency and the wall-plug efficiency of the device. | 2013-11-28 |
20130313587 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING MODULE THEREOF - A light emitting element including an epitaxy layer, at least one first electrode, at least one second electrode, a first bonding pad and a second bonding pad. The epitaxy layer includes in sequence a first semiconductor layer, an active layer and a second semiconductor layer, and the first semiconductor layer has an exposed portion exposed from the second semiconductor layer and the active layer. The first electrode is disposed at the exposed portion. The second electrode is disposed at the second semiconductor layer. The first bonding pad is connected with the first electrode. The second bonding pad is connected with the second electrode. Two light emitting elements with different structures and the light emitting module utilizing the light emitting elements mentioned above are also disclosed. | 2013-11-28 |
20130313588 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor light emitting device includes a semiconductor layer having a light emitting layer. The device also includes a p-side electrode provided on a first region including the light emitting layer; an n-side electrode provided on a second region layer not including the light emitting layer; and a first insulating film having a first opening communicating with the p-side electrode and a second opening communicating with the n-side electrode. A p-side interconnection is provided on the first insulating film and electrically connected to the p-side electrode through the first opening. An n-side interconnection is provided on the first insulating film and electrically connected to the n-side electrode through the second opening. The p-side interconnection has a plurality of protrusive parts protruding toward the n-side interconnection, and the n-side interconnection has a plurality of portions extending between the protrusive parts of the p-side interconnection. | 2013-11-28 |
20130313589 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT SOURCE UNIT - According to an embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, n-side electrode and a resin layer. The semiconductor layer has a first face and a second face opposite to the first face, and includes a light emitting layer. The p-side electrode is provided on the semiconductor layer on the second face side. The n-side electrode is provided on the semiconductor layer on the second face side. The resin layer is provided on the first face and transmits light emitted from the light emitting layer, the resin layer including a top surface opposite to the first face and four side faces provided along an outer edge of the first face and connected to the top surface, the resin layer including a scattering substance scattering the light emitted from the light emitting layer. | 2013-11-28 |
20130313590 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first interconnection section, a second interconnection section, and a varistor film. The semiconductor layer includes a light emitting layer. The first electrode is provided in a emitting region on the second surface. The second electrode is provided in a non-emitting region on the second surface. The first interconnection section is provided on the first electrode and electrically connected to the first electrode. The second interconnection section is provided on the second electrode and on the first electrode and electrically connected to the second electrode. The varistor film is provided in contact with the first electrode and the second interconnection section between the first electrode and the second interconnection section. | 2013-11-28 |
20130313591 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to an embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode and an insulating layer. The semiconductor layer has a first face and a second face opposite to the first face, and includes a light emitting layer. The p-side electrode is provided in a region including the light emitting layer on the second face side, and the n-side electrode is provided in a region not including the light emitting layer on the second face side. The insulating layer covers the semiconductor layer, the p-side electrode, and the n-side electrode on the second face side, and includes at least a portion containing a magnetic substance. | 2013-11-28 |
20130313592 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to an embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, an second electrode, a first insulating film, a first interconnection and a second interconnection. The semiconductor layer includes a luminous portion and a non-luminous portion. The first electrode is provided on the luminous portion, and the second electrode is provided on the non-luminous portion. The first insulating film is provided on the semiconductor layer, the first electrode and the second electrode. The first interconnection having a first protrusion is provided on the first insulating film and electrically connected to the first electrode. The second interconnection having a second protrusion is provided on the first insulating film and electrically connected to the second electrode. A tip end of the first protrusion faces a tip end of a second protrusion, being apart therefrom with a minimum gap between the first interconnection and the second interconnection. | 2013-11-28 |
20130313593 | LED LIGHTING APPARATUS AND METHOD FOR FABRICATING WAVELENGTH CONVERSION MEMBER FOR USE IN THE SAME - A light-emitting diode (LED) lighting apparatus is provided. The LED lighting apparatus includes at least one LED, and a wavelength conversion member spaced apart from the LED and configured to convert a wavelength of light emitted from the LED. The wavelength conversion member includes a light-transmitting member, and a transfer molded wavelength conversion layer disposed on at least one surface of the light-transmitting member. The transfer molded wavelength conversion layer includes a resin and a phosphor. | 2013-11-28 |
20130313594 | OPTOELECTRONIC ELEMENT AND MANUFACTURING METHOD THEREOF - An optoelectronic element includes an optoelectronic unit having a first top surface; a first metal layer on the first top surface; a first transparent structure surrounding the optoelectronic unit and exposing the first top surface; and a first contact layer on the first transparent structure, including a connective part electrically connected with the first metal layer. | 2013-11-28 |
20130313595 | ENHANCEMENT OF QUANTUM YIELD USING HIGHLY REFLECTIVE AGENTS - Compositions having luminescent properties are described. The compositions can include a luminescent material, such as quantum dots and a reflective material, such as barium sulfate, both suspended in a matrix material. The presence of the reflecting material increases the amount of light captured from the composition. The compositions described herein can be used in back-lighting for LCDs and can also be used in other applications, such as color conditioning of ambient lighting. | 2013-11-28 |
20130313596 | LIGHT-EMITTING DEVICE HAVING PATTERNED INTERFACE AND THE MANUFACTURING METHOD THEREOF - The present disclosure provides a light-emitting device having a patterned interface composed of a plurality of predetermined patterned structures mutually distinct, wherein the plurality of predetermined patterned structures are repeatedly arranged in the patterned interface such that any two neighboring patterned structures are different from each other. The present disclosure also provides a manufacturing method of the light-emitting device. The method comprises the steps of providing a substrate, generating a random pattern arrangement by a computing simulation, forming a mask having the random pattern arrangement on the substrate, and removing a portion of the substrate thereby transferring the random pattern arrangement to the substrate. | 2013-11-28 |
20130313597 | SEMICONDUCTOR LIGHT-EMITTING DEVICES - A semiconductor light-emitting device includes a substrate having an upper surface and a plurality of bumps positioned on the upper surface in a periodic manner, a first conductive type semiconductor layer positioned on the substrate, a light-emitting structure positioned on the first conductive type semiconductor layer, and a second conductive type semiconductor layer positioned on the light-emitting structure. The first conductive type semiconductor layer includes a plurality of protrusions each facing a portion of the substrate between the bumps, the protrusions are positioned in a ring manner at a peripheral region of the first conductive type semiconductor layer, and the protrusions are spaced apart from the bumps. | 2013-11-28 |
20130313598 | ELECTRODE CONTACT STRUCTURE OF LIGHT-EMITTING DIODE - An LED electrode contact structure for an LED is provided. The LED includes a plurality of N-type electrodes, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a mirror layer, a buffer layer, a binding layer, a permanent substrate and a P-type electrode that are stacked in sequence. The N-type semiconductor layer has an irregular surface and a plurality of contact platforms. The contact platforms are formed and distributed on the N-type semiconductor layer in a patterned arrangement, and the irregular surface is formed at areas on the N-type semiconductor layer without the contact platforms. The N-type electrodes are respectively formed on the contact platforms. The contact platforms have roughness between 0.01 μm and 0.1 μm, such that not only voids are not generated but also good adhesion is provided to prevent carrier confinement and disengagement. Therefore, satisfactory electrical contact is ensured to thereby increase light emitting efficiency. | 2013-11-28 |
20130313599 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure including a substrate, a color filter layer, a conductive light-shielding layer, a buffer layer, a scan line, a data line, an active device, and a pixel electrode is provided. The substrate has a pixel region. The color filter layer is disposed corresponding to the pixel region. The conductive light-shielding layer is disposed corresponding to the periphery of the pixel region. The buffer layer covers the conductive light-shielding layer and color filter layer. The scan line and the data line are disposed on the buffer layer. The active device is disposed on the buffer layer and electrically connected to the scan line and data line. The pixel electrode is disposed on the buffer layer and electrically connected to the active device, wherein an overlapping area between the pixel electrode and the conductive light-shielding layer constitutes a storage capacitor. A method for manufacturing the pixel structure is also provided. | 2013-11-28 |
20130313600 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure including a substrate, a color filter layer, a conductive light-shielding layer, a buffer layer, a scan line, a data line, an active device, and a pixel electrode is provided. The substrate has a pixel region. The color filter layer is disposed corresponding to the pixel region. The conductive light-shielding layer is disposed corresponding to the periphery of the pixel region. The buffer layer covers the conductive light-shielding layer and color filter layer. The scan line and the data line are disposed on the buffer layer. The active device is disposed on the buffer layer and electrically connected to the scan line and data line. The pixel electrode is disposed on the buffer layer and electrically connected to the active device, wherein an overlapping area between the pixel electrode and the conductive light-shielding layer constitutes a storage capacitor. A method for manufacturing the pixel structure is also provided. | 2013-11-28 |
20130313601 | ILLUMINATION DEVICES AND METHODS FOR MAKING THE SAME - The present disclosure is generally directed to illumination devices, and methods for making the same. The device, in particular, includes a first conductor layer, a first insulator layer disposed on the first conductor layer and having at least one first aperture defined therein through the first insulator layer, a second conductor layer disposed on the first insulator layer and having at least one second aperture defined therein through the second conductor layer and positioned to align with the at least one first aperture, and a light manipulation layer disposed on the second conductor layer and having at least one pair of apertures defined therein through the light manipulation layer including a third aperture and a fourth aperture, where the third aperture is positioned to align with the at least one second and first apertures. | 2013-11-28 |
20130313602 | LIGHT EMITTING DEVICE - The light emitting device has a light emitting element | 2013-11-28 |
20130313603 | Wavelength Converter for an LED, Method of Making, and LED Containing Same - A wavelength converter for an LED is described that comprises a substrate of monocrystalline garnet having a cubic crystal structure, a first lattice parameter and an oriented crystal face. An epitaxial layer is formed directly on the oriented crystal face of the substrate. The layer is comprised of a monocrystalline garnet phosphor having a cubic crystal structure and a second lattice parameter that is different from the first lattice parameter wherein the difference between the first lattice parameter and the second lattice parameter results in a lattice mismatch within a range of ±15%. The strain induced in the phosphor layer by the lattice mismatch shifts the emission of the phosphor to longer wavelengths when a tensile strain is induced and to shorter wavelengths when a compressive strain is induced. Preferably, the wavelength converter is mounted on the light emitting surface of a blue LED to produce an LED light source. | 2013-11-28 |
20130313604 | Method for Producing a Light-Emitting Semiconductor Component and Light-Emitting Semiconductor Component - A method for producing a light-emitting semiconductor component is specified. A light-emitting semiconductor chip is arranged on a mounting area of a carrier. The semiconductor chip is electrically connected to electrical contact regions on the mounting area. An encapsulation layer is applied to the semiconductor chip by means of atomic layer deposition. All surfaces of the semiconductor chip which are free after mounting and electrical connection are covered with an encapsulation layer. Furthermore, a light-emitting semiconductor component is specified. | 2013-11-28 |
20130313605 | ELECTRODE CONTACT STRUCTURE OF LIGHT-EMITTING DIODE - A light-emitting diode (LED) electrode contact structure for an LED is provided. The LED includes a plurality of N-type electrodes, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a mirror layer, a buffer layer, a binding layer, a permanent substrate and a P-type electrode that are stacked in sequence. The N-type semiconductor layer has an irregular surface and a plurality of contact platforms. The contact platforms are formed and distributed on the N-type semiconductor layer in a patterned arrangement, and the irregular surface is formed at areas on the N-type semiconductor layer without the contact platforms. The N-type electrodes are respectively formed on the contact platforms. Through flat interfaces provided by the contact platforms, voids are not generated when the N-type electrodes are formed on the contact platforms. Therefore, satisfactory electrical contact is ensured to thereby increase light emitting efficiency. | 2013-11-28 |
20130313606 | ILLUMINATING DEVICE - An illuminating device includes a substrate, a circuit layer, a conductive structure, and at least one LED die. The circuit layer is disposed on a top surface of the substrate. The conductive structure is disposed on the top surface of the substrate and includes a graphite layer. The LED die is attached to the conductive structure and is electrically connected to the circuit layer through the conductive structure. | 2013-11-28 |
20130313607 | Silicon Controlled Rectifier With Stress-Enhanced Adjustable Trigger Voltage - Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR. | 2013-11-28 |
20130313608 | SEMICONDUCTOR DEVICE - A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array. | 2013-11-28 |
20130313609 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a nitride semiconductor device having an excellent boundary between a nitride semiconductor and a gate insulating film, resulting in improved device characteristics, and a manufacturing method therefor. The nitride semiconductor device includes: an electron transport layer made of a nitride semiconductor; an electron supply layer layered on the electron transport layer, the electron supply layer being made of a nitride semiconductor including Al and having an Al composition different from that of the electron transport layer; a source electrode and a drain electrode formed on the electron supply layer with a gap therebetween; a gate insulating film covering the surface of the electron supply layer between the source electrode and the drain electrode; a passivation film covering a surface of the gate insulating film and having an opening between the source electrode and the drain electrode; and a gate electrode having a main gate body in the opening facing the electron supply layer through the gate insulating film. | 2013-11-28 |
20130313610 | SEMICONDUCTOR DEVICE HAVING A NECKED SEMICONDUCTOR BODY AND METHOD OF FORMING SEMICONDUCTOR BODIES OF VARYING WIDTH - Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body. | 2013-11-28 |
20130313611 | A NON-UNIFORM LATERAL PROFILE OF TWO-DIMENSIONAL ELECTRON GAS CHARGE DENSITY IN TYPE III NITRIDE HEMT DEVICES USING ION IMPLANTATION THROUGH GRAY SCALE MASK - A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain. | 2013-11-28 |
20130313612 | HEMT GaN DEVICE WITH A NON-UNIFORM LATERAL TWO DIMENSIONAL ELECTRON GAS PROFILE AND METHOD OF MANUFACTURING THE SAME - A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain. A two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain. | 2013-11-28 |
20130313613 | Selectively Area Regrown III-Nitride High Electron Mobility Transistor - Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain. | 2013-11-28 |
20130313614 | METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME - The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance R | 2013-11-28 |
20130313615 | INTEGRATED CIRCUIT LAYOUT HAVING MIXED TRACK STANDARD CELL - An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer. | 2013-11-28 |
20130313616 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE - A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate. | 2013-11-28 |
20130313617 | Embedded JFETs for High Voltage Applications - A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. | 2013-11-28 |
20130313618 | FIN-JFET - Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate. | 2013-11-28 |
20130313619 | FIN FIELD-EFFECT-TRANSISTOR (FET) STRUCTURE AND MANUFACTURING METHOD - A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region, and doping top of the semiconductor substrate to form a doped layer at top surface of the semiconductor substrate over the first region and the second region. The method also includes etching the doped layer to form a first sub-fin in the first region and a first sub-fin in the second region, and forming an insulating layer over the semiconductor substrate including the first sub-fin in the first region and the first sub-fin in the second region. Further, the method includes removing top portions of the first sub-fin in the first region and the first sub-fin in the second region and forming corresponding second sub-fins. | 2013-11-28 |
20130313620 | METHOD AND STRUCTURE FOR RADIATION HARDENING A SEMICONDUCTOR DEVICE - Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity. | 2013-11-28 |
20130313621 | IMAGE PICKUP UNIT AND IMAGE PICKUP DISPLAY SYSTEM - A device for image sensing includes a photoelectric conversion unit and at least one transistor. The photoelectric conversion unit is configured to convert incident electromagnetic radiation into an electric signal. The at least one transistor includes a first gate electrode and a second gate electrode above the first gate electrode. The first gate electrode and the second gate electrode do not overlap each other within a non-overlapping region. | 2013-11-28 |
20130313622 | PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus in which each of a plurality of pixels includes a photoelectric conversion element configured to generate an electric charge by a photoelectric conversion, an impurity diffusion region, and a gate electrode configured to transfer the electric charge from the photoelectric conversion element to the impurity diffusion region. The photoelectric conversion apparatus includes a gate control line composed of a metal wiring extending in a first direction and being connected electrically to the gate electrode. Some or all of the impurity diffusion regions of the plurality of pixels are mutually connected. A read out circuit region is arranged in an outside in a second direction from a pixel arranged at a most outside among all of the plurality of pixels. A metal wiring layer arranged in a pixel array region is composed of only a single wiring layer including a plurality of wirings in the same height. | 2013-11-28 |
20130313623 | THRESHOLD GATE AND THRESHOLD LOGIC ARRAY - Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the magnetic tunnel junction element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring several Boolean gates. | 2013-11-28 |
20130313624 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first connection portion and a second connection portion connect a first control gate to a second control gate, and are separated from each other. The first control gate includes a first disconnection portion between the first connection portion and a source diffusion layer closest to the first connection portion. The second control gate includes a second disconnection portion between the second connection portion and the source diffusion layer closest to the second connection portion. A first word gate and a second word gate are not disconnected in portions overlapping the first disconnection portion and the second disconnection portion. | 2013-11-28 |
20130313625 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate and at least a first gate structure disposed on the semiconductor substrate. Furthermore, a spacer only disposed at a side of the first gate structure, and a material of the spacer does not comprise nitride. | 2013-11-28 |
20130313626 | Methods and Apparatus for Non-Volatile Memory Cells - Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells. | 2013-11-28 |
20130313627 | Multi-Level Contact to a 3D Memory Array and Method of Making - A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers. | 2013-11-28 |
20130313628 | SONOS STRUCTURE, MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR WITH THE SAME STRUCTURE - The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content. | 2013-11-28 |
20130313629 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME - A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern. | 2013-11-28 |
20130313630 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode. | 2013-11-28 |
20130313631 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING SAME - A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P—N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type. | 2013-11-28 |
20130313632 | Semiconductor Device with Voltage Compensation Structure - A voltage compensation structure includes a first semiconductor or insulating material disposed along one or more sidewalls of a trench formed in a doped epitaxial semiconductor material. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for n-type dopant atoms than p-type dopant atoms. The voltage compensation structure further includes a doped second semiconductor material disposed in the trench so that the first semiconductor or insulating material is interposed between the doped second semiconductor material and the doped epitaxial semiconductor material. The doped second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material so that a lateral charge separation occurs between the doped second semiconductor material and the doped epitaxial semiconductor material. | 2013-11-28 |
20130313633 | Semiconductor Device and Method of Forming Junction Enhanced Trench Power Mosfet having Gate Structure Embedded within Trench - A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region. | 2013-11-28 |
20130313634 | POWER SEMICONDUCTOR DEVICE AND EDGE TERMINAL STRUCTURE THEREOF - An edge terminal structure of a power semiconductor device is provided that includes a substrate, a first and a second electrodes disposed on a surface and a back of the substrate respectively, a first field plate, and a second field plate. The power semiconductor device includes an active area and an edge termination area, and there is a trench in a surface of the substrate in the edge terminal area beside the active area. The first field plate is disposed on a sidewall of the trench and extends on a tail of the trench, and it includes at least a L-shaped electric-plate, a gate insulation layer under the L-shaped electric-plate, and the first electrode on the L-shaped electric-plate. The second field plate includes at least an insulation layer and the first electrode thereon. The insulation layer covers the tail of the trench and a tail of the L-shaped electric-plate further. | 2013-11-28 |
20130313635 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention is a semiconductor device having a semiconductor layer comprising a wide band gap semiconductor, wherein the semiconductor layer includes: a first conductivity-type source region, a second conductivity-type channel region and a first conductivity-type drain region, which are formed in this order from the surface side of the semiconductor layer; a source trench lying from the surface of the semiconductor layer through the source region and the channel region to the drain region; a gate insulating film formed so as to contact the channel region; a gate electrode facing the channel region with the gate insulating film interposed therebetween; and a first breakdown voltage holding region of a second conductivity type formed selectively on the side face or the bottom face of the source trench, and the semiconductor device includes a barrier formation layer, which is joined with the drain region in the source trench, for forming, by junction with the drain region, a junction barrier lower than a diffusion potential of a body diode formed by p-n junction between the channel region and the drain region. | 2013-11-28 |
20130313636 | TERMINATION ARRANGEMENT FOR VERTICAL MOSFET - Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown. | 2013-11-28 |
20130313637 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A transistor having a source region, a drain region, a plurality of trenches extended in the longitudinal direction of a channel between the source region and the drain region and arranged in parallel in a longitudinal direction of a channel, an epitaxial layer formed on the lateral surfaces of each of the trenches, a gate oxide film covering the epitaxial layer and a gate electrode covering the gate insulating film and filled in the trenches. | 2013-11-28 |
20130313638 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p | 2013-11-28 |
20130313639 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of a second conductivity type provided on the semiconductor substrate, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a first well of the second conductivity type provided on the second semiconductor layer, a second well of the first conductivity type provided on part of the first well, a source layer of the second conductivity type provided on part of the second well and separated from the first well, a back gate layer of the first conductivity type provided on another part of the second well, and a drain layer of the second conductivity type provided on another part of the first well. The second semiconductor layer and the second well are separated from each other by the first well. | 2013-11-28 |
20130313640 | Semiconductor Device and Method of Forming Junction Enhanced Trench Power Mosfet - A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region. | 2013-11-28 |
20130313641 | DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed. | 2013-11-28 |
20130313642 | Semiconductor Device Having Gradient Doping Profile - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate over a substrate. The method includes performing a first implantation process to form a first doped region in the substrate, the first doped region being adjacent to the gate. The method includes performing a second implantation process to form a second doped region in the substrate, the second doped region being formed farther away from the gate than the first doped region, the second doped region having a higher doping concentration level than the first doped region. The method includes removing portions of the first and second doped regions to form a recess in the substrate. The method includes epitaxially growing a third doped region in the recess, the third doped region having a higher doping concentration level than the second doped region. | 2013-11-28 |
20130313643 | Structure and Method to Modulate Threshold Voltage For High-K Metal Gate Field Effect Transistors (FETs) - A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed. | 2013-11-28 |
20130313644 | SWITCHING CIRCUIT - A switching circuit comprises a first transistor and a second transistor formed in an active area of semiconductor substrate. The source and drain regions of the transistors are electrically connected to respective source wires and drain wires through a plurality of intermediate metal layers stacked above the transistor. Electrical connections between different layers are made with a plurality of vias. To improve switching performance, the intermediate wires are disposed such that intermediate wires electrically connected to the transistor source regions are not directly beneath the drain wires. Similarly, intermediate wires electrically connected to drain regions are arranged not to be directly underneath source wires. | 2013-11-28 |
20130313645 | SEMICONDUCTOR ELEMENT AND DISPLAY DEVICE USING THE SAME - A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion. | 2013-11-28 |
20130313646 | Structure and Method for Fabricating Fin Devices - A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes. | 2013-11-28 |
20130313647 | FORMING FACET-LESS EPITAXY WITH A CUT MASK - A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer. | 2013-11-28 |
20130313648 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF - A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench. | 2013-11-28 |
20130313649 | FIN ISOLATION FOR MULTIGATE TRANSISTORS - Multigate transistor devices and methods of their fabrication are disclosed. One such device includes a plurality of semiconductor fins that have source and drain regions and a gate structure overlaying the fins. The device further includes a dielectric layer that is beneath the gate structure and the fins. Here, the dielectric layer includes first dielectric regions that are disposed beneath the fins and second dielectric regions that are disposed between the fins. In addition, the first dielectric regions have a density that is greater than a density of the second dielectric regions. | 2013-11-28 |
20130313650 | TID HARDENED MOS TRANSISTORS AND FABRICATION PROCESS - A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. | 2013-11-28 |