48th week of 2009 patent applcation highlights part 47 |
Patent application number | Title | Published |
20090292842 | Data access device with wireless network application service - A data access device with a wireless network application service includes a microprocessing unit, a wireless network module, and a memory unit, and the data access device is connected to a main system through a USB interface. The memory unit includes two memory blocks, and the first memory block is provided for the device to access data and includes a wireless network module driver program and a network service software for connecting a network service, and the second memory block is provided for the main system to access data and the data downloaded from a network service by the network service software. | 2009-11-26 |
20090292843 | Controlling passthrough of communications between multiple buses - A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus. | 2009-11-26 |
20090292844 | Multiprocessor gateway - A multiprocessor gateway for multiple serial buses includes: multiple communication modules that are each provided for connection of one serial bus; multiple processors for processing data that are transferred in word-based fashion, via an internal system bus appurtenant to the respective processor, between the processor and the communication modules, the internal system buses of the multiprocessor gateway being connected to the communication modules, which have a respective appurtenant interface unit for each system bus, each processor exchanging data, via its appurtenant system bus and the interface unit, appurtenant to the system bus, of a communication module, with the serial bus connected to the communication module, independently of the other processors and without waiting time. | 2009-11-26 |
20090292845 | Communication System Having a Master/Slave Structure - A communication system comprising a master unit and a plurality of slave units. In error mode, e.g. when a path error or a complete failure of a subscriber occurs, data transmission is carried out in a loop, starting from the master unit, via a first communication path and a second communication path. | 2009-11-26 |
20090292846 | METHOD OF INTERRUPT SCHEDULING - There is provided a method of interrupt scheduling. The method comprises: without allowing a target process woken up when an interrupt occurs to enter into a ready queue, directly comparing the priority of the woken-up target process with that of a current process performed before the occurrence of the interrupt, and executing a rescheduling in accordance with the compared result; and performing direct context switching with respect to the current process into the target process in accordance with whether or not the rescheduling is executed. Accordingly, in the method of interrupt scheduling, the preemption latency caused by the interrupt in the operating system of the computer system can be minimized by omitting the process of allowing the woken-up target process to enter into the ready queue and the process of selecting a process with the highest priority on the ready queue. | 2009-11-26 |
20090292847 | MICROPROCESSOR APPARATUS PROVIDING FOR SECURE INTERRUPTS AND EXCEPTIONS - An apparatus for executing secure code, having a microprocessor coupled to a secure non-volatile memory via a private bus a system memory via a system bus. The microprocessor executes non-secure application programs and a secure application program. The microprocessor accomplishes private bus transactions over the private bus to access the secure application program within the secure non-volatile memory. The private bus transactions are hidden from system bus resources and devices coupled to the system bus. The microprocessor includes normal interrupt logic and secure execution mode interrupt logic. The normal interrupt logic provides non-secure interrupts for interrupting the non-secure application programs when the microprocessor is operating in a non-secure mode. The secure execution mode interrupt logic provides secure interrupts when the microprocessor is operating in a secure mode, where the secure execution mode interrupt logic cannot be observed or accessed by the system bus resources or the non-secure application programs. | 2009-11-26 |
20090292848 | Method and Apparatus for an Electric Meter - An improved meter and its operation is described. The meter can be a part of a larger automated meter reading process that allows for remote reading of the meter though power line communication. Using a microcomputer core, the meter processes incoming analog data and can calculate several relevant data values need by utility providers. The meter can also be used to monitor and detect tampering dry connect/voltage free devices, such as gas and water meters, connected to the meter. | 2009-11-26 |
20090292849 | ADAPTABLE PCI EXPRESS CONTROLLER CORE - A controller core for controlling communication of Peripheral Component Interconnect (PCI) Express, the controller core comprises: a standard configuration register unit, a capabilities register unit, a logic unit and a bond option signal. The standard configuration register unit is configured for controlling the communication of the PCI-E, and supporting the controller core been embedded internally and accessible from exterior. The logic unit applied to associate with the standard configuration register unit and the capabilities register unit for identifying a hot insertion and removal from exterior of the controller core; and the bond option signal is used to enable and disenable the standard configuration register unit, the capabilities register unit, and the logic unit respectively. | 2009-11-26 |
20090292850 | File System Adapter for Hardware Implementation or Acceleration of File System Functions - A file system adapter card that may be plugged into a host computer system for providing hardware-based file system accesses outside the purview of a host operating system running on the host computer system. The file system adapter card includes a hardware-implemented or hardware-accelerated file service subsystem and a computer bus that permits a host computer system to communicate directly with the file service subsystem for providing file service requests and receiving file service responses. The file service subsystem includes dedicated hardware that operates outside the immediate control of a host operating system, including specialized circuitry for performing at least one major subsystem function. | 2009-11-26 |
20090292851 | DOCKING STATION FOR PORTABLE ELECTRONIC DEVICES - A docking station apparatus interfaces a portable electronic device with one or more electrical systems of a vehicle. The apparatus includes a docking assembly having an internal cavity and configured to hold the electronic device, and a mechanical interface in the cavity and configured to provide a wired or wireless connection to the electronic device. A power supply conversion circuit translates vehicle power levels to electronic device power levels, and one or more support circuits or connectors provide different connectivity functions for the electronic device. The support circuits or connectors can include input audio/video connectors in the docking assembly to provide analog audio/video signals to an analog distribution hub; an audio/video encoder and digital data connectors to provide digitally encoded audio/video signals in a wired or wireless mode to a digital distribution hub; multiplexing circuitry to accept analog audio, composite video, or component video for multiplexing between externally supplied audio/video and locally generated audio/video; and a command and control circuit to provide command and control data, and navigation data, to the electronic device in a wired or wireless mode. | 2009-11-26 |
20090292852 | Hard drive pod docking system - The invention relates to a hard drive dock (HDD) including a HDD enclosure having a first HDD outer surface and a second HDD outer surface. Each of the first HDD outer surface and the second HDD outer surface have disposed within an electrical connector configured to electrically connect to a releasably attached hard drive pod (HDP). The HDD includes a bridge circuit disposed within the HDD enclosure. The bridge circuit is configured to provide a communicative interface between the releasably attached HDP and the computer data bus connection. The HDD is mechanically configured to accept a releasably attached hard drive pod (HDP) on either or both of the first HDD surface and the second HDD surface. The invention also relates to a HDD enclosure having two or more HDD outer surfaces. The invention also relates to a releasably attached hard drive pod. | 2009-11-26 |
20090292853 | APPARATUS AND METHOD FOR PRECLUDING EXECUTION OF CERTAIN INSTRUCTIONS IN A SECURE EXECUTION MODE MICROPROCESSOR - An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292854 | USE OF BOND OPTION TO ALTERNATE BETWEEN PCI CONFIGURATION SPACE - An adaptor for adapting one of a first device complying with a first bus, and a second device complying with a second bus to a Peripheral Component Interconnect Express (PCIe) interface. The adaptor comprises a first bridge for interconnecting the first bus with the PCIe bus, a second bridge for interconnecting the second bus with the PCIe bus, and a PCIe core coupled to the two bridges. A bond option signal is coupled to the two bridges and the PCIe core for enabling one of the two bridges, and one of the two bridges is configured by the PCIe core. | 2009-11-26 |
20090292855 | HIGH-RADIX INTERPROCESSOR COMMUNICATIONS SYSTEM AND METHOD - A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n×p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port. | 2009-11-26 |
20090292856 | INTERSERVER COMMUNICATION MECHANISM AND COMPUTER SYSTEM - An interserver communication mechanism which can eliminate the need for preparing an external I/O device for each of physical servers for communication between the physical servers and can avoid generation of overhead caused by protocol conversion. A plurality of physical servers are connected to the interserver communication mechanism via I/O link and I/O switch. The interserver communication mechanism has a read instruction generator for issuing an instruction to access data of the physical servers and a write instruction generator for transmitting the read data to the other server. Data transfer between the physical servers is carried out in the interior of the interserver communication mechanism by reading out data from a data transmission originator, writing the read data to a transmission destination as it is, and directly turning back the data at the interserver communication mechanism. | 2009-11-26 |
20090292857 | CACHE MEMORY UNIT - A cache memory unit temporarily stores data having been stored in a main memory, the valid bits of the flag memory corresponding to the lines of the entries at the to-be-invalidated entry addresses are rewritten so as to indicate invalidation of the lines of the entries at the to-be-invalidated entry addresses, so that the lines of the entries at the to-be-invalidated entry addresses are invalidated. | 2009-11-26 |
20090292858 | Distributed Virtual Switch for Virtualized Computer Systems - A method for persisting a state of a virtual port in a virtualized computer system is described. A distributed virtual port (DVport) is stored in a persistent storage location, the DVport comprising a state of a corresponding virtual port and configuration settings of the virtual port. In addition, an association between the virtual port and the virtual network interface card (VNIC) connected to the virtual port is stored. When a virtual machine corresponding to the VNIC is restarted, the state from the DVport is restored to a new virtual port from the persistent storage location. | 2009-11-26 |
20090292859 | INTEGRATED STORAGE DEVICE AND CONTROL METHOD THEREOF - An integrated storage device and a control method thereof are provided. The integrated storage device includes an interface controller, a microcontroller, a plurality of non-volatile storage devices, and a channel link controller. The interface controller retrieves a master control signal and a slave control signal sent by a motherboard. The microcontroller generates a selecting signal. The non-volatile storage devices have at least two storage types. The non-volatile storage devices are divided into a first group of storage device and a second group of storage device according to the selecting signal. The channel link controller respectively controls the first group of storage device and the second group of storage device according to the master control signal and the slave control signal. Thereby, the accessing efficiency of the integrated storage device is increased. | 2009-11-26 |
20090292860 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - The present invention relates to a method of programming a non-volatile memory device. A method of programming an non-volatile memory device in accordance with an aspect of the present invention includes inputting n page of data, storing a single page of data in each of page buffer units of a plurality of memory cell units, programming a first page of data stored in a page buffer unit of a first memory cell unit, transferring a second page of data, stored in a page buffer unit of a second memory cell unit, to the page buffer unit of the first memory cell unit, and programming the transferred second page of data into the first memory cell unit. | 2009-11-26 |
20090292861 | USE OF RDMA TO ACCESS NON-VOLATILE SOLID-STATE MEMORY IN A NETWORK STORAGE SYSTEM - A network storage controller uses a non-volatile solid-state memory (NVSSM) subsystem which includes raw flash memory as stable storage for data, and uses remote direct memory access (RDMA) to access the NVSSM subsystem, including to access the flash memory. Storage of data in the NVSSM subsystem is controlled by an external storage operating system in the storage controller. The storage operating system uses scatter-gather lists to specify the RDMA read and write operations. Multiple client-initiated reads or writes can be combined in the storage controller into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory. | 2009-11-26 |
20090292862 | FLASH MEMORY MODULE AND STORAGE SYSTEM - A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller. | 2009-11-26 |
20090292863 | MEMORY SYSTEM WITH A SEMICONDUCTOR MEMORY DEVICE - A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device. | 2009-11-26 |
20090292864 | IDENTIFICATION INFORMATION MANAGEMENT SYSTEM AND METHOD FOR MICROCOMPUTER - An exemplary object of the present invention is to facilitate the management of identification information in a microcomputer having a flash memory. A system | 2009-11-26 |
20090292865 | SYSTEMS AND METHODS FOR SCHEDULING A MEMORY COMMAND FOR EXECUTION BASED ON A HISTORY OF PREVIOUSLY EXECUTED MEMORY COMMANDS - A memory system is operated by maintaining a queue of memory commands to be executed, maintaining a list of previously executed memory commands, comparing local information associated with the commands to be executed with local information associated with the list of previously executed commands, and selecting one of the commands for execution from the queue of memory commands to be executed based on a result of the comparison. | 2009-11-26 |
20090292866 | DISK APPARATUS AND COMMAND PROCESSING METHOD - A control unit in a disk apparatus stores a command in a queue. When the execution of the command stored in the queue is not completed within a predetermined time, the control unit stores an LBA corresponding to a command which is executed within the predetermined time and during execution of which the disk retry is generated more than a predetermined number of times, as a monitoring object LBA in a monitoring object LBA management table. Further, when an LBA corresponding to an execution object command corresponds to the monitoring object LBA stored in the monitoring object LBA management table, the control unit rearranges the command in the position at the end of the queue. | 2009-11-26 |
20090292867 | Storage-apparatus, disk controller, and command issue control method - The storage apparatus of the present invention includes a disk controller (CM) that issues a command to a disk via a fabric device. The CM controls the number of commands to be issued to the disk based on the structure of the storage apparatus and the operation state of the storage apparatus. | 2009-11-26 |
20090292868 | DISK CONTROL UNIT AND STORAGE SYSTEM - Provided is a disk controller comprising a front end FC I/F to a host, a back end FC I/F to a magnetic disk, a processor, and a main memory section. The front end I/F and the back end I/F are provided for performing information exchange with a network (connected) device that is connected to a network and manages storage. The main memory section stores registered information expressing an attribution of the network (connected) device, access information including security and performance of each network (connected) device through the network, and ranking information assigning a rank to each network (connected) device based on the registered information and the access information. An appropriate network (connected) device is selected from various types of information including the ranking information. | 2009-11-26 |
20090292869 | DATA DELIVERY SYSTEMS - A request for a multi-segment, sequential data file is received from a user. At least a portion of a first segment of the multi-segment, sequential data file is provided from a previously-energized first storage device to the user. A previously-unenergized second storage device that contains a second segment of the multi-segment, sequential data file is energized. | 2009-11-26 |
20090292870 | STORAGE APPARATUS AND CONTROL METHOD THEREOF - With this storage apparatus and its control method for presenting multiple virtual volumes to a host apparatus and dynamically allocating to each of the multiple virtual volumes a physical storage area for storing data according to the usage status of each of the multiple virtual volumes, the importance set to each of the multiple virtual volumes is managed, and a storage area is dynamically allocated to each of the multiple virtual volumes. Here, upon dynamically allocating the storage area to each of the multiple virtual volumes, a storage area provided by a plurality of memory apparatus groups respectively configured from a plurality of memory apparatuses is allocated to one or more virtual volumes with low importance among the multiple virtual volumes, and a storage area provided by one of the memory apparatus groups is allocated to other virtual volumes among the multiple virtual volumes. | 2009-11-26 |
20090292871 | STORAGE CONTROLLER, AND METHOD OF CONTROLLING STORAGE CONTROLLER TO IMPROVE THE RELIABILITY OF THE STORAGE CONTROLLER - The present invention controls supply of power to a storage device on the basis of an access status, moves a logical storage device between physical storage devices having different power supply modes, reduces energization time, and improves the reliability. A relocation plan creation portion creates a relocation plan by disposing a logical volume with high access frequency in a RAID group which is in a long-time energization mode, disposing a logical volume with moderate access frequency in a RAID group which is in a first short-time energization mode, and disposing a logical volume with low access frequency in a RAID group which is in a second short-time energization mode. An execution time determination portion determines an execution time for executing the relocation plan, on the basis of the access frequency to the RAID groups. The volumes with higher access frequency are disposed in the RAID group in which the power supply time is long, and the volumes with lower access frequency are disposed in the RAID group in which the power is supplied in an on-demand fashion. | 2009-11-26 |
20090292872 | Method and device for controlling disk array apparatus - A method for controlling a disk array apparatus includes: assigning serial addresses to all addresses of multiple disk drives of the disk array apparatus in an order of disk drive; equally separating the serial addresses into a first disk group having first serial addresses in an increasing order and a second disk group having second serial addresses in the increasing order; and writing data in the first disk group at one of the first serial addresses and in the second disk group at a corresponding one of the second serial addresses, said corresponding one of the second serial addresses being obtained by adding a maximum serial address out of the first serial addresses of the first disk group to said one of the first serial addresses. | 2009-11-26 |
20090292873 | DISK ARRAY APPARATUS, METHOD FOR APPLICATION OF CONTROL FIRMWARE, AND CONTROLLING UNIT FOR CONTROLLING APPLICATION OF CONTROL FIRMWARE - A disk array apparatus with a number of storage units aims at application of new control firmware to the storage units. The disk array apparatus includes a controlling unit controlling the storage units, which controlling unit includes a storing section storing control firmware to be applied; a monitoring section for monitoring a state of access to each storage unit to which the control firmware is to be applied; and an application instructing section instructing, on the basis of the result of the monitoring by the monitoring section, each the first storage unit to apply the first control firmware. In response to the instructing by the application instructing section, the control firmware is applied to each the storage unit. | 2009-11-26 |
20090292874 | VIRTUAL PATH STORAGE SYSTEM AND CONTROL METHOD FOR THE SAME - Provided is a storage system having improved access performance. The storage system includes: a hard disk drive, and a storage controller for reading/writing data from/to the hard disk drive, the storage controller including: at least one interface connected to a host computer through a network; and a plurality of processors connected to the interface through an internal network. The storage system is characterized in that: the processor provides at least one logical access port to the host computer; and the interface stores routing information including a processor which processes an access request addressed to the logical access port, extracts an address from the received access request upon reception of the access request from the host computer, specifies the processor which processes the received access request based on the routing information and the extracted address, and transfers the received access request to the specified processor. | 2009-11-26 |
20090292875 | DISK ARRAY CONTROLLER CAPABLE OF DETECTING AND CORRECTING FOR UNEXPECTED DISK DRIVE POWER-ON-RESET EVENTS - A disk array controller detects disk drive power-on-reset events that may cause a disk drive to lose uncommitted write data stored in its cache. When an unexpected disk drive power-on-reset event is detected, the disk array controller may initiate an appropriate corrective action. For example, the disk array controller may initiate a disk drive rebuild operation, or may re-send a set of write commands to the disk drive. | 2009-11-26 |
20090292876 | In-System Programming to Switch Memory Access from One Area to Another in Memory Cards - In-system programming to switch memory access from one area to another in memory cards is disclosed. A command to access a first area of a memory card is received. Access is switched from the first area of the memory card to a second area of the memory card if specified data follows the received command allowing for the memory access switch. | 2009-11-26 |
20090292877 | EVENT SERVER USING CACHING - An event server adapted to receive events from an input stream and produce an output event stream. The event server uses a processor using code in an event processing language to process the events. The event server obtaining input events from and/or producing output events to a cache. | 2009-11-26 |
20090292878 | METHOD AND SYSTEM FOR PROVIDING DIGITAL RIGHTS MANAGEMENT FILES USING CACHING - A method for providing DRM files using caching includes identifying DRM files to be displayed in a file list in response to a request, decoding a number of first DRM files from among the identified DRM files and caching the first DRM files in a first memory space, and reading the first DRM files in the first memory space in response to the request. Then, a system displays the first DRM files as a file list in a display area. The second DRM files from among the identified DRM files other than the first DRM files are not initially decoded, and file data related to the second DRM files are cached in a second memory space. DRM files from among the second DRM files are subsequently decoded in response to a subsequent command. | 2009-11-26 |
20090292879 | Nodma cache - A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory. | 2009-11-26 |
20090292880 | CACHE MEMORY SYSTEM - A cache memory system controlled by an arbiter includes a memory unit having a cache memory whose capacity is changeable, and an invalidation processing unit that requests invalidation of data stored at a position where invalidation is performed when the capacity of the cache memory is changed in accordance with a change instruction. The invalidation processing unit includes an increasing/reducing processing unit that sets an index to be invalidated in accordance with a capacity before change and a capacity after change and requests the arbiter to invalidate the set index, and an index converter that selects either an index based on the capacity before change or an index based on the capacity after change associated with an access address from the arbiter, and the capacity of the cache memory can be changed while maintaining the number of ways of the cache memory. | 2009-11-26 |
20090292881 | DISTRIBUTED HOME-NODE HUB - A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches. | 2009-11-26 |
20090292882 | STORAGE AREA NETWORK SERVER WITH PARALLEL PROCESSING CACHE AND ACCESS METHOD THEREOF - A storage area network (SAN) server with a parallel processing cache and an access method thereof are described, which are supplied for a plurality of request to access data in a server through an SAN. The server includes physical storage devices, for storing data sent by the request and data transmitted to the request; copy managers, for managing the physical storage devices connected to the server, and each copy manager includes a cache memory unit, for temporarily storing the data accessed by the physical storage devices, and a data manager, for recording an index of the data in the cache memory unit, providing a cache copy stored in the cache memory unit to a corresponding request end, and confirming an access time for each virtual device manager to access the cache copy. | 2009-11-26 |
20090292883 | Apparatus, Method, and Computer Program Product for Memory Validation Operations in a Memory - In accordance with an example embodiment of the present invention, an apparatus, comprising a first memory, wherein the first memory is configured to store data related to a first event, store a memory validation indicator related to a second event, and a second memory, wherein the second memory is configured to store a memory validation indicator related to the first event, wherein the first memory validation is based at least in part on the second memory validation indicator. | 2009-11-26 |
20090292884 | SYSTEM ENABLING TRANSACTIONAL MEMORY AND PREDICTION-BASED TRANSACTION EXECUTION METHOD - This invention provides a system enabling Transactional Memory with overflow prediction mechanism, comprising: prediction unit for predicting the mode for the next execution of a transaction based on the final status of the previous execution of the transaction; execution unit for executing the transaction in the execution mode predicted by the prediction unit, wherein the execution mode comprises overflow mode and non-overflow made. According to this invention, before a transaction is executed, it is predicted whether or not the transaction will overflow, and therefore, the execution of the transaction which is necessary to determine whether or not an overflow will occur is saved and the system performance can be improved. | 2009-11-26 |
20090292885 | METHOD AND APPARATUS FOR PROVIDING ATOMIC ACCESS TO MEMORY - Apparatus for controlling atomic access to a memory includes an access request evaluator for receiving an atomic access request to an address in the memory from a client and determining whether to allow atomic access to the requested address. An access indicator indicates whether a select address is currently under atomic access in the memory, and an access release indicates whether the atomic access is completed at the select address. The access request evaluator enables the client atomic access to the requested address if the access indicator indicates that the requested address is currently not under atomic access. | 2009-11-26 |
20090292886 | REACTIVE PLACEMENT CONTROLLER FOR INTERFACING WITH BANKED MEMORY STORAGE - An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue. | 2009-11-26 |
20090292887 | METHOD AND APPARATUS FOR PRESERVING MEMORY CONTENTS DURING A POWER OUTAGE - A method and apparatus for preserving contents of a volatile memory when a main (e.g., AC) power source is disconnected. The apparatus comprises flash memory, a controller for writing to the flash memory and a temporary power source. The temporary power source may be a relatively low power battery or supercapacitor. The apparatus is removably attached to a computing device (e.g., via a USB port). When main power of the device is disconnected, the temporary power source provides power for the apparatus, the volatile memory containing data to be safeguarded, and sufficient processing resources to transfer the data. For example, an auxiliary processor may be powered (instead of a relatively high-power processor) or just one core of a multi-core processor. Data are written to the apparatus and can be recovered when main power is reconnected. Or, the apparatus may be detached and attached to a different device for data recovery. | 2009-11-26 |
20090292888 | Backing up Data from Backup Target to Backup Facility - Aspects of the subject matter described herein relate to backup up data. In aspects, a backup target determines a degree to which a data set included on the backup target is not backed up on a backup facility. The degree can represent more than just that the data set is completely backed up or is not backed up at all. If the degree satisfies a condition, the backup target utilizes information derived from a backup history of one or more attempted or successfully completed backup sessions between the backup target and the backup facility to determine whether to provide a notification regarding backup state. The backup target also may send the degree and other backup information to a backup facility which may use this information in determining a backup scheme to employ with the backup target. | 2009-11-26 |
20090292889 | Automated backup and reversion system - An automated backup and reversion system comprising at least two storage systems with one source storage system being physically connected to at least one host system during normal processing at any given time. During the backup process, involved storage devices are physically disconnected from the host system. The at least one destination storage system receiving the information backup may thereafter be connected to the host system to allow for subsequent host processing. The initial source storage system may then remain disconnected from the host system and assume the role of a destination storage system. Each storage system is located at the same logical location while being processed so that the host system is unaware that any storage system change has occurred. A plurality of storage systems may be configured with only one being processed at any given time, and the remainder may comprise successive backups after any negative event. | 2009-11-26 |
20090292890 | SYSTEM AND METHOD FOR IMPROVED SNAPCLONE PERFORMANCE IN A VIRTUALIZED STORAGE SYSTEM - A system and method of creating a snapclone for on-line point-in-time complete backup in a virtualized storage system is disclosed. In one embodiment, a method for creating a snapclone for on-line point-in-time complete backup in a virtualized storage system includes receiving a copy operation directed to one or more identified segments of an original virtual disk, in response to the copy operation, substantially sequentially copying the one or more identified segments to a snapclone virtual disk, clearing bits in an in-memory sharing bitmap associated with already copied one or more identified segments, and writing the cleared bits in the in-memory sharing bitmap to a disk resident virtual disk metadata associated with the snapclone virtual disk upon receiving a current write I/O operation while the copy operation is in progress. The received current write I/O operation is targeting data outside the LBA range of the already copied one or more identified segments. | 2009-11-26 |
20090292891 | MEMORY-MIRRORING CONTROL APPARATUS AND MEMORY-MIRRORING CONTROL METHOD - When an update instruction for updating task data stored in a memory is transmitted through a transaction process performed by an application server, an active node apparatus generates, based on the update instruction, an update log indicating update contents of the task data stored in the memory, and then distributes, in a multicast manner, the generated update log to other standby node apparatuses each with a memory. With this, mirroring among the plurality of memories is controlled. | 2009-11-26 |
20090292892 | Method to Reduce Power Consumption of a Register File with Multi SMT Support - A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system. | 2009-11-26 |
20090292893 | MICROPROCESSOR HAVING SECURE NON-VOLATILE STORAGE ACCESS - An apparatus providing for a secure execution environment. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292894 | MICROPROCESSOR HAVING INTERNAL SECURE MEMORY - An apparatus providing for a secure execution environment. The apparatus includes a microprocessor that is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-secure memory and a secure volatile memory. The non-secure memory is configured to store portions of the non-secure application programs for execution by the microprocessor, where the non-secure memory is observable and accessible by the non-secure application programs and by system bus resources within the microprocessor. The secure volatile memory is configured to store the secure application program for execution by the microprocessor, where the secure volatile memory is isolated from the non-secure application programs and the system bus resources within the microprocessor. | 2009-11-26 |
20090292895 | MANAGING SERVER, POOL ADDING METHOD AND COMPUTER SYSTEM - In a computer system, even when the virtual storage capacity of pools is increased, it is possible to keep the availability of each pool at least at a desired level. The managing server compares a reference value beforehand stored therein with an evaluation value of availability which represents a degree of resistivity against destruction, the degree being derived by use of physical configuration information which is obtained from the controller and which is associated with the pool; and determines necessity of addition of an element to the pool if the availability evaluation value exceeds the reference value and indicates the addition of the element to the pool to the storage apparatus. | 2009-11-26 |
20090292896 | INFORMATION MANAGEMENT METHOD, RECORDING/PLAYBACK APPARATUS, AND INFORMATION STORAGE MEDIUM - In an information management method according to an embodiment of the invention, one or more freely installable memory cards are used. A suitable information management can be made even if a part or all of the memory cards is/are optionally attached or detached. Digital AV information of which recording may be distributed over the one or more memory cards is managed according to a prescribed format (which is common to all of the memory cards). Identification information for identifying the card is recorded on each of the memory cards. Allocation information (FAT) indicating where is allocated a portion of the digital AV information is also recorded on each of the memory cards. The allocation information of each of the memory cards identified by the identification information is acquired, and the acquired allocation information is integrated. The acquisition and integration are performed each time the memory card is attached or detached. | 2009-11-26 |
20090292897 | DEGENERATION METHOD AND INFORMATION PROCESSING APPARATUS - By including detecting an abnormality in a first system common unit; reading a priority indication, from the storage portion, indicating whether or not the first system common unit is to be degenerated when an abnormality occurs in the first system common unit for each of the partitioned portions; carrying out, when an abnormality is detected in a partitioned portion to which the priority indication is set, suspend processing on the information processing apparatus by the system control portion on the partitioned portion; and carrying out degeneration processing for suspending operation of the first system common unit and switching to the second system common unit, quick recovery is achieved when a significant partition is down due to a fault experienced in a common unit. | 2009-11-26 |
20090292898 | PROCESSOR WITH ADDRESS GENERATOR - A processor for processing data is provided. The processor comprises an address generator, which is operative to generate an address based on a base address and a fractional step (Δ). | 2009-11-26 |
20090292899 | Data processing apparatus and method for handling address translation for access requests issued by processing circuitry - A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, whilst also allowing certain problem cases to be handled correctly and in an efficient manner. | 2009-11-26 |
20090292900 | MULTIPROCESSOR NODE CONTROL TREE - Control messages are sent from a control processor to a plurality of attached processors via a control tree structure comprising the plurality of attached processors and branching from the control processor, such that two or more of the plurality of attached processor nodes are operable to send messages to other attached processor nodes in parallel. | 2009-11-26 |
20090292901 | MICROPROCESSOR APPARATUS AND METHOD FOR PERSISTENT ENABLEMENT OF A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The secure application program is executed exclusively within a secure execution mode within the microprocessor. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292902 | APPARATUS AND METHOD FOR MANAGING A MICROPROCESSOR PROVIDING FOR A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus. The secure application program executes in a secure execution mode. The microprocessor has secure execution mode logic that monitors conditions corresponding to the microprocessor associated with tampering, and causes the microprocessor to transition to a degraded operating mode from the secure execution mode following detection of a first one or more of the conditions. The degraded operating mode exclusively provides for execution of BIOS instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, stores the secure application program. Transactions over the private bus are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292903 | MICROPROCESSOR PROVIDING ISOLATED TIMERS AND COUNTERS FOR EXECUTION OF SECURE CODE - An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The a microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a plurality of timers which are visible and accessible only by the secure application program when executing in a secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292904 | APPARATUS AND METHOD FOR DISABLING A MICROPROCESSOR THAT PROVIDES FOR A SECURE EXECUTION MODE - An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure watchdog logic that monitors environmental attributes corresponding to the microprocessor and to the secure application program, and that is configured to transfer program control to one of a plurality of event handlers within the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292905 | Performing An Allreduce Operation On A Plurality Of Compute Nodes Of A Parallel Computer - Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer, each node including at least two processing cores, that include: performing, for each node, a local reduction operation using allreduce contribution data for the cores of that node, yielding, for each node, a local reduction result for one or more representative cores for that node; establishing one or more logical rings among the nodes, each logical ring including only one of the representative cores from each node; performing, for each logical ring, a global allreduce operation using the local reduction result for the representative cores included in that logical ring, yielding a global allreduce result for each representative core included in that logical ring; and performing, for each node, a local broadcast operation using the global allreduce results for each representative core on that node. | 2009-11-26 |
20090292906 | Multi-Mode Register File For Use In Branch Prediction - A multi-mode register file is described. In one embodiment, the multi-mode register file includes an operand in a first mode. The multi-mode register file further includes auxiliary information which replaces the operand in a second mode. | 2009-11-26 |
20090292907 | Dynamic Merging of Pipeline Stages in an Execution Pipeline to Reduce Power Consumption - A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance. | 2009-11-26 |
20090292908 | Method and arrangements for multipath instruction processing - A system is disclosed that includes a fetch stage to retrieve an instruction to be utilized by processing units in a multi-path pipeline. The instruction can have selectors that can select functions to be performed by individual paths of the pipeline that can accept and utilize the same instruction. A first processing unit in a first path can execute a part of the retrieved instruction in response to the function selector, and a second processing unit can execute a part of the retrieved instruction in response to the function selector. Other embodiments are also disclosed. | 2009-11-26 |
20090292909 | Methods for initial bootstrap of user terminals in network - Methods and devices for initial bootstrap of a user terminal are provided. The user terminal transmits at least one first message to an initial bootstrap server. The first message includes device management capability information for the user terminal. The initial bootstrap server selects a device management protocol to be used by the user terminal and sends the selected device management protocol to the user terminal in at least one second message. | 2009-11-26 |
20090292910 | SYSTEM AND METHOD OF ACCESSING BIOS CHANGE SUMMARY INFORMATION WITHIN A BIOS OPERATING ENVIRONMENT - A system and method of accessing basic input output system (BIOS) change summary information within a BIOS operating environment is disclosed. According to an aspect, a basic input output system (BIOS) set-up interface is disclosed. The BIOS set-up interface includes a navigation routine accessible via a BIOS set-up menu and operable to initiate displaying a secondary user display interface. The BIOS set-up interface further includes a BIOS change summary interface accessible using the secondary display user interface and configured to display BIOS set-up changes made using the BIOS set-up menu. | 2009-11-26 |
20090292911 | Boot test system and method thereof - A boot test system applied to test a cold boot in a target computer is provided. The boot test system includes a host computer and an autorun module. The host computer is used to test the target computer to turn power on/off and output a power-on signal and a power-off signal to the target computer based on a feedback signal. The autorun module installed in the target computer is used to output the feedback signal to the host computer during the boot of the target computer. Whereby, the present invention retains a fail result of the boot of the target computer for debugging by a worker. | 2009-11-26 |
20090292912 | STORAGE MEDIUM STORING MASTER BOOT RECORD, COMPUTER SYSTEM HAVING THE SAME AND BOOTING METHOD OF THE COMPUTER SYSTEM - A storage medium storing a master boot record, a computer system having the same, and a booting method of the computer system, the storage medium including: a first sector to store a first master boot record including an execution code for grasping command information and implementing a preset control according to the command information; a first data storage region to store a first data file for booting; a second sector to store a second master boot record to implement booting based on the first data file; a second data storage region to store a second data file for booting; and a third sector to store a third master boot record to implement booting based on the second data file. | 2009-11-26 |
20090292913 | APPARATUS AND METHOD FOR COUNTER-BASED COMMUNICATIONS IN WIRELESS SENSOR NETWORKS AND OTHER NETWORKS - A method includes wirelessly receiving a message at a receiving node. The method also includes extracting a partial counter value from the message, where the partial counter value represents a subset of bits from a complete counter value of a transmitting node. The method further includes decrypting and authenticating the message based on the partial counter value. Decrypting and authenticating the message could include examining a bitmap to identify a bit value associated with the partial counter value, decrypting and authenticating the message if the identified bit value has a first value, and discarding the message if the identified bit value has a second value. Decrypting and authenticating the message could also include identifying at least one complete counter value at the receiving node based on the partial counter value and attempting to decrypt and authenticate the message using the at least one complete counter value. | 2009-11-26 |
20090292914 | NODES AND SYSTEMS AND METHODS FOR DISTRIBUTING GROUP KEY CONTROL MESSAGE - Nodes, systems and methods for distributing a group key control message are disclosed. The system mainly includes a root node and child nodes. The apparatus includes a distribution tree establishment node. The method mainly includes: establishing a distribution tree for the group key control message in the group key management system, a root node delivering the group key control message to the child nodes according to the distribution tree; the child nodes receiving the group key control message delivered from the root node, forwarding or locally processing the received group key control message. With the present disclosure, a replication/distribution mechanism for the group key control message is established within the group key management system, thereby eliminating the dependence of the group key management system on the deployed environment multicast service, and improving the availability and expansibility of the group key management system. | 2009-11-26 |
20090292915 | NETWORK SYSTEM AND DEVICE SETTING METHOD OF NETWORK SYSTEM - Disclosed is a network system including: a provisioning server to provide setting information to a device newly connected to a network; and a mediating device to mediate information transmission between the device newly connected to the network and other device, wherein the mediating device includes: a communication function to communicate with the device newly connected to the network; an access control function to restrict access to the other device to a certain amount or less; and a data transfer function to transfer data, and when there is a transfer request of the setting information from the device newly connected to the network, the mediating device sends the transfer request to the provisioning server by restricted access based on the access control function, and when the setting information is sent from the provisioning server, the mediating device transfers the setting information to the device newly connected to the network. | 2009-11-26 |
20090292916 | Certificate Management and Transfer System and Method - A method and system for Certificate management and transfer between messaging clients are disclosed. When communications are established between a first messaging client and a second messaging client, one or more Certificates stored on the first messaging client may be selected and transferred to the second messaging client. Messaging clients may thereby share Certificates. Certificate management functions such as Certificate deletions, Certificate updates and Certificate status checks may also be provided. | 2009-11-26 |
20090292917 | SECURE TRANSPORT OF MULTICAST TRAFFIC - Secure tunneled multicast transmission and reception through a network is provided. A join request may be received from a second tunnel endpoint, the join request indicating a multicast group to be joined. Group keys may be transmitted to the second tunnel endpoint, where the group keys are based at least on the multicast group. A packet received at the first tunnel endpoint may be cryptographically processed to generate an encapsulated payload. A header may be appended to the encapsulated payload to form an encapsulated packet, wherein the header includes information associated with the second tunnel endpoint. A tunnel may be established between the first tunnel endpoint and the second tunnel endpoint based on the appended header. The encapsulated packet may be transmitted through the tunnel to the second tunnel endpoint. The second tunnel endpoint may receive the encapsulated packet. Cryptographic processing of the encapsulated packet may reveal the packet having a second header. The packet may then be forwarded on an interface toward at least one multicast recipient identified in the second header. | 2009-11-26 |
20090292918 | AUTHENTICATION SYSTEM AND AUTHENTICATION DEVICE - An authentication system is provided with a server device for generating a random number used for authentication and check data obtained by encrypting the random number using an encryption key, an authentication device for authenticating a device to be authenticated by transmitting the random number transmitted from the server device to the device to be authenticated and comparing reply data transmitted from the device to be authenticated with check data transmitted from the server device, and the device to be authenticated for encrypting the random number transmitted from the authentication device using the encryption key and transmitting the encrypted random number as reply data. | 2009-11-26 |
20090292919 | SECURE EXECUTION ENVIRONMENT ON EXTERNAL DEVICE - A device, such as a smartcard, may be externally-connected to a host platform and may be used to enhance or extend security services provided by the host platform's Trusted Platform Module (TPM). The device and the platform exchange keys in order to facilitate reliable identification of the platform by the device and vice versa, and to support cryptographic tunneling. A proxy component on the host device tunnels information between the platform and the device, and also provides the device with access to the TPM's services such as sealing and attestation. The device can provide secure services to the platform, and may condition provision of these services on conditions such as confirming the platform's identity through the exchanged keys, or platform state measurements reported by the TPM. | 2009-11-26 |
20090292920 | Device authentication in a PKI - A method for establishing a link key between correspondents in a public key cryptographic scheme, one of the correspondents being an authenticating device and the other being an authenticated device. The method also provides a means for mutual authentication of the devices. The authenticating device may be a personalized device, such as a mobile phone, and the authenticated device may be a headset. The method for establishing the link key includes the step of introducing the first correspondent and the second correspondent within a predetermined distance, establishing a key agreement and implementing challenge-response routine for authentication. Advantageously, main-in-the middle attacks are minimized. | 2009-11-26 |
20090292921 | METHOD FOR THE ENCRYPTED DATA EXCHANGE AND COMMUNICATION SYSTEM - The embodiments relate to a method for the encrypted data exchange between subscribers of a communication system using cryptography based on elliptical curves, wherein upon a query by a first subscriber a scalar multiplication is calculated by the second subscriber, wherein merely part of the result of the scalar multiplication is returned to the first subscriber as a response. The invention relates to a communication system. | 2009-11-26 |
20090292922 | SYSTEM AND METHOD FOR EXCHANGING SECURE INFORMATION BETWEEN SECURE REMOVABLE MEDIA (SRM) DEVICES - A system and method for exchanging secure information between Secure Removable Media (SRM) devices. An initialization operation is performed between the SRM devices. After a mutual authentication operation is performed between the SRM devices, a secret key is exchanged for secure information exchange. An installation setup operation is then performed to establish an environment for moving rights between the SRM devices, and the rights information can be directly exchanged between the SRM devices by performing a rights installation operation between the SRM devices. | 2009-11-26 |
20090292923 | KEY-IN PROCESSING DEVICE AND METHOD - A key-in processing device for executing a control processing on a basis of information of a key input comprises a determination part for determining what a same key is input continuously, a first storage part for storing information corresponding to an application software that is an object for processing according to the key determined the continuous input, the application software installed on the device, and a notifying part for notifying the application software corresponding to the information stored in the first storage part of information corresponding to the key determined the continuous input. | 2009-11-26 |
20090292924 | MECHANISM FOR DETECTING HUMAN PRESENCE USING AUTHENTICATED INPUT ACTIVITY - When a service request associated with an initiated online service transaction is received, an attestation identifying a human-input activity is requested. Upon receiving a signature attesting the human-input activity, the previously initiated service transaction is authenticated based at least in part on the signature. | 2009-11-26 |
20090292925 | METHOD FOR PROVIDING WEB APPLICATION SECURITY - A method for an HTTP server to decide whether a remote client is victim of a phishing ttack, comprising: —receiving a first HTTP request from the remote client on said HTTP Server; —responding to said first HTTP request, wherein a token is added to the response submitted to said remote client; —receiving a second HTTP request on said HTTP server; —judging whether the second HTTP request includes said token; —judging whether the token originates from said remote client; —processing the HTTP request when said remote client has really issued the second HTTP request. | 2009-11-26 |
20090292926 | System and method for controlling features on a device - Trust between entities participating in an upgrade or enablement/disablement process is established and, to facilitate this remotely and securely, a highly tamper resistant point of trust in the system that is being produced is used. This point of trust enables a more efficient distribution system to be used. Through either a provisioning process or at later stages, i.e. subsequent to installation, manufacture, assembly, sale, etc.; the point of trust embodied as a feature controller on the device or system being modified is given a feature set (or updated feature set) that, when validated, is used to enable or disable entire features or to activate portions of the feature. | 2009-11-26 |
20090292927 | METHODS AND SYSTEMS FOR SINGLE SIGN ON WITH DYNAMIC AUTHENTICATION LEVELS - Method and systems for single sign on with dynamic authentication levels is described. The method include receiving a data request for access to a second application, where the user is already authenticated to the first application at a first authentication level. Application information about the authentication level necessary to access the second application is retrieved. In response to a request, the user provides the further authentication data for accessing the second application. The type of the further authentication data required is based on the first authentication level and the minimum authentication level necessary to access the second application. The user is then authenticated to the second application at the minimum authentication level necessary to access the second application. | 2009-11-26 |
20090292928 | Acquisition and particular association of inference data indicative of an inferred mental state of an authoring user and source identity data - A computationally implemented method includes, but is not limited to: acquiring inference data indicative of an inferred mental state of an authoring user in connection with at least a particular item of an electronic message, acquiring source identity data providing one or more identities of one or more sources that is or are basis, at least in part, for the inference data indicative of the inferred mental state of the authoring user, associating the inference data indicative of the inferred mental state of the authoring user with the particular item; and associating the source identity data providing one or more identities of the one or more sources with the particular item. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure. | 2009-11-26 |
20090292929 | INITIALIZATION OF A MICROPROCESSOR PROVIDING FOR EXECUTION OF SECURE CODE - An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The microprocessor has secure execution mode initialization logic and an authorized public key. The secure execution mode initialization logic provides for initialization of a secure execution mode within the microprocessor. The secure execution mode initialization logic employs an asymmetric key algorithm to decrypt an enable parameter directing entry into the secure execution mode. The authorized public key is used to decrypt the enable parameter, the enable parameter having been encrypted according to the asymmetric key algorithm using an authorized private key that corresponds to the authorized public key. The secure non-volatile memory stores the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292930 | SYSTEM, METHOD AND APPARATUS FOR ASSURING AUTHENTICITY AND PERMISSIBLE USE OF ELECTRONIC DOCUMENTS - A system and method for secure document management including tagging and/or remotely tracking documents exchanged between one or more users and a document repository. In some embodiments, the security policies for documents are determined based at least in part on document content, metadata associated with the document, and/or usage history of the document. | 2009-11-26 |
20090292931 | APPARATUS AND METHOD FOR ISOLATING A SECURE EXECUTION MODE IN A MICROPROCESSOR - An apparatus providing for a secure execution environment, including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to provide for a secure execution mode within the microprocessor for execution of the secure application program. The secure execution mode logic records the state of the microprocessor in a non-volatile indicator register upon entry into the secure execution mode and upon exit from the secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor. | 2009-11-26 |
20090292932 | DEVICE FOR MANAGING ELECTRONIC DEVICES CONSTITUTING STORAGE SYSTEM - A management device that manages a plurality of electronic devices constituting a storage system specifies a power effect unit, through which a path that cannot be closed does not pass, from among a plurality of power effect units present in the storage system (units whose power states are switched independently), and causes the power state of the power effect unit to be transitioned to a power savings state by closing the path passing through the power effect unit. The power effect units are units, the power states of which are switched independently, and are the electronic devices themselves or a part thereof. | 2009-11-26 |
20090292933 | ENHANCING POWER EFFICIENCY IN A WIRELESS INTERNET CARD - A wireless internet card to support enhancing power efficiency. The wireless internet comprises a front end comprising shared frequency resources. The wireless internet card also comprises a first wireless block and a second wireless block. While the first wireless block is in low-power mode, the second wireless block may get access to the shared radio frequency resources without waking-up the first wireless block thus enhancing the power efficiency. The second wireless block sends a request to the first wireless block to use shared radio frequency resources. A coexistence block coupled to the second wireless block and the first wireless block may wait for a time duration to elapse after the request is received and may allow the second wireless block to use the shared radio frequency resources if the time duration is elapsed. | 2009-11-26 |
20090292934 | INTEGRATED CIRCUIT WITH SECONDARY-MEMORY CONTROLLER FOR PROVIDING A SLEEP STATE FOR REDUCED POWER CONSUMPTION AND METHOD THEREFOR - A method comprising determining that a minimum operation level of an integrated circuit ( | 2009-11-26 |
20090292935 | Method, System and Apparatus for Power Management of a Link Interconnect - A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests. | 2009-11-26 |
20090292936 | MICROCOMPUTER HAVING CPU AND PWM TIMER - A microcomputer includes: a CPU executing a predetermined calculation process; and a PWM timer generating a PWM pulse. The PWM timer includes a RAM for storing a duty value of the PWM pulse and a PWM controller for generating the PWM pulse. The PWM controller includes a PWM counter for counting up from a predetermined value as an initial value. The PWM pulse has an unit waveform, which is generated based on comparison between the duty value of the RAM and an output value of the PWM counter. The RAM outputs a new duty value at every comparison without functioning the CPU so that the duty value of the PWM pulse is changed in chronological order. | 2009-11-26 |
20090292937 | PROGRAMMABLE SYSTEM ON A CHIP - A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another. | 2009-11-26 |
20090292938 | Power Management of Components Having Clock Processing Circuits - A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit. In another form, the operation conditions of the VRM or power supply unit are monitored in real-time as a frequency transition is occurring. In addition, control signals to a VRM or power supply may be monitored to control how changes are made to the frequency of a clock signal. Further still, the power available from a VRM or power supply is monitored and a clock signal frequency to one or more system components is controlled to balance the load to the power available from the VRM or power supply. | 2009-11-26 |
20090292939 | BROADCAST/VOD RECEIVER AND VIEWING MANAGEMENT METHOD - According to one embodiment, an information processor comprises a flush memory which stores a main program for executing information processing by using time data acquired through the clock count operation and a sub-program for upgrading a version of the main program of the information processing, a storage memory which stores the time data, and an arithmetic processing unit which executes the main program in starting the processor and executes the sub-program in upgrading the version, wherein the arithmetic processing unit executes the sub-program so as to continue the clock count operation even during execution of the version upgrading, and when the upgrading has completed, restarts the main program so as to restart the clock count operation by using the time data stored in the storage upon an execution start caused by restarting the main program. | 2009-11-26 |
20090292940 | Memory controller, system including the controller, and memory delay amount control method - A memory controller transmits and receives data to and from a memory. The memory controller includes a delay control section deciding a set value indicative of a determined delay amount in response to a result of a comparison between a test data transmitted to the memory and test data received from the memory, and transmitting the decided set value to the memory, a taking-in section receiving the set value stored in the memory, and a delay adjustment section receiving data from the memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section. | 2009-11-26 |
20090292941 | PROOF-GUIDED ERROR DIAGNOSIS (PED) BY TRIANGULATION OF PROGRAM ERROR CAUSES - Systems and methods are disclosed for performing error diagnosis of software errors in a program by from one or more error traces, building a repair program containing one or more modified program semantics corresponding to fixes to observed errors; encoding the repair program with constraints, biases and priortization into a constraint weighted problem; and solving the constraint weighted problem to generate one or more repair solutions, wherein the encoding includes at least one of: a) constraining one or more repairs choices guided by automatically inferring one or more partial specifications of intended program behaviors and program structure; b) biasing one or more repair choices guided by typical programming mistakes; and c) prioritizing the repair solutions based on error locations and possible changes in program semantics. | 2009-11-26 |