48th week of 2009 patent applcation highlights part 11 |
Patent application number | Title | Published |
20090289236 | STABILIZATION OF PHOTOCHROMIC SYSTEMS - Photochromic compositions are disclosed comprising a polymeric material, a photochromic dye, a hydroxyphenyl triazine UV absorber and, optionally, a further light stabilizer selected from the sterically hindered amines. These systems provide a reversible photochromic effect and show improved light stabilization and color fastness. | 2009-11-26 |
20090289237 | Chemiluminescent process and product - The present invention teaches a chemiluminescent device along with a process for its production. The invention specifically relates to a chemiluminescent article of manufacture (FIG. | 2009-11-26 |
20090289238 | Horizontal universal frame lift system - The Horizontal Universal Frame Lift System is compromised of four telescoping posts located in each corner of a vehicle or trailer on which a universal metal frame is mounted to each of the four corners. The telescoping posts are raised and/or lowered with electronic actuators and drive screws. An electronic control module activates the actuators with the use of a toggle switch or hand held remote transmitter. When the actuators are activated with the toggle switch or remote control it raises and/or lowers the frame to the desired position. The frame itself mounts on the top inside of the cargo area of vehicle or trailer and as such a person may also mount any type of cover onto the frame which would also be raised or lowered with the frame. | 2009-11-26 |
20090289239 | CONNECTOR FOR AN INSULATOR TO BE CONNECTED TO A SUPPORT MEMBER - A connector for an insulator to be connected to a support member is disclosed. In one embodiment, the connector includes a plurality of divergent arms. This connector may include a main body, and at least two side wings extending from the main body where each the side wing is configured to engage with at least one of the divergent arms of the support member. The connector may further include at least one strap engagement element configured to engage at least one strap to secure the connector to the support member. | 2009-11-26 |
20090289240 | NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source. | 2009-11-26 |
20090289241 | Phase change memory devices and fabrication methods thereof - In a memory device, a transistor may be formed on a substrate, and a first electrode may be electrically connected thereto. A phase change material film may be vertically formed on the first electrode, and a second electrode may be formed on the phase change material film. | 2009-11-26 |
20090289242 | Phase Change Memory With Tapered Heater - An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. | 2009-11-26 |
20090289243 | SHORT BRIDGE PHASE CHANGE MEMORY CELLS AND METHOD OF MAKING - Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge. | 2009-11-26 |
20090289244 | SEMICONDUCTOR HETEROSTRUCTURE NANOWIRE DEVICES - Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals. | 2009-11-26 |
20090289245 | FACETED CATALYTIC DOTS FOR DIRECTED NANOTUBE GROWTH - Faceted catalytic dots are used for directing the growth of carbon nanotubes. In one example, a faceted dot is formed on a substrate for a microelectronic device. A growth promoting dopant is applied to a facet of the dot using an angled implant, and a carbon nanotube is grown on the doped facet of the dot. | 2009-11-26 |
20090289246 | METHOD FOR PRODUCING AT LEAST ONE MULTILAYER BODY, AND MULTILAYER BODY - The invention concerns a process for the production of a multi-layer body, wherein the multi-layer body includes at least two functional layers on a top side of a carrier substrate, which are structured in register relationship with each other, by a procedure whereby an underside of the carrier substrate is prepared in such a way that in a first region there results a transparency for a first exposure radiation and in at least one second region there results a transparency for at least one second exposure radiation different therefrom in register relationship with the first region, the underside is successively exposed with the first and the at least one second exposure radiation and the first exposure radiation is used for structuring a first functional layer and the at least one second exposure radiation is used for structuring at least one second functional layer on the top side of the carrier substrate. | 2009-11-26 |
20090289247 | Organic-semiconductor-based infrared receiving device - An organic-semiconductor-based infrared receiving device comprises an electrode layer having a positive layer and a negative layer to form an electric field, and a transport layer located between the positive and negative layers and having a first and a second predetermined material combined in a predetermined ratio. The energy of infrared light from a light source is received at an interface between the first and second materials. The thickness of the transport layer can be increased to enhance the light absorbance in the infrared light range to form electron-hole pairs, which are then parted to form a plurality of electrons and holes driven by the electric field to move to the negative layer and the positive layer, respectively, so that a predetermined photocurrent is generated. | 2009-11-26 |
20090289248 | DIOXAANTHANTHRENE COMPOUND AND SEMICONDUCTOR DEVICE - A dioxaanthanthrene compound is represented by structural formula ( | 2009-11-26 |
20090289249 | Oxide Semiconductor, Thin-Film Transistor and Method for Producing the Same - Disclosed is an oxide semiconductor having an amorphous structure, wherein higher mobility and reduced carrier concentration are achieved. Also disclosed are a thin film transistor, a method for producing the oxide semiconductor, and a method for producing the thin film transistor. Specifically disclosed is an oxide semiconductor which is characterized by being composed of an amorphous oxide represented by the following a general formula: In | 2009-11-26 |
20090289250 | System And Method For Manufacturing A Thin-film Device - A thin-film device includes a plurality of circuit components defining an operational region of the thin-film device, an unpatterned channel portion ( | 2009-11-26 |
20090289251 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring. The stacked structure unit has a memory layer and a rectifying element. The rectifying element has a Schottky junction formed on an interface between an electrode and an oxide semiconductor. The electrode includes a metal and the oxide semiconductor includes a metal. | 2009-11-26 |
20090289252 | Light Emitting Element and Display Device Using The Same - An object of the invention is to provide a highly reliable light emitting element with low drive voltage and longer life than a conventional light emitting element, and a display device using the light emitting element. A light emitting element according to the invention comprises a plurality of layers which is interposed between a pair of electrodes, in which at least one of the plurality of layers is formed of a layer containing a light emitting material, and the layer containing a light emitting material is interposed between a layer containing an oxide semiconductor and/or metal oxide and a material having a higher hole transporting property than an electron transporting property, and a layer containing an oxide semiconductor and/or metal oxide, a material having a higher electron transporting property than a hole transporting property and a material which can donate electrons to the material having a higher electron transporting property than a hole transporting property. | 2009-11-26 |
20090289253 | Semiconductor Wafer and Method of Forming Sacrificial Bump Pad for Wafer Probing During Wafer Sort Test - A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps. | 2009-11-26 |
20090289254 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film. | 2009-11-26 |
20090289255 | FLEXIBLE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A flexible display device adapted to prevent a disconnection of pad electrode and a line short-circuit is disclosed. The flexible display device and the manufacturing method thereof according to the present embodiments forms only the barrier film or no layer on the mother substrate in the vicinity of the cut line which divides the mother substrate into the TFT substrate. Even when the mother substrate is pressed using a press machine, cracks or lifts of layers are not generated in the TFT substrate unlike the conventional technology so that a disconnection is not generated in the gate pad electrode or the data pad electrode. Thus, line short-circuits generated as the layers are separated and attached to the TFT substrate can be prevented. | 2009-11-26 |
20090289256 | THIN FILM TRANSISTOR AND DISPLAY DEVICE INCLUDING THIN FILM TRANSISTOR - A thin film transistor with favorable electric characteristics is provided, which includes a gate electrode layer; a first insulating layer covering the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions, which are provided with a distance therebetween and at least partly overlap with the gate electrode layer; a microcrystalline semiconductor layer which is provided over the first insulating layer in part of a channel formation region, and at least partly overlaps with the gate electrode layer and does not overlap with at least one of the pair of impurity semiconductor layers; a second insulating layer between and in contact with the first insulating layer and the microcrystalline semiconductor layer; and an amorphous semiconductor layer over the first insulating layer, covering the second insulating layer and the microcrystalline semiconductor layer. The first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxynitride layer. | 2009-11-26 |
20090289257 | EXPOSURE MASK USING GRAY-TONE PATTERN, MANUFACTURING METHOD OF TFT SUBSTRATE USING THE SAME AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE TFT SUBSTRATE - Disclosed are an exposure mask capable of improving uniformity of a resist film thickness of a half film thickness part and reducing a display defect to increase a manufacturing yield, a method of manufacturing a TFT substrate using the exposure mask and a liquid crystal display comprising the TFT substrate manufactured by the method and having no display defect. The exposure mask includes a light-shielding pattern on a transparent substrate in which a gray-tone area is provided to at least a part of the light-shielding pattern, the gray-tone area having an oblong light-shielding pattern having a width of a submarginal resolution of an exposure apparatus and sandwiched between oblong slit-type transmissive patterns having a width of the submarginal resolution, and a light-shielding rate of the gray-tone area is gradually reduced toward a center of the oblong light-shielding pattern from longitudinal ends thereof. | 2009-11-26 |
20090289258 | Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same - A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device including the same, which allow a size of a grain of a channel region to be increased, can effectively protect the channel region of a semiconductor layer at the time of etching process, and can reduce processing cost. The thin film transistor includes a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer pattern disposed on the gate insulating layer and including a channel region, a source region and a drain region, an etch stop layer pattern disposed on the channel region of the semiconductor layer pattern and having a thickness of 20 to 60nm, and source and drain electrodes disposed on the source and drain regions of the semiconductor layer pattern, respectively. | 2009-11-26 |
20090289259 | PIXEL STRUCTURE OF DISPLAY PANEL AND METHOD OF MAKING THE SAME - A pixel structure of a display panel is provided. The pixel structure includes a first storage capacitor formed by a pixel electrode and a common electrode pattern, and a second storage capacitor formed by an electrode pattern and the common electrode pattern. Accordingly, the storage capacitance is greatly improved without sacrificing the aperture ratio, or the aperture ratio is improved by reducing the area of the storage capacitor while the storage capacitance is maintained. | 2009-11-26 |
20090289260 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THAT - A liquid crystal display device which can reduce or eliminate a display defect is provided. The liquid crystal display device includes a first alignment film formed on one of the pair of substrates; a second alignment film formed on another of the pair of substrates; first projecting portions which are provided to the first alignment film and project into the liquid crystal layer by first constitutional members which constitute a layer below the first alignment film; and second projecting portions which are provided to the second alignment film, face the first projecting portions, and project into the liquid crystal layer by second constitutional members which constitute a layer below the second alignment film, the first projecting portion being set lower than the second projecting portion, and an area of an upper surface of the first projecting portion being set smaller than an area of an upper surface of the second projecting portion. The first alignment film is made of a photo-decomposition-type alignment film material. | 2009-11-26 |
20090289261 | GALLIUM NITRIDE CRYSTAL SUBSTRATE AND METHOD OF PRODUCING SAME - A low-distortion gallium nitride crystal substrate including low dislocation single crystal regions (Z) having a definite c-axis and a definite a-axis, C-plane growth regions (Y) having a c-axis and a-axis parallel to the c-axis and a-axis of the low dislocation single crystal regions (Z), voluminous defect accumulating regions (H) having a c-axis inverse to the c-axis of the low dislocation single crystal regions (Z) and an a-axis parallel with the a-axis of the low dislocation single crystal regions (Z), and 0.1/cm | 2009-11-26 |
20090289262 | JUNCTION BARRIER SCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY - An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing. | 2009-11-26 |
20090289263 | System and Method for Emitter Layer Shaping - Embodiments of an LED disclosed has an emitter layer shaped to a controlled depth or height relative to a substrate of the LED to maximize the light output of the LED and to achieve a desired intensity distribution. In some embodiments, the exit face of the LED may be selected to conserve radiance. In some embodiments, shaping the entire LED, including the substrate and sidewalls, or shaping the substrate alone can extract 100% or approximately 100% of the light generated at the emitter layers from the emitter layers. In some embodiments, the total efficiency is at least 90% or above. In some embodiments, the emitter layer can be shaped by etching, mechanical shaping, or a combination of various shaping methods. In some embodiments, only a portion of the emitter layer is shaped to form the tiny emitters. The unshaped portion forms a continuous electrical connection for the LED. | 2009-11-26 |
20090289264 | Silicon carbide semiconductor device and method of manufacturing the same - An SiC semiconductor device includes a substrate, a drift layer disposed on a first surface of the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a trench penetrating the source region and the base region to the drift layer, a gate insulating layer disposed on a surface of the trench, a gate electrode disposed on a surface of the gate insulating layer, a first electrode electrically coupled with the source region and the base region, a second electrode disposed on the second surface of the substrate, and a second conductivity-type layer disposed at a portion of the base region located under the source region. The second conductivity-type layer has the second conductivity type and has an impurity concentration higher than the base region. | 2009-11-26 |
20090289265 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING AN ELECTRONIC DEVICE - An electronic device comprising at least one die stack having at least a first die (D | 2009-11-26 |
20090289266 | REFLECTION TYPE OPTICAL SENSOR DEVICE - Provided is a reflection type optical sensor device including: a semiconductor light source being formed by providing a light emitting region on a predetermined region of a substrate; and a photo-detection element being integrated on the same substrate as the substrate where the semiconductor light source is formed to surround an outer circumferential surface of the semiconductor light source, and including a light receiving region. When the light emitted from the semiconductor light source is reflected by an external object, the photo-detection element may detect the light to sense the object. Through this, it is possible to reduce cost and ensure a small size. Also, the photo-detection element is constructed to surround the outer circumferential surface of the semiconductor light source, and thus more accurately detect the light. | 2009-11-26 |
20090289267 | SOLID STATE LED BRIDGE RECTIFIER LIGHT ENGINE - A solid-state light engine comprised of light emitting diodes (LEDs) configured into a bridge rectifier with a current limiting module coupled to the LED bridge rectifier. The light engine may be packaged for high temperature operation. Optionally, the LEDs comprise wavelength-converting phosphors with a persistence that is a multiple of the peak to peak current period, to smooth and mask ripple frequency pulsation of emitted light. | 2009-11-26 |
20090289268 | LIGHT EMITTING APPARATUS AND SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus and a light emitting apparatus which are capable of efficiently dissipating the heat generated by a semiconductor device and have high reliability, and a method for manufacturing the same are provided. | 2009-11-26 |
20090289269 | PACKAGING STRUCTURE OF LIGHT EMITTING DIODE - The present invention discloses a light-emitting diode packaging structure, comprising a base; a chip; a first material disposed on at least one side of the chip and having a first refraction index; a second material disposed upon the chip, having a second refraction index, and separated with the first material with an interface therebetween to refract the light refracted from the first material; and a ball lens disposed upon the second material and forming a confined space with the base; whereby, the light emitted from the chip refracts through the first refraction material and the second refraction material and finally emits out from the ball lens. | 2009-11-26 |
20090289270 | GROUP III NITRIDE SEMICONDUCTOR MULTILAYER STRUCTURE AND PRODUCTION METHOD THEREOF - According to the invention it is possible to obtain a flat AlN crystal film seed layer with a high degree of crystallinity, and particularly, a flat AlN crystal film seed layer that is homogeneous throughout can be used even with large substrates having diameters of 100 mm and greater, in order to obtain highly crystalline GaN-based thin-films for highly reliable, high-luminance LED elements and the like. The invention relates to a Group III nitride semiconductor multilayer structure obtained by layering an n-type semiconductor layer, composed of a Group III nitride semiconductor, a luminescent layer and a p-type semiconductor layer, on a sapphire substrate, the Group III nitride semiconductor multilayer structure having an AlN crystal film that is accumulated as the seed layer by sputtering on the sapphire substrate surface, and the AlN crystal film having a grain boundary spacing of 200 nm or greater. The arithmetic mean surface roughness (Ra) of the AlN crystal film surface is preferably no greater than 2 angstrom. The oxygen content of the AlN crystal film is preferably no greater than 5 atomic percent. | 2009-11-26 |
20090289271 | SILICATE-BASED PHOSPHORS AND LED LIGHTING DEVICES USING THE SAME - Disclosed herein is a group of phosphors of the formula | 2009-11-26 |
20090289272 | LIGHT EMITTING DEVICE PACKAGE - Disclosed is a light emitting device package. The light emitting device package includes a semiconductor substrate comprising a first surface at a first depth from an upper surface of the semiconductor substrate and a second surface at a second depth from the first surface; and a light emitting part on the second surface of the semiconductor substrate. | 2009-11-26 |
20090289273 | LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously. | 2009-11-26 |
20090289274 | PACKAGE STRUCTURE OF LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - Provided are a LED package structure and a method of manufacturing the same. The LED package structure includes first and second plate-shaped auxiliary support pieces; a heat-dissipating portion formed upwardly higher than the first and second auxiliary support pieces; a plurality of auxiliary leads connected between each of the auxiliary support pieces and a side surface of the heat-dissipating portion, a portion of each of the plurality of auxiliary leads adjacent to the heat-dissipating portion extending along the same level with the top surface of the heat-dissipating portion; and main leads extending from the auxiliary support pieces to the heat-dissipating portion along the same level with the top surface of the auxiliary leads and spaced apart from the heat-dissipating portion, wherein the heat-dissipating portion, the auxiliary support pieces and the main leads are integrally formed using a conductive metallic material. According to the LED package structure, connection leads are integrally formed with a heat-dissipating portion through perforating or bending a metal plate whose central part is thicker than its peripheral part, followed by molding and cutting process, thereby facilitating and simplifying the manufacturing process. | 2009-11-26 |
20090289275 | Light Emitting Device, Package, Light Emitting Device Manufacturing Method, Package Manufacturing Method and Package Manufacturing Die - Provided is a light emitting device wherein a resin molded body having a circular or an oval recessed section at the center suppresses generation of cracks. A light emitting device ( | 2009-11-26 |
20090289276 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side, an n-type ultrahigh-concentration impurity layer and an n-type high-concentration impurity layer to serve as a cathode are formed. In a guard-ring opposed region located in the cathode and opposite to the guard ring, a cathode-side p-type diffusion region is formed. Accordingly, concentration of the electric current on an outer peripheral end portion of the anode is suppressed. | 2009-11-26 |
20090289277 | POWER SEMICONDUCTOR DEVICE - A plurality of cell structures of a vertical power device are formed at a semiconductor substrate. One cell structure included in the plurality of cell structures and located in a central portion CR of the main surface has a lower current carrying ability than the other cell structure included in the plurality of cell structures and located in an outer peripheral portion PR of the main surface. This provides a power semiconductor device having a long power cycle life. | 2009-11-26 |
20090289278 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a collector layer of a first conductivity type; a semiconductor area of a second conductivity type formed on the collector layer; a base layer of the first conductivity type formed on the semiconductor area; an emitter layer of the second conductivity type formed in an island shape on the base layer; an insulation film formed on the semiconductor area, the base layer and the emitter layer; a gate electrode formed on the insulation film; an emitter electrode formed on the base layer and the emitter layer; a collector electrode formed on the collector layer; and a crystal defect area of the first conductivity type locally formed in the collector layer. A position of a defect concentration peak of the crystal defect area is in the collector layer. An edge of the crystal defect area adjoins the semiconductor area or is located in the semiconductor area. | 2009-11-26 |
20090289279 | METHOD AND APPARATUS FOR BURIED-CHANNEL SEMICONDUCTOR DEVICE - Methods and apparatus of integrating a buried-channel PMOS into a BiCMOS process. The apparatus comprises at least one bipolar transistor and at least one MOS device coupled to the at least one bipolar transistor, such that a gate of the at least one MOS device may be coupled to an emitter of the at least one bipolar transistor. The MOS device comprises a buried channel having mobility means, such as strained silicon for promoting hole mobility in the buried channel, and confinement means, such as a cap layer disposed proximate to the buried channel for limiting leakage of holes from the buried channel. The apparatus may be formed by exposing a substrate in a PMOS, forming a SiGe layer on the substrate, forming an oxide layer on the SiGe layer, masking the PMOS, and removing at least some of the oxide and at least some of the SiGe layer. | 2009-11-26 |
20090289280 | Method for Making Transistors and the Device Thereof - A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors ( | 2009-11-26 |
20090289281 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines. | 2009-11-26 |
20090289282 | SOLID STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transistor for outputting a signal corresponding to the potential of the floating diffusion layer. A low concentration impurity region having an impurity concentration lower than that of the first conductivity type semiconductor region is formed in part of a surface portion of the first conductivity type semiconductor region which is located below a gate electrode of the amplifying transistor and serves as a well region of the amplifying transistor. | 2009-11-26 |
20090289283 | Wafer For Backside Illumination Type Solid Imaging Device, Production Method Thereof And Backside Illumination Solid Imaging Device - A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming a given active layer on a support substrate made of C-containing p-type semiconductor material through an insulating layer. | 2009-11-26 |
20090289284 | High shrinkage stress silicon nitride (SiN) layer for NFET improvement - A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region. | 2009-11-26 |
20090289285 | Semiconductor device and method of fabricating the same - Provided is a semiconductor device including a transistor that has a silicide layer formed over a semiconductor substrate. The gate electrode of each transistor is composed of a polysilicon electrode and the silicide layer formed thereon. Each transistor further has source/drain impurity-diffused layers composed of low-concentration doped regions and high-concentration doped regions, and silicide layers formed over the source/drain impurity-diffused layers. The surface of each silicide layer is positioned above the surface of the semiconductor substrate. The silicide layers contain a silicidation-suppressive metal, and have a concentration profile of the silicidation-suppressive metal over a region of the silicide layers ranging from the surface to a predetermined depth, such as increasing the concentration from the surface of each silicide layer in the depth-wise direction of the semiconductor substrate. | 2009-11-26 |
20090289286 | CMOS Image Sensor Having improved signal eficiency and method for manufacturing the same - A CMOS image sensor and a method for manufacturing the same improves signal efficiency by reducing a dark signal, and includes a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area, and a field oxide in the substrate for electrical isolation within the image area. | 2009-11-26 |
20090289287 | CMOS Image Sensor and Method of Manufacturing the Same - Disclosed herein are a CMOS image sensor and a method of manufacturing the same, which can reduce current leakage through a plug connecting a photodiode and a transfer transistor to each other, and thereby provide low dark current levels. The CMOS image sensor includes a first epitaxial layer on or in a substrate. A photodiode PD is in the first epitaxial layer. A second epitaxial layer is on or in the substrate (e.g., on the first epitaxial layer). A shallow trench isolation region is in an area of the substrate. A plug is in the substrate (e.g., the second epitaxial layer) connected with the photodiode and spaced apart from the shallow trench isolation region. A transfer transistor having a gate electrode and source/drain regions is connected with the plug. | 2009-11-26 |
20090289288 | INTEGRATED CIRCUIT INCLUDING AN INSULATING STRUCTURE BELOW A SOURCE/DRAIN REGION AND METHOD - An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate. | 2009-11-26 |
20090289289 | DRAM CELL WITH MAGNETIC CAPACITOR - A DRAM cell includes a substrate, a transistor, and a magnetic capacitor. The substrate is composed of semiconductor material with a main surface, the transistor is formed at the main surface, and the magnetic capacitor is formed in a metal layer. The magnetic capacitor includes a first magnetic layer, a dielectric layer formed on the surface of the first magnetic layer, and a second magnetic layer formed on the surface of the dielectric layer. The dielectric layer is a non-conductive material and the first magnetic layer and the second magnetic layer are formed by an alloy of CoNiFe. | 2009-11-26 |
20090289290 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 2009-11-26 |
20090289291 | SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER - A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap. | 2009-11-26 |
20090289292 | Semiconductor Memory Device and Method for Forming Capacitor Thereof - A semiconductor device that is capable of preventing a storage node bunker defect or a defect due to loss of a barrier layer, and a method for forming a capacitor thereof. The semiconductor memory device includes a contact hole formed in an interlayer dielectric layer on a semiconductor substrate; a barrier layer formed on the bottom of the contact hole; a first storage node contact formed of a conductive layer that fills the rest of the contact hole; a second storage node contact formed on the result formed with the first storage node contact so as to be shifted by a given distance from the first storage node contact; an insulation layer formed between the second storage node contacts; a storage electrode connected with the second storage node contact and isolated on a per cell basis; and dielectric layer and plate electrode for covering the storage electrode. | 2009-11-26 |
20090289293 | SEMICONDUCTOR DEVICE HAVING TRI-GATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor. | 2009-11-26 |
20090289294 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes: a semiconductor layer; a trench dug downward from the surface of the semiconductor layer; a source region formed on the surface layer portion of the semiconductor layer adjacently to a first side of the trench in a prescribed direction; a drain region formed on the surface layer portion of the semiconductor layer adjacently to a second side of the trench opposite to the first side in the prescribed direction; a first insulating film formed on the bottom surface and the side surface of the trench; a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film; a second insulating film formed on the floating gate; and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film. | 2009-11-26 |
20090289295 | Semiconductor Device and Method of Fabricating the same - The invention relates to semiconductor devices and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer, the second conductive layer, the dielectric layer, and the first conductive layer are patterned so that the first conductive layer partially remains to prevent the tunnel insulating layer from being exposed. Sidewalls of the gate electrode layer are etched. A first passivation layer is formed on the entire surface including the sidewalls of the gate electrode layer. At this time, a thickness of the first passivation layer formed on the sidewalls of the gate electrode layer is thicker than that of the first passivation layer formed in other areas. A cleaning process is performed to thereby remove byproducts occurring in the etch process. A gate pattern is formed by etching the first passivation layer, the first conductive layer, and the tunnel insulating layer. | 2009-11-26 |
20090289296 | Semiconductor Device and Method of Fabricating the same - A semiconductor device and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer and the second conductive layer are patterned. A first passivation layer is formed on sidewalls of the gate electrode layer. Gate patterns are formed by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed. A second passivation layer is formed on the entire surface along a surface of the gate patterns including the first passivation layer. | 2009-11-26 |
20090289297 | CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A charge trap-type non-volatile memory device, and related method, includes forming over a substrate a tunnel insulating layer, a charge trapping layer, a dielectric layer, and a conductive layer for a gate electrode; forming a gate electrode by selectively etching the conductive layer for the gate electrode; forming a spacer including a first spacer and a second spacer on a sidewall of the gate electrode, the second spacer being formed of material different from that of the first spacer; and etching the dielectric layer and the charge trapping layer by using the spacer as an etching barrier, thereby preventing an attack to the gate electrode when etching the charge trapping layer and thus enhancing reliability and stability of transistors. In addition, in one or more embodiments, a sidewall of the charge trapping layer pattern is formed vertically, thereby preventing formation of a tail and an attack to the substrate. | 2009-11-26 |
20090289298 | SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR - An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region. | 2009-11-26 |
20090289299 | HIGH DENSITY HIGH PERFORMANCE POWER TRANSISTOR LAYOUT - A power transistor comprises a gate region, a source region, and a drain region. The gate region comprises a first line portion, a second line portion, and a third line portion. The first line portion couples to the second line portion so as to form a first V-shaped structure. The second line portion couples to the third line portion so as to form a second V-shaped structure. The first line portion, the second line portion, and the third line portion form a N-shaped structure. | 2009-11-26 |
20090289300 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r | 2009-11-26 |
20090289301 | LASER ANNEALING OF METAL OXIDE SEMICONDUCTORON TEMPERATURE SENSITIVE SUBSTRATE FORMATIONS - A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the temperature sensitive substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device includes at least a layer of metal oxide semiconductor material, an interface of the metal oxide layer with a dielectric layer, and a gate metal layer adjacent the layer of metal oxide semiconductor material and the interface. The method then includes the step of at least partially annealing the layer of metal oxide semiconductor material by heating the adjacent gate metal layer with pulses of infra red or visible light radiation. | 2009-11-26 |
20090289302 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device | 2009-11-26 |
20090289303 | METHOD AND APPARATUS FOR FABRICATING AN ULTRA THIN SILICON ON INSULATOR - In one embodiment, the invention is a method and apparatus for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas. | 2009-11-26 |
20090289304 | CO-INTEGRATION OF MULTI-GATE FET WITH OTHER FET DEVICES IN CMOS TECHNOLOGY - The present invention relates to a CMOS circuit device on a SOI substrate with an oriented silicon surface, comprising on a first substrate region a FET that has a FET channel region of a first conductivity type, and comprising on a second substrate region a FinFET that has a FinFET channel region of a second conductivity type which is opposite to the first conductivity type. The invention also relates to a method for fabricating such a CMOS circuit device. The fabrication of the multi-gate planar FET comprises, at an intermediate step, forming a FET channel stack with an alternating sequence of layers of a FET material and of a sacrificial material and containing main FET-channel faces, which have the same orientation as the oriented silicon surface. According to the invention, a co-integration of multi-gate FET devices is achieved that ensures high carrier mobilities for both NMOS and PMOS FETs. | 2009-11-26 |
20090289305 | ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION - A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs. | 2009-11-26 |
20090289306 | LATERAL OXIDATION WITH HIGH-K DIELECTRIC LINER - Disclosed are methods of making and using a high-K dielectric liner to facilitate the lateral oxidation of a high-K gate dielectric, integrated circuit structures containing the high-K dielectric liner and/or oxidized high-K gate dielectric, and other associated methods. | 2009-11-26 |
20090289307 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a semiconductor substrate having a SRAM region; an N-type element region formed in the SRAM region on the semiconductor substrate and including N-type source/drain regions; a P-type element region formed in the SRAM region on the semiconductor substrate so as to be substantially parallel to the N-type element region and including P-type source/drain regions; P-type well contact connections and N-type well contact connections formed on both sides of the N-type and P-type element regions in a longitudinal direction outside the SRAM region on the semiconductor substrate, respectively; an element isolation region for isolating the N-type element region, the P-type element region, the P-type well contact connection and the N-type well contact connection; a P-type well continuously formed under the N-type element region and the P-type well contact connection in the semiconductor substrate, and an N-type well continuously formed under the P-type element region and the N-type well contact connection in the semiconductor substrate. | 2009-11-26 |
20090289308 | SEMICONDUCTOR DEVICE WITH A TRANSISTOR HAVING DIFFERENT SOURCE AND DRAIN LENGTHS - A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length. | 2009-11-26 |
20090289309 | METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS - A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts. | 2009-11-26 |
20090289310 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region. | 2009-11-26 |
20090289311 | Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error - A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer. | 2009-11-26 |
20090289312 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a first region, a source region, a second region, a drain region, a gate insulating layer, a field insulating layer and a gate electrode. The first region is formed in a surface area of a semiconductor substrate. The source region is formed in a surface area of the first region. The second region is formed in a surface area of the semiconductor substrate. The drain region is formed in a surface region of the second region. The gate insulating layer is formed on a front surface of the semiconductor substrate between the source region and the second region. The field insulating layer is formed in a surface area of the semiconductor substrate between the drain region and the gate insulating layer. The gate electrode covers part of the gate insulating layer and part of the field insulating layer. The field insulating layer has, in its portion overlapping the gate electrode, such a step that a portion of the field insulating layer between the step and the gate insulating layer is thinner than the rest of the field insulating layer. | 2009-11-26 |
20090289313 | MICRO ELECTRIC MECHANICAL SYSTEM DEVICE AND METHOD OF PRODUCING THE SAME - A MEMS device comprises a substrate, an island-shaped first insulating layer formed on the substrate, a second insulating film formed on the top and side surfaces of the first insulating layer and the top surface of the substrate, and having a thickness smaller than that of the first insulating layer, a metal layer formed on the second insulating film in an island-shaped region where the first insulating layer is formed, and a MEMS system element formed on the metal layer. | 2009-11-26 |
20090289314 | MICRO-ELECTROMECHANICAL RESONANCE DEVICE WITH PERIODIC STRUCTURE - A Micro Electro Mechanical Systems resonance device includes a substrate, and an input electrode, connected to an alternating current source having an input frequency. The device also includes an output electrode, and at least one anchoring structure, connected to the substrate. The device further includes a vibratile structure connected to an anchoring structure by at least one junction, having a natural acoustic resonant frequency. The vibration under the effect of the input electrode, when it is powered, generates, on the output electrode, an alternating current wherein the output frequency is equal to the natural frequency. The vibratile structure and/or the anchoring structure includes a periodic structure. The periodic structure includes at least first and second zones different from each other, and corresponding respectively to first and second acoustic propagation properties. | 2009-11-26 |
20090289315 | SEMICONDUCTOR SENSOR AND MANUFACTURING METHOD OF SENSOR BODY FOR SEMICONDUCTOR SENSOR - A semiconductor sensor of which the thickness may be reduced and a method of manufacturing a sensor body for the semiconductor sensor are provided. A total length L | 2009-11-26 |
20090289316 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device comprises a distributed Bragg reflector layer of a first conductivity type, an optical absorption layer, and a semiconductor layer of a second conductivity type, sequentially formed on a semiconductor substrate; wherein said Bragg reflection layer of the first conductivity type has first semiconductor layers having a band gap wavelength larger than the wavelength of incident light, and second semiconductor layers having a band gap wavelength smaller than the wavelength of incident light; and an optical layer thickness of each of said first semiconductor layers is larger than the optical layer thickness of each of said second semiconductor layers. | 2009-11-26 |
20090289317 | PACKAGING STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured. | 2009-11-26 |
20090289318 | ELECTRONICS DEVICE PACKAGE AND FABRICATION METHOD THEREOF - Embodiments provide an electronic device package and a method for fabricating thereof. A semiconductor chip has a substrate. A supporting brick is separated from the substrate by a certain distance. A bonding pad having a surface is disposed across the substrate and the supporting brick. | 2009-11-26 |
20090289319 | SEMICONDUCTOR DEVICE - A semiconductor device, that is approximately identical in package size to a semiconductor chip, such as a W-CSP, is devised to secure a wider area for sealing such as laser marking. A semiconductor substrate has a plurality of via electrodes extending from the bottom of the semiconductor substrate to top electrodes, a bottom wire net formed at the bottom of the semiconductor substrate such that the bottom wire net is connected to the via electrodes, and an insulative film covering the bottom wire net. A sealing area having a sealing mark is disposed at the bottom of the semiconductor substrate. The sealing area is located such that the outer circumference of the sealing area is spaced apart from the bottom wire net in a direction parallel to a sealing mark forming surface, and the outer circumference of the sealing area is disposed at the edge of the semiconductor substrate. | 2009-11-26 |
20090289320 | FAST P-I-N PHOTODETECTOR WITH HIGH RESPONSITIVITY - A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon. | 2009-11-26 |
20090289321 | Thermal sensing and reset protection for an integrated circuit chip - There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state. | 2009-11-26 |
20090289322 | MEMORY DEVICES HAVING A CARBON NANOTUBE - In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory. | 2009-11-26 |
20090289323 | Apparatus For Implementing Multiple Integrated Circuits Using Different Gate Oxide Thicknesses On A Single Integrated Circuit Die - An apparatus comprising plurality of functional integrated circuit blocks, each manufactured with different oxide thicknesses on a monolithic integrated circuit die, is described. Using different gate oxide thicknesses for different functional integrated circuit blocks provides reduced power consumption and increases performance in processing systems. Several embodiments comprising different combinations of functional integrated circuit blocks, including processor cores and memory elements, are presented. | 2009-11-26 |
20090289324 | MASK OVERHANG REDUCTION OR ELIMINATION AFTER SUBSTRATE ETCH - A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature. | 2009-11-26 |
20090289325 | Semiconductor Device with Crack Prevention Ring - A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process. | 2009-11-26 |
20090289326 | Semiconductor device and method of fabricating the same - A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug. | 2009-11-26 |
20090289327 | CAPACITOR INSULATING FILM AND METHOD FOR FORMING THE SAME, AND CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor insulating film includes a laminated structure in which aluminum oxide films and titanium dioxide films are alternately laminated, wherein the titanium dioxide films each have a rutile crystal structure, and the ratio of the total thickness of the aluminum oxide films to the total thickness of the laminated structure ranges from 3 to 8%. | 2009-11-26 |
20090289328 | INSULATION FILM FOR CAPACITOR ELEMENT, CAPACITOR ELEMENT AND SEMICONDUCTOR DEVICE - An insulation film includes niobium, oxygen and a metal element, and the insulation film has a band gap width of larger than 4.2 eV, and at least a portion of the insulation film includes an amorphous structure. | 2009-11-26 |
20090289329 | Differential Varactor - A high-Q differential varactor includes reduced inner spacing dimensions between differential fingers. | 2009-11-26 |
20090289330 | GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE, SUBSTRATE FOR GROUP III NITRIDE SEMICONDUCTOR DEVICE, AND METHODS OF MAKING SAME - A III group nitride semiconductor substrate according to the present invention is fabricated by forming a metal film or metal nitride film | 2009-11-26 |
20090289331 | Semiconductor chip and semiconductor device, and method of manufacturing the same - At least a part of an outer edge of a surface where a circuit forming region, for example, of a semiconductor substrate that forms a semiconductor chip is arranged (a region surrounded by a scribe line around the circuit forming region) is cut or polished, so as to form a smooth slope is chamfered non-parallel and non-vertical to the circuit forming region. Then, a code indicating management information is assigned to the slope. Further, a plurality of semiconductor chips are stacked to manufacture a semiconductor device. | 2009-11-26 |
20090289332 | METHODS FOR MAKING SUBSTRATES AND SUBSTRATES FORMED THEREFROM - A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition. | 2009-11-26 |
20090289333 | Annealing a Buffer Layer for Fabricating Electronic Devices on Compliant Substrates - A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing. | 2009-11-26 |
20090289334 | Metal gate structure and method of manufacturing same - A method of manufacturing a metal gate structure includes providing a substrate ( | 2009-11-26 |
20090289335 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD AND TIE BAR - An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield. | 2009-11-26 |