| 47th week of 2012 patent applcation highlights part 43 |
| Patent application number | Title | Published |
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| 20120295373 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - To provide a method of manufacturing a nitride semiconductor light emitting element, which has a small number of steps and thus, can improve productivity, the method of manufacturing a nitride semiconductor light emitting element including a nitride semiconductor light emitting element structure having an n-type nitride semiconductor layer and a p-side nitride semiconductor layer which are laminated on a substrate, an n-side pad electrode connecting surface and a p-side pad electrode connecting surface which are formed on the same plane of the substrate; a n-side pad electrode on the n-side pad electrode connecting surface; and a p-side pad electrode on the p-side pad electrode connecting surface, and in the manufacturing method, a pad electrode layer forming step, a resist pattern forming step, a pad electrode layer etching step, a protective layer forming step and a resist pattern removing step are sequentially performed. | 2012-11-22 |
| 20120295374 | LIGHT EMITTING DEVICE, PACKAGE, LIGHT EMITTING DEVICE MANUFACTURING METHOD, PACKAGE MANUFACTURING METHOD AND PACKAGE MANUFACTURING DIE - A light emitting device includes a resin molded body having a circular or an oval recessed section at the center suppresses generation of cracks. The device is provided with a light emitting element, a first resin molded body having a plurality of outer surfaces, and a recessed section at the center. First and second leads are electrically connected to the light emitting element, and a second resin molded body is applied in the recessed section. The light emitting element is placed on the first lead, and the surface of the second resin molded resin forms a light emitting surface. A gate notch is formed on an extended line of a normal line on one point on a circular cross-section of the recessed section in the normal line direction. | 2012-11-22 |
| 20120295375 | PEELING METHOD AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING THE PEELING METHOD - The present invention provides a simplifying method for a peeling process as well as peeling and transcribing to a large-size substrate uniformly. A feature of the present invention is to peel a first adhesive and to cure a second adhesive at the same time in a peeling process, thereby to simplify a manufacturing process. In addition, the present invention is to devise the timing of transcribing a peel-off layer in which up to an electrode of a semiconductor are formed to a predetermined substrate. In particular, a feature is that peeling is performed by using a pressure difference in the case that peeling is performed with a state in which plural semiconductor elements are formed on a large-size substrate. | 2012-11-22 |
| 20120295376 | METHOD FOR MANUFACTURING A LED ARRAY DEVICE, AND LED ARRAY DEVICE MANUFACTURED THEREBY - Disclosed are a method for fabricating a GaN LED array device for optogenetics and a GaN LED array device fabricated thereby. | 2012-11-22 |
| 20120295377 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor device. The method can include removing a growth substrate from a structure body by using a first treatment material. The structure body has the growth substrate, a buffer layer formed on the growth substrate, and the nitride semiconductor layer formed on the buffer layer. A support substrate is bonded to the nitride semiconductor layer. The method can include reducing thicknesses of the buffer layer and the nitride semiconductor layer by using a second treatment material different from the first treatment material after removing the growth substrate. | 2012-11-22 |
| 20120295378 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of making a semiconductor light-emitting device including (A) a light-emitting portion by laminating in sequence a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (B) a first electrode electrically connected to the first compound semiconductor layer; (C) a transparent conductive material layer on the second compound semiconductor layer; (D) an insulating layer on a transparent conductive material layer; and (E) a second reflective electrode that on the transparent conductive material layer and on the insulating layer in a continuous manner, wherein, that the areas of the active layer, the transparent conductive material layer, the insulating layer, and the second electrode S | 2012-11-22 |
| 20120295379 | DEPOSITION MASK, DEPOSITION APPARATUS, AND DEPOSITION METHOD - A deposition mask | 2012-11-22 |
| 20120295380 | ETCHANT AND METHOD OF MANUFACTURING AN ARRAY SUBSTRATE USING THE SAME - An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH | 2012-11-22 |
| 20120295381 | METHOD OF MANUFACTURING ORGANIC EL DISPLAY UNIT - A method of manufacturing an organic EL display unit and an organic EL display unit capable of improving light emitting efficiency and life of blue are provided. A hole injection layer are formed on a lower electrode. For a red organic EL device and a green organic EL device, a hole transport layer, a red light emitting layer, and a green light emitting layer made of a polymer material are formed. A hole transport layer made of a low molecular material is formed on the hole injection layer of a blue organic EL device. A blue light emitting layer made of a low molecular material is formed on the red light emitting layer, the green light emitting layer, and the hole transport layer for the blue organic EL device. An electron transport layer, an electron injection layer, and an upper electrode are sequentially formed on the blue light emitting layer. | 2012-11-22 |
| 20120295382 | METHOD OF LIFT-OFF PATTERNING THIN FILMS IN SITU EMPLOYING PHASE CHANGE RESISTS - Method for making a patterned thin film of an organic semiconductor. The method includes condensing a resist gas into a solid film onto a substrate cooled to a temperature below the condensation point of the resist gas. The condensed solid film is heated selectively with a patterned stamp to cause local direct sublimation from solid to vapor of selected portions of the solid film thereby creating a patterned resist film. An organic semiconductor film is coated on the patterned resist film and the patterned resist film is heated to cause it to sublime away and to lift off because of the phase change. | 2012-11-22 |
| 20120295383 | METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Disclosed is a method of producing a semiconductor wafer, which includes: placing a wafer ( | 2012-11-22 |
| 20120295384 | Temperature Stable MEMS Resonator - One embodiment of the present inventions sets forth a method for decreasing a temperature coefficient of frequency (TCF) of a MEMS resonator. The method comprises lithographically defining slots in the MEMS resonator beams and filling the slots with a compensating material (for example, an oxide) wherein the temperature coefficient of Young's Modulus (TCE) of the compensating material has a sign opposite to a TCE of the material of the resonating element. | 2012-11-22 |
| 20120295385 | LIGHTLY-DOPED DRAINS (LDD) OF IMAGE SENSOR TRANSISTORS USING SELECTIVE EPITAXY - Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors. | 2012-11-22 |
| 20120295386 | STRATIFIED PHOTODIODE FOR HIGH RESOLUTION CMOS IMAGE SENSOR IMPLEMENTED WITH STI TECHNOLOGY - A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages. | 2012-11-22 |
| 20120295387 | METHOD FOR PRODUCING A THIN-FILM PHOTOVOLTAIC CELL HAVING AN ETCHANT-RESISTANT ELECTRODE AND AN INTEGRATED BYPASS DIODE AND A PANEL INCORPORATING THE SAME - A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least first, second and third series-connected cells on a support, each cell being a laminated structure comprising a junction layer including semiconducting material of a first and second type, a front electrode formed of a transparent conductive oxide resistant to an etchant disposed in electrical contact with the semiconducting material of the first type, and a back electrode in electrical contact with the semiconducting material of the second type. A portion of both the back electrode and the junction layer are separated from a selected parent solar cell. Using the separated portion of the back electrode the semiconducting material of the second type of the separated portion of the junction layer is connected to the semiconducting material of the first type of any one chosen solar cell in the array. | 2012-11-22 |
| 20120295388 | LARGE AREA CONCENTRATOR LENS STRUCTURE AND METHOD - A solar module includes a substrate member, a plurality of photovoltaic strips arranged in an array configuration overlying the substrate member, and a concentrator structure comprising extruded glass material operably coupled to the plurality of photovoltaic strips. A plurality of elongated convex regions are configured within the concentrator structure. The plurality of elongated convex regions are respectively coupled to the plurality of photovoltaic strips. Each of the plurality of elongated convex regions includes a length and a convex surface region characterized by a radius of curvature, each of the elongated convex regions being configured to have a magnification ranging from about 1.5 to about 5. A coating material rendering the glass self-cleaning overlies the plurality of elongated convex regions. | 2012-11-22 |
| 20120295389 | IMAGE SENSOR HAVING WAVE GUIDE AND METHOD FOR MANUFACTURING THE SAME - An image sensor having a wave guide includes a semiconductor substrate formed with a photodiode and a peripheral circuit region; an anti-reflective layer formed on the semiconductor substrate; an insulation layer formed on the anti-reflective layer; a wiring layer formed on the insulation layer and connected to the semiconductor substrate; at least one interlayer dielectric stacked on the wiring layer; and a wave guide connected to the insulation layer by passing through the interlayer dielectric and the wiring layer which are formed over the photodiode. | 2012-11-22 |
| 20120295390 | SINGLE-CRYSTALLINE SILICON ALKALINE TEXTURING WITH GLYCEROL OR ETHYLENE GLYCOL ADDITIVES - Alternative additives that can be used in place of isopropyl alcohol in aqueous alkaline etchant solutions for texturing a surface of a single-crystalline silicon substrate are provided. The alternative additives do not have volatile constituents, yet can be used in an aqueous alkaline etchant solution to provide a pyramidal shaped texture surface to the single-crystalline silicon substrate that is exposed to such an etchant solution. Also provided is a method of forming a textured silicon surface. The method includes immersing a single-crystalline silicon substrate into an etchant solution to form a pyramid shaped textured surface on the single-crystalline silicon substrate. The etchant solution includes an alkaline component, silicon (etched into the solution as a bath conditioner) and glycerol or ethylene glycol as an additive. The textured surface of the single-crystalline silicon substrate has (111) faces that are now exposed. | 2012-11-22 |
| 20120295391 | METHOD OF MANUFACTURING A SOLAR CELL - A method of manufacturing a solar cell includes preparing a base substrate having a first conductive type; diffusing an impurity having a second conductive type (opposite the first conductive type) into the base substrate to form an emitter layer having a first impurity concentration on the base substrate and a by-product layer on the emitter layer; irradiating a laser beam onto the emitter layer corresponding to a first region of the base substrate to form a front contact portion having a second impurity concentration higher than the first impurity concentration; irradiating the laser beam onto the by-product layer to remove the by-product layer corresponding to the first region; removing the by-product layer from an area outside of the first region; forming an anti-reflection layer on the base substrate; forming a front electrode on the anti-reflection layer corresponding to the first region; and forming a back electrode on the base substrate. | 2012-11-22 |
| 20120295392 | METHOD FOR PRODUCING AN ARRAY OF THIN-FILM PHOTOVOLTAIC CELLS HAVING A TOTALLY SEPARATED INTEGRATED BYPASS DIODE AND METHOD FOR PRODUCING A PANEL INCORPORATING THE SAME - A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least three series-connected solar cells, each cell being a laminated structure including semiconducting material of first and second types, a front electrode in contact with the material of the first type, and a back electrode in contact with the material of the second type. The bypass diode is formed by total separation from a selected parent cell. The material of the first type of the diode is connected to the material of the second type of any one chosen solar cell in the array. The material of the second type of the diode is connected with the material of the first type of the one chosen solar cell in the array so that the diode is connected in parallel and in opposition to the one chosen solar cell. | 2012-11-22 |
| 20120295393 | METHOD FOR PRODUCING AN ARRAY OF THIN-FILM PHOTOVOLTAIC CELLS HAVING AN ETCHANT-RESISTANT ELECTRODE AND AN INTEGRATED BYPASS DIODE ASSOCIATED WITH A PLURALITY OF CELLS AND A PANEL INCORPORATING THE SAME - An array of series-connected solar cells is formed on a support layer with at least a two cells being adjacent and a third solar cell being either adjacent or separated from the second solar cell. A portion of the photovoltaic junction layer is separated from the first solar cell. The semiconducting material of the first type of the separated portion is electrically connected with the semiconducting material of the second type of the second solar cell through physical contact between the front electrode of the first cell and the back electrode of the second cell. The material of the second type of the separated portion of the junction layer is connected with the semiconducting material of the first type of the third cell to define a bypass diode that is in parallel and in opposition to the second and the third solar cells. | 2012-11-22 |
| 20120295394 | METHOD FOR REAR POINT CONTACT FABRICATION FOR SOLAR CELLS - A method for forming holes in the backside dielectric layer of solar cells for fabrication of rear point contact. The backside dielectric layer is coated with a layer of carbon. A shadow mask is placed over the carbon layer and reactive ion etch (RIE) is used to transfer the holes in the shadow mask to the carbon layer, to thereby form a carbon mask. The shadow mask is then removed and RIE is used to transfer the holes from the carbon mask to the dielectric layer. The carbon mask is then removed by, e.g., ashing. | 2012-11-22 |
| 20120295395 | METHOD FOR PRODUCING AN ARRAY OF THIN-FILM PHOTOVOLTAIC CELLS HAVING A TOTALLY SEPARATED INTEGRATED BYPASS DIODE ASSOCIATED WITH A PLURALITY OF CELLS AND METHOD FOR PRODUCING A PANEL INCORPORATING THE SAME - A method for producing an array a thin-film solar cell with a cell level integrated bypass diode, the includes forming at least three series-connected solar cells; totally separating a bypass diode from a selected parent solar cell; connecting the semiconducting material of the first type of the photovoltaic junction layer of the bypass diode with the semiconducting material of the second type of any one chosen solar cell in the array; and connecting the semiconducting material of the second type of the photovoltaic junction layer of the bypass diode with the semiconducting material of the first type of any other chosen solar cell in the array so that the bypass diode is connected in parallel and in opposition to both the one chosen solar cell and the other chosen solar cell. | 2012-11-22 |
| 20120295396 | SYNTHESIZING PHOTOVOLTAIC THIN FILMS OF HIGH QUALITY COPPER-ZINC-TIN ALLOY WITH AT LEAST ONE CHALCOGEN SPECIES - A method for synthesizing a thin film of copper, zinc, tin, and a chalcogen species (“CZTCh” or “CZTSS”) with well-controlled properties. The method includes depositing a thin film of precursor materials, e.g., approximately stoichiometric amounts of copper (Cu), zinc (Zn), tin (Sn), and a chalcogen species (Ch). The method then involves re-crystallizing and grain growth at higher temperatures, e.g., between about 725 and 925 degrees K, and annealing the precursor film at relatively lower temperatures, e.g., between 600 and 650 degrees K. The processing of the precursor film takes place in the presence of a quasi-equilibrium vapor, e.g., Sn and chalcogen species. The quasi-equilibrium vapor is used to maintain the precursor film in a quasi-equilibrium condition to reduce and even prevent decomposition of the CZTCh and is provided at a rate to balance desorption fluxes of Sn and chalcogens. | 2012-11-22 |
| 20120295397 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Stable electrical characteristics and high reliability are provided to a semiconductor device including an oxide semiconductor. In a process of manufacturing a transistor including an oxide semiconductor film, an amorphous oxide semiconductor film is formed, and oxygen is added to the amorphous oxide semiconductor film, so that an amorphous oxide semiconductor film containing excess oxygen is formed. Then, an aluminum oxide film is formed over the amorphous oxide semiconductor film, and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that a crystalline oxide semiconductor film is formed. | 2012-11-22 |
| 20120295398 | ION IMPLANT MODIFICATION OF RESISTIVE RANDOM ACCESS MEMORY DEVICES - An improved method of fabricating a resistive memory device is disclosed. A resistive memory includes a bottom electrode, a top electrode and a resistive material layer interposed therebetween. Interfaces are formed between the resistive material layer and the respective top and bottom electrodes. Ions are implanted in the device to change the characteristics of one or both of these interfaces, thereby improving the performance of the memory device. These ions may be implanted after the three layers are fabricated, during the fabrication of these layers, or at both times. | 2012-11-22 |
| 20120295399 | OXIDE-BASED THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, ZINC OXIDE ETCHANT, AND A METHOD OF FORMING THE SAME - Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession. | 2012-11-22 |
| 20120295400 | METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The method for producing a semiconductor chip with an adhesive film includes preparing a laminate of a divided semiconductor wafer, an adhesive film and a dicing tape, the adhesive film having a thickness in the range of 1 to 15 μm and a tensile elongation at break of less than 5%, and the tensile elongation at break being less than 110% of the elongation at a maximum load; and dividing the adhesive film for a semiconductor by picking up the plurality of semiconductor chips in a laminating direction of the laminate. The divided semiconductor wafer has been obtained by cutting the semiconductor wafer in a thickness less than that of the semiconductor wafer and by grinding the other side of the semiconductor wafer on which no cut is formed to reach the cut. | 2012-11-22 |
| 20120295401 | METHODS FOR FORMING ASSEMBLIES AND MULTI CHIP MODULES INCLUDING STACKED SEMICONDUCTOR DICE - An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first semiconductor device is disclosed. Spacers space the active surface of the first semiconductor device substantially a predetermined distance apart from the back side of the second semiconductor device. Discrete conductive elements are extended between the active surface of the first semiconductor device and the substrate prior to positioning of the second semiconductor device. Intermediate portions of the discrete conductive elements pass through an aperture formed between the active surface of the first semiconductor device, the back side of the second semiconductor device, and two of the spacers positioned therebetween. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed. | 2012-11-22 |
| 20120295402 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, FLIP CHIP PACKAGE HAVING THE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE FLIP CHIP PACKAGE - A semiconductor device can include a semiconductor chip, a protective layer pattern, an under bump metallurgy (UBM) layer, and conductive bumps. The semiconductor chip can include a pad and a guard ring. The protective layer pattern can be formed on the semiconductor chip to expose the pad and the guard ring. The UBM layer can be formed on the protective layer and can directly make contact with the pad and the guard ring. The conductive bumps can be formed on a portion of the UBM layer on the pad. Thus, the UBM layer and the guard ring can directly make contact with each other, so that a uniform current can be provided to the UBM layer on the pad regardless of a thick difference of different portions of the UBM layer. | 2012-11-22 |
| 20120295403 | FABRICATION METHOD OF EMBEDDED CHIP SUBSTRATE - An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip. | 2012-11-22 |
| 20120295404 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board. | 2012-11-22 |
| 20120295405 | METHODS FOR VACUUM ASSISTED UNDERFILLING - Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered. | 2012-11-22 |
| 20120295406 | CARBON NANOTUBE DISPERSION LIQUID AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A carbon nanotube dispersion liquid obtained by mixing carbon nanotubes, a first organic solvent that is a nonpolar solvent, and a second organic solvent that has a polarity higher than that of this first organic solvent and is compatible with this first organic solvent. | 2012-11-22 |
| 20120295407 | THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A thin film transistor (TFT) and a method of manufacturing the same are provided, the TFT including a gate insulating layer on a gate. A channel may be formed on a portion of the gate insulating layer corresponding to the gate. A metal material may be formed on a surface of the channel. The metal material crystallizes the channel. A source and a drain may contact side surfaces of the channel. | 2012-11-22 |
| 20120295408 | METHOD FOR MANUFACTURING MEMORY DEVICE - The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor. | 2012-11-22 |
| 20120295409 | METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions. | 2012-11-22 |
| 20120295410 | METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE - A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer. | 2012-11-22 |
| 20120295411 | CLOSED CELL TRENCH POWER MOSFET STRUCTURE AND METHOD TO FABRICATE THE SAME - A closed cell trench MOSFET structure having a drain region of a first conductivity type, a body of a second conductivity type, a trenched gate, and a plurality of source regions of the first conductivity type is provided. The body is located on the drain region. The trenched gate is located in the body and has at least two stripe portions and a cross portion. A bottom of the stripe portions is located in the drain region and a bottom of the cross portion is in the body. The source regions are located in the body and at least adjacent to the stripe region of the trenched gate. | 2012-11-22 |
| 20120295412 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: providing a substrate having an active area and a gate structure on the active area and formed with a first interlayer dielectric layer thereon, wherein the first interlayer dielectric layer has a first open to expose a portion of a surface of the active area, and an upper surface of the first interlayer dielectric layer is substantially flush with an upper surface of the gate; filling the first open with a first conductive material to form a first portion of contact; forming a second interlayer dielectric layer over the first interlayer dielectric layer, the second interlayer dielectric layer having a second open to substantially expose an upper part of the first portion of the contact in the first open; and filling the second open with a second conductive material to form a second portion of the contact. | 2012-11-22 |
| 20120295413 | METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY ELEMENT AND METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a non-volatile semiconductor memory element including a variable resistance element and a non-ohmic element. The variable resistance element includes a first electrode, a variable resistance layer, and a shared electrode. The non-ohmic element includes the shared electrode, a semiconductor or insulator layer, and a second electrode. The method includes: forming the first electrode on a substrate; forming the variable resistance layer on the first electrode; forming the shared electrode by nitriding a front surface of the variable resistance layer; forming the semiconductor or insulator layer on the shared electrode; and forming the second electrode. In the forming of the shared electrode, a front surface of a transition metal oxide is nitrided by a plasma nitriding process to form the shared electrode comprising a transition metal nitride. | 2012-11-22 |
| 20120295414 | METHODS FOR PRODUCING STACKED ELECTROSTATIC DISCHARGE CLAMPS - Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1. | 2012-11-22 |
| 20120295415 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, comprising bonding a first principal surface of a substrate to a supporting substrate through a light-to-heat conversion film, and removing a portion of the light-to-heat conversion film exposed on the supporting substrate. A method of manufacturing a semiconductor device, comprising forming a light-to-heat conversion film on a supporting substrate, bonding a semiconductor substrate to the supporting substrate, so that the light-to-heat conversion film extends outside the semiconductor substrate, performing an anti-contamination treatment on the light-to-heat conversion film, and separating the supporting substrate and the semiconductor substrate from each other. | 2012-11-22 |
| 20120295416 | ADHESIVE SHEET FOR PRODUCING SEMICONDUCTOR DEVICE - An object of the present invention is to provide an adhesive sheet that can capture cations mixed in from outside during various processes of manufacturing a semiconductor device to prevent deterioration in electrical characteristics of a semiconductor device to be manufactured and to improve product reliability. It is an adhesive sheet for producing a semiconductor device, in which when 2.5 g of the adhesive sheet is soaked in 50 ml of an aqueous solution containing 10 ppm of copper ions, and the solution is left at 120° C. for 20 hours, the concentration of copper ions in the aqueous solution is 0 to 9.9 ppm. | 2012-11-22 |
| 20120295417 | SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING - A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed. | 2012-11-22 |
| 20120295418 | METHODS FOR IMPROVED GROWTH OF GROUP III NITRIDE BUFFER LAYERS - Methods are disclosed for growing high crystal quality group III-nitride epitaxial layers with advanced multiple buffer layer techniques. In an embodiment, a method includes forming group III-nitride buffer layers that contain aluminum on suitable substrate in a processing chamber of a hydride vapor phase epitaxy processing system. A hydrogen halide or halogen gas is flowing into the growth zone during deposition of buffer layers to suppress homogeneous particle formation. Some combinations of low temperature buffers that contain aluminum (e.g., AlN, AlGaN) and high temperature buffers that contain aluminum (e.g., AlN, AlGaN) may be used to improve crystal quality and morphology of subsequently grown group III-nitride epitaxial layers. The buffer may be deposited on the substrate, or on the surface of another buffer. The additional buffer layers may be added as interlayers in group III-nitride layers (e.g., GaN, AlGaN, AlN). | 2012-11-22 |
| 20120295419 | METHODS FOR DEPOSITING A MATERIAL ATOP A SUBSTRATE - Methods for depositing a material atop a substrate are provided herein. In some embodiments, a method of depositing a material atop a substrate may include exposing a substrate to a silicon containing gas and a reducing gas; increasing a flow rate of the silicon containing gas while decreasing a flow rate of the reducing gas to form a first layer; and depositing a second layer atop the first layer. | 2012-11-22 |
| 20120295420 | SEMICONDUCTOR DEVICES WITH REDUCED STI TOPOGRAPHY BY USING CHEMICAL OXIDE REMOVAL - A thermal oxide may be removed in semiconductor devices prior to performing complex manufacturing processes, such as forming sophisticated gate electrode structures, by using a gaseous process atmosphere instead of a wet chemical etch process, wherein the masking of specific device regions may be accomplished on the basis of a resist mask. | 2012-11-22 |
| 20120295421 | LOW TEMPERATURE SELECTIVE EPITAXY OF SILICON GERMANIUM ALLOYS EMPLOYING CYCLIC DEPOSIT AND ETCH - Cyclic deposit and etch (CDE) selective epitaxial growth employs an etch chemistry employing a combination of hydrogen chloride and a germanium-containing gas to provide selective deposition of a silicon germanium alloy at temperatures lower than 625° C. High strain epitaxial silicon germanium alloys having a germanium concentration greater than 35 atomic percent in a temperature range between 400° C. and 550° C. A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium-containing precursor gas is employed to deposit the silicon germanium alloy with thickness uniformity and at a high deposition rate during each deposition step in this temperature range. Presence of the germanium-containing gas in the etch chemistry enhances the etch rate of the deposited silicon germanium alloy material during the etch step. | 2012-11-22 |
| 20120295422 | METHOD FOR FABRICATING InGaN-BASED MULTI-QUANTUM WELL LAYERS - A method for fabricating quantum wells by using indium gallium nitride (InGaN) semiconductor material includes fabricating a potential well on a layered group III-V nitride structure at a first predetermined temperature in a reactor chamber by injecting into the reactor chamber an In precursor gas and a Ga precursor gas. The method further includes, subsequent to the fabrication of the potential well, terminating the Ga precursor gas, maintaining a flow of the In precursor gas, and increasing the temperature in the reactor chamber to a second predetermined temperature while adjusting the In precursor gas flow rate from a first to a second flow rate. In addition, the method includes annealing and stabilizing the potential well at the second predetermined temperature while maintaining the second flow rate. The method also includes fabricating a potential barrier above the potential well at the second predetermined temperature while resuming the Ga precursor gas. | 2012-11-22 |
| 20120295423 | GRAPHENE BASED THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE - A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices. | 2012-11-22 |
| 20120295424 | METHOD FOR DESIGNING SOI WAFER AND METHOD FOR MANUFACTURING SOI WAFER - A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength λ comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength λ of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation. | 2012-11-22 |
| 20120295425 | METHODS OF FABRICATING DEVICES BY LOW PRESSURE COLD WELDING - Methods of transferring a metal and/or organic layer from a patterned stamp, preferably a soft, elastomeric stamp, to a substrate are provided. The patterned metal or organic layer may be used for example, in a wide range of electronic devices. The present methods are particularly suitable for nanoscale patterning of organic electronic components. | 2012-11-22 |
| 20120295426 | CMOS WITH CHANNEL P-FINFET AND CHANNEL N-FINFET HAVING DIFFERENT CRYSTALLINE ORIENTATIONS AND PARALLEL FINS - A method for fabricating an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. The method includes bonding a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A first plurality of fins and a second plurality of fins are created. A spacer is formed around each fin in the first plurality of fins and second plurality of fins. A set of regions of the second layer between each fin in the first plurality of fins and the second plurality of fins are recessed to form a base with exposed sidewalls under each fin in the first plurality of fins and the second plurality of fins. The base under each fin and a set of exposed regions between each fin is oxidized. | 2012-11-22 |
| 20120295427 | HIGH THROUGHPUT CYCLICAL EPITAXIAL DEPOSITION AND ETCH PROCESS - Methods of selective formation leave high quality epitaxial material using a repeated deposition and selective etch process. During the deposition process, an inert carrier gas is provided with a silicon-containing source without hydrogen carrier gas. After depositing silicon-containing material, an inert carrier gas is provided with an etchant to selectively etch deposited material without hydrogen. The deposition and etch processes can be repeated until a desired thickness of silicon-containing material is achieved. Using the processes described within, it is possible to maintain temperature and pressure conditions, as well as inert carrier gas flow rates, to provide for increased throughput. The inert flow can be constant, or etch rates can be increased by reducing inert flow for the etch phases of the cycles. | 2012-11-22 |
| 20120295428 | METHODS FOR PRETREATMENT OF GROUP III-NITRIDE DEPOSITIONS - Embodiments of the present disclosure relate to methods for pretreatment of substrates and group III-nitride layers for manufacturing devices such as light emitting diodes (LEDs), laser diodes (LDs) or power electronic devices. One embodiment of the present disclosure provides a method including providing one or more substrates having an aluminum containing surface in a processing chamber and exposing a surface of each of the one or more substrates having an aluminum containing surface to a pretreatment gas mixture to form a pretreated surface. The pretreatment gas mixture includes ammonia (NH | 2012-11-22 |
| 20120295429 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas. | 2012-11-22 |
| 20120295430 | METHOD FOR PROCESSING A SUBSTRATE HAVING A NON-PLANAR SUBSTRATE SURFACE - A technique for conformal processing of a substrate having a non-planar surface is disclosed. The technique includes several stages. In a first stage, some surfaces of the substrate are effectively processed. During a second stage, these surfaces are treated to limit or eliminate further processing of these surfaces. During a third stage, other surfaces of the substrate are processed. In some applications, the surfaces that are perpendicular, or substantially perpendicular to the flow of particles are processed in the first and second stages, while other surfaces are processed in the third stage. In some embodiments, the second stage includes the deposition of a film on the substrate. | 2012-11-22 |
| 20120295431 | METHOD FOR ETCHING GATE STACK - A method for etching a metal gate stack is provided. The method includes forming a gate stack on a substrate, where the gate stack includes a metal gate. A wet etch process is performed on the gate stack. The wet etch process includes submersing the substrate with the gate stack in an aqueous solution composed of a wet etchant and an oxidizer, removing the substrate from the solution and rinsing the solution from the etched gate stack. | 2012-11-22 |
| 20120295432 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes forming an interlayer insulating layer over the semiconductor substrate of a cell region, and forming gate structures over the semiconductor substrate of a peripheral region. Reserved bit line regions are formed in the cell region by etching the interlayer insulating layer, and gates are formed by etching the gate structures in the peripheral region. A capping insulating layer and an isolation layer are formed over the reserved bit line regions and the gates, the isolation layer of the cell region is removed, and an etch-back process is performed on the capping insulating layer, and bit lines are formed in the respective reserved bit line regions. Semiconductor device yields can be enhanced because patterns having a fine critical dimension can be formed in peripheral regions with an increased degree of integration. | 2012-11-22 |
| 20120295433 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 2012-11-22 |
| 20120295434 | SOLDER COLLAPSE FREE BUMPING PROCESS OF SEMICONDUCTOR DEVICE - A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps. | 2012-11-22 |
| 20120295435 | PATTERN TRANSFER METHOD - In one embodiment, a pattern transfer method includes forming a photoreactive resin on a substrate to be processed. The method further includes pressing a mold against the photoreactive resin, the mold including a transparent substrate having a concave-convex pattern, and a light-blocking film provided on a part of surfaces of the concave-convex pattern. The method further includes irradiating the photoreactive resin with light through the mold in a state in which the mold is pressed against the photoreactive resin. The method further includes baking the photoreactive resin in a state in which the mold is pressed against the photoreactive resin after irradiating the photoreactive resin with the light. The method further includes releasing the mold from the photoreactive resin after baking the photoreactive resin. The method further includes rinsing the photoreactive resin with a rinsing solution after releasing the mold. | 2012-11-22 |
| 20120295436 | FORMATION OF A ZINC PASSIVATION LAYER ON TITANIUM OR TITANIUM ALLOYS USED IN SEMICONDUCTOR PROCESSING - Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl | 2012-11-22 |
| 20120295437 | METHOD FOR FABRICATING THROUGH-SILICON VIA STRUCTURE - A method for fabricating through-silicon via structure is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a through-silicon via in the semiconductor substrate; covering a liner in the through-silicon via; performing a baking process on the liner; forming a barrier layer on the liner; and forming a through-silicon via electrode in the through-silicon via. | 2012-11-22 |
| 20120295438 | COPPER INTERCONNECTION, METHOD FOR FORMING COPPER INTERCONNECTION STRUCTURE, AND SEMICONDUCTOR DEVICE - A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers. | 2012-11-22 |
| 20120295439 | Metal-Semiconductor Intermixed Regions - In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure. | 2012-11-22 |
| 20120295440 | LASER MATERIAL REMOVAL METHODS AND APPARATUS - Embodiments of the present invention generally provide methods and apparatus for material removal using lasers in the fabrication of solar cells. In one embodiment, an apparatus is provided that removes portions of a dielectric layer deposited on a solar cell substrate according to a desired pattern. In certain embodiments, methods for removing a portion of a material via a laser without damaging the underlying substrate are provided. In one embodiment, the intensity profile of the beam is adjusted so that the difference between the maximum and minimum intensity within a spot formed on a substrate surface is reduced to an optimum range. In one example, the substrate is positioned such that the peak intensity at the center versus the periphery of the substrate is lowered. In one embodiment, the pulse energy is improved to provide thermal stress and physical lift-off of a desired portion of a dielectric layer. | 2012-11-22 |
| 20120295441 | METHOD FOR FORMING HARD MASK IN SEMICONDUCTOR DEVICE FABRICATION - A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask. | 2012-11-22 |
| 20120295442 | Chemical mechanical polishing pad having a low defect window - A chemical mechanical polishing pad having a polishing layer with an integral window and a polishing surface adapted for polishing a substrate selected from a magnetic substrate, an optical substrate and a semiconductor substrate, wherein the formulation of the integral window provides improved defectivity performance during polishing. Also provided is a method of polishing a substrate using the chemical mechanical polishing pad. | 2012-11-22 |
| 20120295443 | METHOD FOR RECLAIMING SEMICONDUCTOR WAFER AND POLISHING COMPOSITION - Provided is a polishing composition used for polishing a semiconductor wafer surface having a step in order to planarize the wafer surface and thereby reclaiming the semiconductor wafer. The polishing composition contains at least a step eliminating agent, which is adsorbed to the surface of the semiconductor wafer and acts to prevent etching of bottom portion of the step on the wafer surface during polishing. The step eliminating agent is, for example, a water-soluble polymer or a surfactant, and more specifically, a polyvinyl alcohol, a polyvinyl pyrrolidone, a polyethylene glycol, a cellulose, a carboxylic acid surfactant, a sulfonic acid surfactant, a phosphate ester surfactant, or an oxyalkylene polymer. | 2012-11-22 |
| 20120295444 | TECHNIQUES FOR FORMING 3D STRUCTURES - A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer. | 2012-11-22 |
| 20120295445 | Methods of Fabricating Substrates - A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed. | 2012-11-22 |
| 20120295446 | METHOD FOR SINGLE SIDE TEXTURING - A method for single side texturing of a crystalline semiconductor substrate ( | 2012-11-22 |
| 20120295447 | Compositions and Methods for Texturing of Silicon Wafers - Pre-texturing composition for texturing silicon wafers having one or more surfactants. Methods of texturing silicon wafers having the step of wetting said wafer with a pre-texturing composition having one or more surfactants followed by a texturing step. | 2012-11-22 |
| 20120295448 | DIELECTRIC NANOCOMPOSITES AND METHODS OF MAKING THE SAME - Techniques related to nanocomposite dielectric materials are generally described herein. These techniques may be embodied in apparatuses, systems, methods and/or processes for making and using such material. An example process may include: providing a film having a plurality of nanoparticles and an organic medium; comminuting the film to form a particulate; and applying the particulate to a substrate. The example process may also include providing a nanoparticle film having nanoparticles and voids located between the nanoparticles; contacting the film with a vapor containing an organic material; and curing the organic material to form the nanocomposite dielectric film. Various described techniques may provide nanocomposite dielectric materials with superior nanoparticle dispersion which may result in improved dielectric properties. | 2012-11-22 |
| 20120295449 | Method of Depositing Dielectric Film by ALD Using Precursor Containing Silicon, Hydrocarbon, and Halogen - A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule. | 2012-11-22 |
| 20120295450 | ROTARY ELECTRICAL CONTACT DEVICE AND METHOD FOR PROVIDING CURRENT TO AND/OR FROM A ROTATING MEMBER - Examples of rotary electrical connectors include a first pair and a second pair of opposing sheaves coupled together by intersecting first shaft connecting the first pair of opposing sheaves and a second shaft connecting the second pair of opposing sheaves, and at least partially electrically conductive belt disposed about respective perimeters of the first pair and second pair of opposing sheaves and adapted to remain in contact with at least a portion of the respective perimeters of the sheaves during motion of said sheaves. In example devices, one of the plurality of sheaves may remain stationary during operation of the device while the remaining sheaves rotate and/or orbit around a center axis of the stationary sheave, the device being configured to couple current between a stationary power source and a rotating member through the electrically conductive belt. | 2012-11-22 |
| 20120295451 | Magnetic connecting device - The present invention relates to a magnetic connecting device, which is magnetically and electrically coupled to an external device via a communication-type magnetic connector and is configured to transfer operating power to the external device after checking the external device using communication when the external device is coupled to the connecting device, thus ensuring convenience and safety in use. The magnetic connecting device includes a plurality of power terminals magnetically coupled to a connector of an external device and configured to transfer power to the external device, and at least one communication terminal arranged adjacent to the plurality of power terminals and configured to come into contact with the connector of the external device and to transmit or receive data when the external device is coupled. | 2012-11-22 |
| 20120295452 | DAUGHTER CARD ASSEMBLIES - A removable daughter card assembly including a circuit board having a leading edge. The daughter card assembly also includes connector modules that are configured to be mounted to the circuit board proximate to the leading edge. The connector modules face in an insertion direction for engaging corresponding mating connectors when advanced in the insertion direction. The card assembly also includes an elongated stiffener that is configured to be mounted to the circuit board. The stiffener includes a plurality of support walls and a bridge member that couples to each one of the support walls. The support walls are secured to the circuit board. The bridge member extends substantially parallel to and proximate to the leading edge and is dimensioned to prevent bowing along the leading edge. At least two of the support walls comprise alignment features that are configured to engage corresponding guide features of a communication system. | 2012-11-22 |
| 20120295453 | TALL MEZZANINE CONNECTOR - A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto. The mezzanine connector comprises a and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member. | 2012-11-22 |
| 20120295454 | PRINTED CIRCUIT BOARD ASSEMBLY CHIP PACKAGE COMPONENT AND SOLDERING COMPONENT - A printed circuit board assembly (PCBA) chip package component includes: a module board and an interface board. A first soldering pad is set on the bottom of the module board, a second soldering pad is set on top of the interface board, and the second soldering pad is of a castle-type structure. The first soldering pad includes a first soldering area, a second soldering area, and a connection bridge that connects the first soldering area and the second soldering area. The first soldering area corresponds to a top surface of the second soldering pad, and when the first soldering area is soldered to second soldering pad, the second soldering area is located outside the second soldering pad. | 2012-11-22 |
| 20120295455 | GROUNDING UNIT FOR HIGH-FREQUENCY CONNECTOR AND HIGH-FREQUENCY CONNECTOR MODULE HAVING THE SAME - A grounding unit for a high-frequency connector is provided, wherein the grounding unit may include a grounding unit body configured to be selectively fixed to the high-frequency connector; and a grounding fixation unit configured to be connected to the grounding unit body, to be in pressure contact with a grounding region of a printed circuit board (PCB) under elastic force applied in proportion to a thickness of the PCB, and to electrically connect the high-frequency connector to the grounding region. | 2012-11-22 |
| 20120295456 | SOCKET, A PLUG, AND AN ASSEMBLY - A plug and socket assembly comprising (i) a socket that includes a mating means disposed thereon, and an electrical contact on the socket, and (ii) a plug that includes a matching means for mating with the mating means disposed on the socket, and a conducting terminal for coupling electrically to the electrical contact on the socket. The matching means is configured to be adjustable between a compatible mode and an incompatible mode. When in the compatible mode, the matching means allows the electrical contact to contact the conducting terminal, and when in the incompatible mode, the matching means substantially prevents the electrical contact from contacting the conducting terminal. | 2012-11-22 |
| 20120295457 | MAGNETIC CLOSURE FOR ELECTRICAL SOCKET - An electrical socket comprising an electrical receptacle, a cover for the receptacle, a hinge coupling the cover to the receptacle so that the cover can pivot toward and away from an opening in the receptacle to allow insertion of an electrical plug into the receptacle. A paired combination is provided comprising a magnet and a magnet attractive region on ones of the cover and receptacle causing the cover to be attracted to the receptacle when the cover gets to a predetermined distance from the receptacle thereby causing the cover to be closed on the receptacle by magnetic attraction when the plug is not inserted. | 2012-11-22 |
| 20120295458 | Method and Apparatus Pertaining to Movement of a SIM-Card Tray - An apparatus comprises an assembly and a SIM-card tray configured to move, at least partially, into and out of the assembly to thereby selectively electrically connect and disconnect a SIM card that is disposed in the SIM-card tray to and from at least one electrical connector. A biasing member automatically urges movement of the SIM-card tray with respect to at least one of moving the SIM-card tray into the assembly and out of the assembly. By one approach this biasing member comprises a spring. By one approach this spring can serve to both automatically urge movement of the SIM-card tray into the assembly and out of the assembly. These teachings will accommodate a SIM-card tray configured to accommodate a micro-SIM card. These teachings will also accommodate a personal communication device having the aforementioned components. | 2012-11-22 |
| 20120295459 | ELECTRONIC DEVICE CONNECTING STRUCTURE AND FUNCTION EXPANSION DEVICE - For connecting devices, an electromagnetic interference (EMI) connecting portion includes a conductor connected to a first EMI shield. An electrostatic discharge (ESD) contact portion electrically connects to a second EMI shield through a high-impedance element. The ESD contact portion electrically connects the EMI connecting portion to the second EMI shield through the high-impedance element as the ESD contact portion initially contacts the EMI connecting portion during hot docking. The ESD contact portion subsequently moves in response to the initial contact to contact a low-impedance element electrically connected to the second EMI shield and connect the EMI connecting portion to the second EMI shield through the low-impedance element. | 2012-11-22 |
| 20120295460 | VEHICLE-SIDE CONNECTOR - A vehicle-side connector ( | 2012-11-22 |
| 20120295461 | TERMINAL FITTING AND CONNECTOR - A terminal fitting ( | 2012-11-22 |
| 20120295462 | CONNECTOR WITH LOCKING MECHANISMS - A connector of a cable (e.g., a 30-pin connector) can be used to facilitate various security-related and other functionalities. For example, a connector can include security locking mechanisms for engaging or locking the connector to a portable electronic device. A connector can additionally support the transmission of security signals, data signals, power, and/or the like. An unlocking tool can be used to disengage a connector locked to the portable electronic device. More specifically, the unlocking tool can be applied to a connector and cause the locking mechanisms of the connector to release such that the connector can be freely disconnected from a connected portable electronic device. | 2012-11-22 |
| 20120295463 | LOW-INSERTION-FORCE CONNECTOR ASSEMBLY - For connection and disconnection of both connectors with ease and assurance in a narrow work space and connection, and for disconnection of a safety circuit unit without mistakes and in a saved-space, a low-insertion-force connector assembly | 2012-11-22 |
| 20120295464 | COAXIAL CONNECTOR - A male coaxial connector of the present invention comprises a conductive insert and a coupling nut. The conductive insert has a front end with an annular flange. The coupling nut includes an inner surface defining a bore, wherein the bore at least partially surrounds the conductive insert and is configured to receive a provided female coaxial connector. The coupling nut further includes a locking member extending from its inner surface. The male connector further comprises a torque washer formed from fiber-reinforced rubber and disposed between the flange of the conductive insert and the locking member. When the coupling nut engages a female coaxial connector, the locking member and the torque washer are compressed against the flange of the insert. The compressed locking member and the compressed torque washer each maintain a tension force between the male and female connectors to help prevent separation of the male and female connectors. The male coaxial connector can be configured to be coupled to an end of the coaxial cable by, for example, crimping or compression. | 2012-11-22 |
| 20120295465 | COAXIAL CONNECTOR WITH INTEGRATED LOCKING MEMBER - A male coaxial connector according to the present invention comprises a conductive insert and a coupling nut. The conductive insert has a front end with an annular flange. The coupling nut includes an inner surface defining a bore, wherein the bore at least partially surrounds the conductive insert and is configured to receive a female coaxial connector. The coupling nut further includes a locking member extending from its inner surface. When the coupling nut of the male connector engages a female coaxial connector, the locking member is compressed against the flange of the insert and maintains a tension force between the male and female connectors to help prevent them from separating. The male coaxial connector can be configured to be coupled to an end of the coaxial cable by, for example, crimping or compression. | 2012-11-22 |
| 20120295466 | COAXIAL CONNECTOR WITH TORQUE WASHER - A male coaxial connector of the present invention comprises a conductive insert and a coupling nut. The conductive insert has a front end with an annular flange. The coupling nut includes an inner surface defining a bore, wherein the bore at least partially surrounds the conductive insert and is configured to receive a female coaxial connector. The coupling nut further includes an annular flange extending from the inner surface. The male connector also includes a torque washer, preferably formed from fiber-reinforced rubber. The torque washer is disposed between the flange of the conductive insert and the flange of the coupling nut. When the coupling nut engages a female coaxial connector, the torque washer is compressed between the flange of the coupling nut and the flange of the insert. The compressed torque washer maintains a tension force between the male and female connectors to help prevent their separation. The male coaxial connector can be configured to be coupled to an end of the coaxial cable by, for example, crimping or compression. | 2012-11-22 |
| 20120295467 | CONNECTOR AND CONNECTOR ASSEMBLY - A male universal serial bus (USB) connector includes a connection terminal and a locking piece. The locking piece includes a mounting piece fixed to a top wall of the connection terminal, an operation piece, and a connecting piece connected between the operation piece and the mounting piece. A wedge extends on the mounting piece and can be engaged in a female USB connector to prevent the male USB connector from disengaging from the female USB connector. | 2012-11-22 |
| 20120295468 | SPRINGLESS ELECTRIC GATE TENSIONER - The springless electric gate tensioner receptacle and plug connect and axially adjust relative to each other in order to mechanically tension the electrical fence gate wire. The receptacle has a resilient, electrically non-conductive insulator covering handle and conductive sleeve portions. Spaced apart bayonet slots are disposed axially along diametrically opposite sides of the sleeve. The plug includes a solid cylindrical conductive member extending from a handle, the handle being covered with a resilient, electrically non-conductive insulator. Bayonet lugs extend from the plug near its end and project outwardly in a radial direction approximately 180° from each other. Conducting rings extend from the plug and receptacle handles for connection to the gate and fence wires. The projecting bayonet lugs of the plug twist-lock engage user selectable receptacle slots, thereby tensioning the gate wire. | 2012-11-22 |
| 20120295469 | ELECTRONIC DEVICE HAVING CONNECTOR - An electronic device having a connector includes a case including an open end and a closed end, a circuit board housed in the case, an inner connector including a conduction terminal which is connected to the circuit board via a connecting portion, an outer connector including a contact face coming in contact with the circuit board, the outer connector being engaged with the open end, and a play preventing portion fixed in the case, and engaged with the circuit board by causing the circuit board to move from the open end to the closed end, wherein a position of the contact face is determined so that the circuit board is pressed by the contact face so as to cause the circuit board to be engaged with the play preventing portion, and the outer connector does not press the inner connector toward the closed end. | 2012-11-22 |
| 20120295470 | CONNECTOR AND JIG FOR CONNECTOR - A connector is provided which is lightened and has a simplified structure. | 2012-11-22 |
| 20120295471 | VARIABLE CANTED COIL SPRING CROSS SECTION - A canted coil spring includes a plurality of canted coils generally canted relative to a centerline extending through the coils. At least one coil when viewed in the direction of the centerline appears to have a non-elliptical shape and a non-circular shape when the at least one coil is in the unbiased state. The plurality of coils is generally canted at a first coil angle relative to the center line. The at least one coil includes at least one section canted at a second coil angle relative to the centerline. The second coil angle is different from the first coil angle when the at least one coil is in an unbiased state. | 2012-11-22 |
| 20120295472 | PORTABLE UNIVERSAL SERIAL BUS (USB) CABLE KEYCHAIN ASSEMBLY WITH CARABINER CLIP - A cable assembly for connecting a portable electronic device to a host device includes an upstream connector section comprising a upstream connector housing, an upstream connector secured to the upstream connector housing, and a downstream connector section comprising a downstream connector housing, a first downstream connector secured to the downstream connector housing, and a second downstream connector secured to the downstream connector housing. The cable assembly further includes a main body section having an attachment mechanism comprising a through hole formed in the main body, the through hole including on one side a carabiner clip comprising a spring-loaded hinged inwardly movable outer portion completing the through hole. | 2012-11-22 |
